4 * I2C adapter for the PXA I2C bus access.
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly separated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/init.h>
26 #include <linux/time.h>
27 #include <linux/sched.h>
28 #include <linux/delay.h>
29 #include <linux/errno.h>
30 #include <linux/interrupt.h>
31 #include <linux/i2c-pxa.h>
33 #include <linux/of_device.h>
34 #include <linux/of_i2c.h>
35 #include <linux/platform_device.h>
36 #include <linux/err.h>
37 #include <linux/clk.h>
38 #include <linux/slab.h>
40 #include <linux/i2c/pxa-i2c.h>
44 struct pxa_reg_layout {
59 * I2C registers definitions
61 static struct pxa_reg_layout pxa_reg_layout[] = {
81 /* no isar register */
85 static const struct platform_device_id i2c_pxa_id_table[] = {
86 { "pxa2xx-i2c", REGS_PXA2XX },
87 { "pxa3xx-pwri2c", REGS_PXA3XX },
88 { "ce4100-i2c", REGS_CE4100 },
91 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
97 #define ICR_START (1 << 0) /* start bit */
98 #define ICR_STOP (1 << 1) /* stop bit */
99 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
100 #define ICR_TB (1 << 3) /* transfer byte bit */
101 #define ICR_MA (1 << 4) /* master abort */
102 #define ICR_SCLE (1 << 5) /* master clock enable */
103 #define ICR_IUE (1 << 6) /* unit enable */
104 #define ICR_GCD (1 << 7) /* general call disable */
105 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */
106 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */
107 #define ICR_BEIE (1 << 10) /* enable bus error ints */
108 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
109 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
110 #define ICR_SADIE (1 << 13) /* slave address detected int enable */
111 #define ICR_UR (1 << 14) /* unit reset */
112 #define ICR_FM (1 << 15) /* fast mode */
114 #define ISR_RWM (1 << 0) /* read/write mode */
115 #define ISR_ACKNAK (1 << 1) /* ack/nak status */
116 #define ISR_UB (1 << 2) /* unit busy */
117 #define ISR_IBB (1 << 3) /* bus busy */
118 #define ISR_SSD (1 << 4) /* slave stop detected */
119 #define ISR_ALD (1 << 5) /* arbitration loss detected */
120 #define ISR_ITE (1 << 6) /* tx buffer empty */
121 #define ISR_IRF (1 << 7) /* rx buffer full */
122 #define ISR_GCAD (1 << 8) /* general call address detected */
123 #define ISR_SAD (1 << 9) /* slave address detected */
124 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */
128 wait_queue_head_t wait;
130 unsigned int msg_num;
131 unsigned int msg_idx;
132 unsigned int msg_ptr;
133 unsigned int slave_addr;
135 struct i2c_adapter adap;
137 #ifdef CONFIG_I2C_PXA_SLAVE
138 struct i2c_slave_client *slave;
141 unsigned int irqlogidx;
145 void __iomem *reg_base;
146 void __iomem *reg_ibmr;
147 void __iomem *reg_idbr;
148 void __iomem *reg_icr;
149 void __iomem *reg_isr;
150 void __iomem *reg_isar;
152 unsigned long iobase;
153 unsigned long iosize;
156 unsigned int use_pio :1;
157 unsigned int fast_mode :1;
160 #define _IBMR(i2c) ((i2c)->reg_ibmr)
161 #define _IDBR(i2c) ((i2c)->reg_idbr)
162 #define _ICR(i2c) ((i2c)->reg_icr)
163 #define _ISR(i2c) ((i2c)->reg_isr)
164 #define _ISAR(i2c) ((i2c)->reg_isar)
167 * I2C Slave mode address
169 #define I2C_PXA_SLAVE_ADDR 0x1
178 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
181 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
183 printk("%s %08x: ", prefix, val);
185 const char *str = val & bits->mask ? bits->set : bits->unset;
192 static const struct bits isr_bits[] = {
193 PXA_BIT(ISR_RWM, "RX", "TX"),
194 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"),
195 PXA_BIT(ISR_UB, "Bsy", "Rdy"),
196 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"),
197 PXA_BIT(ISR_SSD, "SlaveStop", NULL),
198 PXA_BIT(ISR_ALD, "ALD", NULL),
199 PXA_BIT(ISR_ITE, "TxEmpty", NULL),
200 PXA_BIT(ISR_IRF, "RxFull", NULL),
201 PXA_BIT(ISR_GCAD, "GenCall", NULL),
202 PXA_BIT(ISR_SAD, "SlaveAddr", NULL),
203 PXA_BIT(ISR_BED, "BusErr", NULL),
206 static void decode_ISR(unsigned int val)
208 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
212 static const struct bits icr_bits[] = {
213 PXA_BIT(ICR_START, "START", NULL),
214 PXA_BIT(ICR_STOP, "STOP", NULL),
215 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL),
216 PXA_BIT(ICR_TB, "TB", NULL),
217 PXA_BIT(ICR_MA, "MA", NULL),
218 PXA_BIT(ICR_SCLE, "SCLE", "scle"),
219 PXA_BIT(ICR_IUE, "IUE", "iue"),
220 PXA_BIT(ICR_GCD, "GCD", NULL),
221 PXA_BIT(ICR_ITEIE, "ITEIE", NULL),
222 PXA_BIT(ICR_IRFIE, "IRFIE", NULL),
223 PXA_BIT(ICR_BEIE, "BEIE", NULL),
224 PXA_BIT(ICR_SSDIE, "SSDIE", NULL),
225 PXA_BIT(ICR_ALDIE, "ALDIE", NULL),
226 PXA_BIT(ICR_SADIE, "SADIE", NULL),
227 PXA_BIT(ICR_UR, "UR", "ur"),
230 #ifdef CONFIG_I2C_PXA_SLAVE
231 static void decode_ICR(unsigned int val)
233 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
238 static unsigned int i2c_debug = DEBUG;
240 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
242 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
243 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
246 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
248 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
251 printk(KERN_ERR "i2c: error: %s\n", why);
252 printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
253 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
254 printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n",
255 readl(_ICR(i2c)), readl(_ISR(i2c)));
256 printk(KERN_DEBUG "i2c: log: ");
257 for (i = 0; i < i2c->irqlogidx; i++)
258 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
262 #else /* ifdef DEBUG */
266 #define show_state(i2c) do { } while (0)
267 #define decode_ISR(val) do { } while (0)
268 #define decode_ICR(val) do { } while (0)
269 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
271 #endif /* ifdef DEBUG / else */
273 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
274 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
276 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
278 return !(readl(_ICR(i2c)) & ICR_SCLE);
281 static void i2c_pxa_abort(struct pxa_i2c *i2c)
285 if (i2c_pxa_is_slavemode(i2c)) {
286 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
290 while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
291 unsigned long icr = readl(_ICR(i2c));
294 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
296 writel(icr, _ICR(i2c));
304 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
308 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
310 int timeout = DEF_TIMEOUT;
312 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
313 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
323 return timeout < 0 ? I2C_RETRY : 0;
326 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
328 unsigned long timeout = jiffies + HZ*4;
330 while (time_before(jiffies, timeout)) {
332 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
333 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
335 if (readl(_ISR(i2c)) & ISR_SAD) {
337 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
341 /* wait for unit and bus being not busy, and we also do a
342 * quick check of the i2c lines themselves to ensure they've
345 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
347 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
355 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
360 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
363 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
365 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
366 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
367 if (!i2c_pxa_wait_master(i2c)) {
368 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
373 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
377 #ifdef CONFIG_I2C_PXA_SLAVE
378 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
380 unsigned long timeout = jiffies + HZ*1;
386 while (time_before(jiffies, timeout)) {
388 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
389 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
391 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
392 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
393 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
395 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
403 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
408 * clear the hold on the bus, and take of anything else
409 * that has been configured
411 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
416 udelay(100); /* simple delay */
418 /* we need to wait for the stop condition to end */
420 /* if we where in stop, then clear... */
421 if (readl(_ICR(i2c)) & ICR_STOP) {
423 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
426 if (!i2c_pxa_wait_slave(i2c)) {
427 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
433 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
434 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
437 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
438 decode_ICR(readl(_ICR(i2c)));
442 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
445 static void i2c_pxa_reset(struct pxa_i2c *i2c)
447 pr_debug("Resetting I2C Controller Unit\n");
449 /* abort any transfer currently under way */
452 /* reset according to 9.8 */
453 writel(ICR_UR, _ICR(i2c));
454 writel(I2C_ISR_INIT, _ISR(i2c));
455 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
458 writel(i2c->slave_addr, _ISAR(i2c));
460 /* set control register values */
461 writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
463 #ifdef CONFIG_I2C_PXA_SLAVE
464 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
465 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
468 i2c_pxa_set_slave(i2c, 0);
471 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
476 #ifdef CONFIG_I2C_PXA_SLAVE
481 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
484 /* what should we do here? */
488 if (i2c->slave != NULL)
489 ret = i2c->slave->read(i2c->slave->data);
491 writel(ret, _IDBR(i2c));
492 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
496 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
498 unsigned int byte = readl(_IDBR(i2c));
500 if (i2c->slave != NULL)
501 i2c->slave->write(i2c->slave->data, byte);
503 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
506 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
511 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
512 (isr & ISR_RWM) ? 'r' : 't');
514 if (i2c->slave != NULL)
515 i2c->slave->event(i2c->slave->data,
516 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
519 * slave could interrupt in the middle of us generating a
520 * start condition... if this happens, we'd better back off
521 * and stop holding the poor thing up
523 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
524 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
529 if ((readl(_IBMR(i2c)) & 2) == 2)
535 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
540 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
543 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
546 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
548 if (i2c->slave != NULL)
549 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
552 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
555 * If we have a master-mode message waiting,
556 * kick it off now that the slave has completed.
559 i2c_pxa_master_complete(i2c, I2C_RETRY);
562 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
565 /* what should we do here? */
567 writel(0, _IDBR(i2c));
568 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
572 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
574 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
577 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
582 * slave could interrupt in the middle of us generating a
583 * start condition... if this happens, we'd better back off
584 * and stop holding the poor thing up
586 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
587 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
592 if ((readl(_IBMR(i2c)) & 2) == 2)
598 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
603 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
606 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
609 i2c_pxa_master_complete(i2c, I2C_RETRY);
614 * PXA I2C Master mode
617 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
619 unsigned int addr = (msg->addr & 0x7f) << 1;
621 if (msg->flags & I2C_M_RD)
627 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
632 * Step 1: target slave address into IDBR
634 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
637 * Step 2: initiate the write.
639 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
640 writel(icr | ICR_START | ICR_TB, _ICR(i2c));
643 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
648 * Clear the STOP and ACK flags
650 icr = readl(_ICR(i2c));
651 icr &= ~(ICR_STOP | ICR_ACKNAK);
652 writel(icr, _ICR(i2c));
655 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
657 /* make timeout the same as for interrupt based functions */
658 long timeout = 2 * DEF_TIMEOUT;
661 * Wait for the bus to become free.
663 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
670 dev_err(&i2c->adap.dev,
671 "i2c_pxa: timeout waiting for bus free\n");
678 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
683 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
684 struct i2c_msg *msg, int num)
686 unsigned long timeout = 500000; /* 5 seconds */
689 ret = i2c_pxa_pio_set_master(i2c);
699 i2c_pxa_start_message(i2c);
701 while (i2c->msg_num > 0 && --timeout) {
702 i2c_pxa_handler(0, i2c);
706 i2c_pxa_stop_message(i2c);
709 * We place the return code in i2c->msg_idx.
715 i2c_pxa_scream_blue_murder(i2c, "timeout");
721 * We are protected by the adapter bus mutex.
723 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
729 * Wait for the bus to become free.
731 ret = i2c_pxa_wait_bus_not_busy(i2c);
733 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
740 ret = i2c_pxa_set_master(i2c);
742 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
746 spin_lock_irq(&i2c->lock);
754 i2c_pxa_start_message(i2c);
756 spin_unlock_irq(&i2c->lock);
759 * The rest of the processing occurs in the interrupt handler.
761 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
762 i2c_pxa_stop_message(i2c);
765 * We place the return code in i2c->msg_idx.
769 if (!timeout && i2c->msg_num) {
770 i2c_pxa_scream_blue_murder(i2c, "timeout");
778 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
779 struct i2c_msg msgs[], int num)
781 struct pxa_i2c *i2c = adap->algo_data;
784 /* If the I2C controller is disabled we need to reset it
785 (probably due to a suspend/resume destroying state). We do
786 this here as we can then avoid worrying about resuming the
787 controller before its users. */
788 if (!(readl(_ICR(i2c)) & ICR_IUE))
791 for (i = adap->retries; i >= 0; i--) {
792 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
793 if (ret != I2C_RETRY)
797 dev_dbg(&adap->dev, "Retrying transmission\n");
800 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
803 i2c_pxa_set_slave(i2c, ret);
808 * i2c_pxa_master_complete - complete the message and wake up.
810 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
822 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
824 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
828 * If ISR_ALD is set, we lost arbitration.
832 * Do we need to do anything here? The PXA docs
833 * are vague about what happens.
835 i2c_pxa_scream_blue_murder(i2c, "ALD set");
838 * We ignore this error. We seem to see spurious ALDs
839 * for seemingly no reason. If we handle them as I think
840 * they should, we end up causing an I2C error, which
841 * is painful for some systems.
850 * I2C bus error - either the device NAK'd us, or
851 * something more serious happened. If we were NAK'd
852 * on the initial address phase, we can retry.
854 if (isr & ISR_ACKNAK) {
855 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
860 i2c_pxa_master_complete(i2c, ret);
861 } else if (isr & ISR_RWM) {
863 * Read mode. We have just sent the address byte, and
864 * now we must initiate the transfer.
866 if (i2c->msg_ptr == i2c->msg->len - 1 &&
867 i2c->msg_idx == i2c->msg_num - 1)
868 icr |= ICR_STOP | ICR_ACKNAK;
870 icr |= ICR_ALDIE | ICR_TB;
871 } else if (i2c->msg_ptr < i2c->msg->len) {
873 * Write mode. Write the next data byte.
875 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
877 icr |= ICR_ALDIE | ICR_TB;
880 * If this is the last byte of the last message, send
883 if (i2c->msg_ptr == i2c->msg->len &&
884 i2c->msg_idx == i2c->msg_num - 1)
886 } else if (i2c->msg_idx < i2c->msg_num - 1) {
888 * Next segment of the message.
895 * If we aren't doing a repeated start and address,
896 * go back and try to send the next byte. Note that
897 * we do not support switching the R/W direction here.
899 if (i2c->msg->flags & I2C_M_NOSTART)
903 * Write the next address.
905 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
908 * And trigger a repeated start, and send the byte.
911 icr |= ICR_START | ICR_TB;
913 if (i2c->msg->len == 0) {
915 * Device probes have a message length of zero
916 * and need the bus to be reset before it can
921 i2c_pxa_master_complete(i2c, 0);
924 i2c->icrlog[i2c->irqlogidx-1] = icr;
926 writel(icr, _ICR(i2c));
930 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
932 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
937 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
939 if (i2c->msg_ptr < i2c->msg->len) {
941 * If this is the last byte of the last
942 * message, send a STOP.
944 if (i2c->msg_ptr == i2c->msg->len - 1)
945 icr |= ICR_STOP | ICR_ACKNAK;
947 icr |= ICR_ALDIE | ICR_TB;
949 i2c_pxa_master_complete(i2c, 0);
952 i2c->icrlog[i2c->irqlogidx-1] = icr;
954 writel(icr, _ICR(i2c));
957 #define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
959 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
961 struct pxa_i2c *i2c = dev_id;
962 u32 isr = readl(_ISR(i2c));
964 if (!(isr & VALID_INT_SOURCE))
967 if (i2c_debug > 2 && 0) {
968 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
969 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
973 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
974 i2c->isrlog[i2c->irqlogidx++] = isr;
979 * Always clear all pending IRQs.
981 writel(isr & VALID_INT_SOURCE, _ISR(i2c));
984 i2c_pxa_slave_start(i2c, isr);
986 i2c_pxa_slave_stop(i2c);
988 if (i2c_pxa_is_slavemode(i2c)) {
990 i2c_pxa_slave_txempty(i2c, isr);
992 i2c_pxa_slave_rxfull(i2c, isr);
993 } else if (i2c->msg) {
995 i2c_pxa_irq_txempty(i2c, isr);
997 i2c_pxa_irq_rxfull(i2c, isr);
999 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1006 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
1008 struct pxa_i2c *i2c = adap->algo_data;
1011 for (i = adap->retries; i >= 0; i--) {
1012 ret = i2c_pxa_do_xfer(i2c, msgs, num);
1013 if (ret != I2C_RETRY)
1017 dev_dbg(&adap->dev, "Retrying transmission\n");
1020 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1023 i2c_pxa_set_slave(i2c, ret);
1027 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1029 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1032 static const struct i2c_algorithm i2c_pxa_algorithm = {
1033 .master_xfer = i2c_pxa_xfer,
1034 .functionality = i2c_pxa_functionality,
1037 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1038 .master_xfer = i2c_pxa_pio_xfer,
1039 .functionality = i2c_pxa_functionality,
1042 static struct of_device_id i2c_pxa_dt_ids[] = {
1043 { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
1044 { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
1045 { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA2XX },
1048 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
1050 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1051 enum pxa_i2c_types *i2c_types)
1053 struct device_node *np = pdev->dev.of_node;
1054 const struct of_device_id *of_id =
1055 of_match_device(i2c_pxa_dt_ids, &pdev->dev);
1060 /* For device tree we always use the dynamic or alias-assigned ID */
1063 if (of_get_property(np, "mrvl,i2c-polling", NULL))
1065 if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
1067 *i2c_types = (u32)(of_id->data);
1071 static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1072 struct pxa_i2c *i2c,
1073 enum pxa_i2c_types *i2c_types)
1075 struct i2c_pxa_platform_data *plat = pdev->dev.platform_data;
1076 const struct platform_device_id *id = platform_get_device_id(pdev);
1078 *i2c_types = id->driver_data;
1080 i2c->use_pio = plat->use_pio;
1081 i2c->fast_mode = plat->fast_mode;
1086 static int i2c_pxa_probe(struct platform_device *dev)
1088 struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
1089 enum pxa_i2c_types i2c_type;
1090 struct pxa_i2c *i2c;
1091 struct resource *res = NULL;
1094 i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
1100 /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1101 i2c->adap.nr = dev->id;
1103 ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1105 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1109 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1110 irq = platform_get_irq(dev, 0);
1111 if (res == NULL || irq < 0) {
1116 if (!request_mem_region(res->start, resource_size(res), res->name)) {
1121 i2c->adap.owner = THIS_MODULE;
1122 i2c->adap.retries = 5;
1124 spin_lock_init(&i2c->lock);
1125 init_waitqueue_head(&i2c->wait);
1127 strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1129 i2c->clk = clk_get(&dev->dev, NULL);
1130 if (IS_ERR(i2c->clk)) {
1131 ret = PTR_ERR(i2c->clk);
1135 i2c->reg_base = ioremap(res->start, resource_size(res));
1136 if (!i2c->reg_base) {
1141 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1142 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1143 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1144 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1145 if (i2c_type != REGS_CE4100)
1146 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1148 i2c->iobase = res->start;
1149 i2c->iosize = resource_size(res);
1153 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1156 #ifdef CONFIG_I2C_PXA_SLAVE
1157 i2c->slave_addr = plat->slave_addr;
1158 i2c->slave = plat->slave;
1160 i2c->adap.class = plat->class;
1163 clk_enable(i2c->clk);
1166 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1168 i2c->adap.algo = &i2c_pxa_algorithm;
1169 ret = request_irq(irq, i2c_pxa_handler, IRQF_SHARED,
1170 dev_name(&dev->dev), i2c);
1177 i2c->adap.algo_data = i2c;
1178 i2c->adap.dev.parent = &dev->dev;
1180 i2c->adap.dev.of_node = dev->dev.of_node;
1183 ret = i2c_add_numbered_adapter(&i2c->adap);
1185 printk(KERN_INFO "I2C: Failed to add bus\n");
1188 of_i2c_register_devices(&i2c->adap);
1190 platform_set_drvdata(dev, i2c);
1192 #ifdef CONFIG_I2C_PXA_SLAVE
1193 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1194 dev_name(&i2c->adap.dev), i2c->slave_addr);
1196 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1197 dev_name(&i2c->adap.dev));
1205 clk_disable(i2c->clk);
1206 iounmap(i2c->reg_base);
1212 release_mem_region(res->start, resource_size(res));
1216 static int i2c_pxa_remove(struct platform_device *dev)
1218 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1220 i2c_del_adapter(&i2c->adap);
1222 free_irq(i2c->irq, i2c);
1224 clk_disable(i2c->clk);
1227 iounmap(i2c->reg_base);
1228 release_mem_region(i2c->iobase, i2c->iosize);
1235 static int i2c_pxa_suspend_noirq(struct device *dev)
1237 struct platform_device *pdev = to_platform_device(dev);
1238 struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1240 clk_disable(i2c->clk);
1245 static int i2c_pxa_resume_noirq(struct device *dev)
1247 struct platform_device *pdev = to_platform_device(dev);
1248 struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1250 clk_enable(i2c->clk);
1256 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1257 .suspend_noirq = i2c_pxa_suspend_noirq,
1258 .resume_noirq = i2c_pxa_resume_noirq,
1261 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1263 #define I2C_PXA_DEV_PM_OPS NULL
1266 static struct platform_driver i2c_pxa_driver = {
1267 .probe = i2c_pxa_probe,
1268 .remove = i2c_pxa_remove,
1270 .name = "pxa2xx-i2c",
1271 .owner = THIS_MODULE,
1272 .pm = I2C_PXA_DEV_PM_OPS,
1273 .of_match_table = i2c_pxa_dt_ids,
1275 .id_table = i2c_pxa_id_table,
1278 static int __init i2c_adap_pxa_init(void)
1280 return platform_driver_register(&i2c_pxa_driver);
1283 static void __exit i2c_adap_pxa_exit(void)
1285 platform_driver_unregister(&i2c_pxa_driver);
1288 MODULE_LICENSE("GPL");
1289 MODULE_ALIAS("platform:pxa2xx-i2c");
1291 subsys_initcall(i2c_adap_pxa_init);
1292 module_exit(i2c_adap_pxa_exit);