drivers/i2c/busses/i2c-pmcmsp.c

   1 /*
   2  * Specific bus support for PMC-TWI compliant implementation on MSP71xx.
   3  *
   4  * Copyright 2005-2007 PMC-Sierra, Inc.
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  12  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  14  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  15  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  16  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  17  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  18  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  19  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  20  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  21  */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/i2c.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/completion.h>
  29 #include <linux/mutex.h>
  30 #include <linux/delay.h>
  31 #include <linux/io.h>
  32
  33 #define DRV_NAME        "pmcmsptwi"
  34
  35 #define MSP_TWI_SF_CLK_REG_OFFSET       0x00
  36 #define MSP_TWI_HS_CLK_REG_OFFSET       0x04
  37 #define MSP_TWI_CFG_REG_OFFSET          0x08
  38 #define MSP_TWI_CMD_REG_OFFSET          0x0c
  39 #define MSP_TWI_ADD_REG_OFFSET          0x10
  40 #define MSP_TWI_DAT_0_REG_OFFSET        0x14
  41 #define MSP_TWI_DAT_1_REG_OFFSET        0x18
  42 #define MSP_TWI_INT_STS_REG_OFFSET      0x1c
  43 #define MSP_TWI_INT_MSK_REG_OFFSET      0x20
  44 #define MSP_TWI_BUSY_REG_OFFSET         0x24
  45
  46 #define MSP_TWI_INT_STS_DONE                    (1 << 0)
  47 #define MSP_TWI_INT_STS_LOST_ARBITRATION        (1 << 1)
  48 #define MSP_TWI_INT_STS_NO_RESPONSE             (1 << 2)
  49 #define MSP_TWI_INT_STS_DATA_COLLISION          (1 << 3)
  50 #define MSP_TWI_INT_STS_BUSY                    (1 << 4)
  51 #define MSP_TWI_INT_STS_ALL                     0x1f
  52
  53 #define MSP_MAX_BYTES_PER_RW            8
  54 #define MSP_MAX_POLL                    5
  55 #define MSP_POLL_DELAY                  10
  56 #define MSP_IRQ_TIMEOUT                 (MSP_MAX_POLL * MSP_POLL_DELAY)
  57
  58 /* IO Operation macros */
  59 #define pmcmsptwi_readl         __raw_readl
  60 #define pmcmsptwi_writel        __raw_writel
  61
  62 /* TWI command type */
  63 enum pmcmsptwi_cmd_type {
  64         MSP_TWI_CMD_WRITE       = 0,    /* Write only */
  65         MSP_TWI_CMD_READ        = 1,    /* Read only */
  66         MSP_TWI_CMD_WRITE_READ  = 2,    /* Write then Read */
  67 };
  68
  69 /* The possible results of the xferCmd */
  70 enum pmcmsptwi_xfer_result {
  71         MSP_TWI_XFER_OK = 0,
  72         MSP_TWI_XFER_TIMEOUT,
  73         MSP_TWI_XFER_BUSY,
  74         MSP_TWI_XFER_DATA_COLLISION,
  75         MSP_TWI_XFER_NO_RESPONSE,
  76         MSP_TWI_XFER_LOST_ARBITRATION,
  77 };
  78
  79 /* Corresponds to a PMCTWI clock configuration register */
  80 struct pmcmsptwi_clock {
  81         u8 filter;      /* Bits 15:12,  default = 0x03 */
  82         u16 clock;      /* Bits 9:0,    default = 0x001f */
  83 };
  84
  85 struct pmcmsptwi_clockcfg {
  86         struct pmcmsptwi_clock standard;  /* The standard/fast clock config */
  87         struct pmcmsptwi_clock highspeed; /* The highspeed clock config */
  88 };
  89
  90 /* Corresponds to the main TWI configuration register */
  91 struct pmcmsptwi_cfg {
  92         u8 arbf;        /* Bits 15:12,  default=0x03 */
  93         u8 nak;         /* Bits 11:8,   default=0x03 */
  94         u8 add10;       /* Bit 7,       default=0x00 */
  95         u8 mst_code;    /* Bits 6:4,    default=0x00 */
  96         u8 arb;         /* Bit 1,       default=0x01 */
  97         u8 highspeed;   /* Bit 0,       default=0x00 */
  98 };
  99
 100 /* A single pmctwi command to issue */
 101 struct pmcmsptwi_cmd {
 102         u16 addr;       /* The slave address (7 or 10 bits) */
 103         enum pmcmsptwi_cmd_type type;   /* The command type */
 104         u8 write_len;   /* Number of bytes in the write buffer */
 105         u8 read_len;    /* Number of bytes in the read buffer */
 106         u8 *write_data; /* Buffer of characters to send */
 107         u8 *read_data;  /* Buffer to fill with incoming data */
 108 };
 109
 110 /* The private data */
 111 struct pmcmsptwi_data {
 112         void __iomem *iobase;                   /* iomapped base for IO */
 113         int irq;                                /* IRQ to use (0 disables) */
 114         struct completion wait;                 /* Completion for xfer */
 115         struct mutex lock;                      /* Used for threadsafeness */
 116         enum pmcmsptwi_xfer_result last_result; /* result of last xfer */
 117 };
 118
 119 /* The default settings */
 120 static const struct pmcmsptwi_clockcfg pmcmsptwi_defclockcfg = {
 121         .standard = {
 122                 .filter = 0x3,
 123                 .clock  = 0x1f,
 124         },
 125         .highspeed = {
 126                 .filter = 0x3,
 127                 .clock  = 0x1f,
 128         },
 129 };
 130
 131 static const struct pmcmsptwi_cfg pmcmsptwi_defcfg = {
 132         .arbf           = 0x03,
 133         .nak            = 0x03,
 134         .add10          = 0x00,
 135         .mst_code       = 0x00,
 136         .arb            = 0x01,
 137         .highspeed      = 0x00,
 138 };
 139
 140 static struct pmcmsptwi_data pmcmsptwi_data;
 141
 142 static struct i2c_adapter pmcmsptwi_adapter;
 143
 144 /* inline helper functions */
 145 static inline u32 pmcmsptwi_clock_to_reg(
 146                         const struct pmcmsptwi_clock *clock)
 147 {
 148         return ((clock->filter & 0xf) << 12) | (clock->clock & 0x03ff);
 149 }
 150
 151 static inline void pmcmsptwi_reg_to_clock(
 152                         u32 reg, struct pmcmsptwi_clock *clock)
 153 {
 154         clock->filter = (reg >> 12) & 0xf;
 155         clock->clock = reg & 0x03ff;
 156 }
 157
 158 static inline u32 pmcmsptwi_cfg_to_reg(const struct pmcmsptwi_cfg *cfg)
 159 {
 160         return ((cfg->arbf & 0xf) << 12) |
 161                 ((cfg->nak & 0xf) << 8) |
 162                 ((cfg->add10 & 0x1) << 7) |
 163                 ((cfg->mst_code & 0x7) << 4) |
 164                 ((cfg->arb & 0x1) << 1) |
 165                 (cfg->highspeed & 0x1);
 166 }
 167
 168 static inline void pmcmsptwi_reg_to_cfg(u32 reg, struct pmcmsptwi_cfg *cfg)
 169 {
 170         cfg->arbf = (reg >> 12) & 0xf;
 171         cfg->nak = (reg >> 8) & 0xf;
 172         cfg->add10 = (reg >> 7) & 0x1;
 173         cfg->mst_code = (reg >> 4) & 0x7;
 174         cfg->arb = (reg >> 1) & 0x1;
 175         cfg->highspeed = reg & 0x1;
 176 }
 177
 178 /*
 179  * Sets the current clock configuration
 180  */
 181 static void pmcmsptwi_set_clock_config(const struct pmcmsptwi_clockcfg *cfg,
 182                                         struct pmcmsptwi_data *data)
 183 {
 184         mutex_lock(&data->lock);
 185         pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg->standard),
 186                                 data->iobase + MSP_TWI_SF_CLK_REG_OFFSET);
 187         pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg->highspeed),
 188                                 data->iobase + MSP_TWI_HS_CLK_REG_OFFSET);
 189         mutex_unlock(&data->lock);
 190 }
 191
 192 /*
 193  * Gets the current TWI bus configuration
 194  */
 195 static void pmcmsptwi_get_twi_config(struct pmcmsptwi_cfg *cfg,
 196                                         struct pmcmsptwi_data *data)
 197 {
 198         mutex_lock(&data->lock);
 199         pmcmsptwi_reg_to_cfg(pmcmsptwi_readl(
 200                                 data->iobase + MSP_TWI_CFG_REG_OFFSET), cfg);
 201         mutex_unlock(&data->lock);
 202 }
 203
 204 /*
 205  * Sets the current TWI bus configuration
 206  */
 207 static void pmcmsptwi_set_twi_config(const struct pmcmsptwi_cfg *cfg,
 208                                         struct pmcmsptwi_data *data)
 209 {
 210         mutex_lock(&data->lock);
 211         pmcmsptwi_writel(pmcmsptwi_cfg_to_reg(cfg),
 212                                 data->iobase + MSP_TWI_CFG_REG_OFFSET);
 213         mutex_unlock(&data->lock);
 214 }
 215
 216 /*
 217  * Parses the 'int_sts' register and returns a well-defined error code
 218  */
 219 static enum pmcmsptwi_xfer_result pmcmsptwi_get_result(u32 reg)
 220 {
 221         if (reg & MSP_TWI_INT_STS_LOST_ARBITRATION) {
 222                 dev_dbg(&pmcmsptwi_adapter.dev,
 223                         "Result: Lost arbitration\n");
 224                 return MSP_TWI_XFER_LOST_ARBITRATION;
 225         } else if (reg & MSP_TWI_INT_STS_NO_RESPONSE) {
 226                 dev_dbg(&pmcmsptwi_adapter.dev,
 227                         "Result: No response\n");
 228                 return MSP_TWI_XFER_NO_RESPONSE;
 229         } else if (reg & MSP_TWI_INT_STS_DATA_COLLISION) {
 230                 dev_dbg(&pmcmsptwi_adapter.dev,
 231                         "Result: Data collision\n");
 232                 return MSP_TWI_XFER_DATA_COLLISION;
 233         } else if (reg & MSP_TWI_INT_STS_BUSY) {
 234                 dev_dbg(&pmcmsptwi_adapter.dev,
 235                         "Result: Bus busy\n");
 236                 return MSP_TWI_XFER_BUSY;
 237         }
 238
 239         dev_dbg(&pmcmsptwi_adapter.dev, "Result: Operation succeeded\n");
 240         return MSP_TWI_XFER_OK;
 241 }
 242
 243 /*
 244  * In interrupt mode, handle the interrupt.
 245  * NOTE: Assumes data->lock is held.
 246  */
 247 static irqreturn_t pmcmsptwi_interrupt(int irq, void *ptr)
 248 {
 249         struct pmcmsptwi_data *data = ptr;
 250
 251         u32 reason = pmcmsptwi_readl(data->iobase +
 252                                         MSP_TWI_INT_STS_REG_OFFSET);
 253         pmcmsptwi_writel(reason, data->iobase + MSP_TWI_INT_STS_REG_OFFSET);
 254
 255         dev_dbg(&pmcmsptwi_adapter.dev, "Got interrupt 0x%08x\n", reason);
 256         if (!(reason & MSP_TWI_INT_STS_DONE))
 257                 return IRQ_NONE;
 258
 259         data->last_result = pmcmsptwi_get_result(reason);
 260         complete(&data->wait);
 261
 262         return IRQ_HANDLED;
 263 }
 264
 265 /*
 266  * Probe for and register the device and return 0 if there is one.
 267  */
 268 static int pmcmsptwi_probe(struct platform_device *pldev)
 269 {
 270         struct resource *res;
 271         int rc = -ENODEV;
 272
 273         /* get the static platform resources */
 274         res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
 275         if (!res) {
 276                 dev_err(&pldev->dev, "IOMEM resource not found\n");
 277                 goto ret_err;
 278         }
 279
 280         /* reserve the memory region */
 281         if (!request_mem_region(res->start, resource_size(res),
 282                                 pldev->name)) {
 283                 dev_err(&pldev->dev,
 284                         "Unable to get memory/io address region 0x%08x\n",
 285                         res->start);
 286                 rc = -EBUSY;
 287                 goto ret_err;
 288         }
 289
 290         /* remap the memory */
 291         pmcmsptwi_data.iobase = ioremap_nocache(res->start,
 292                                                 resource_size(res));
 293         if (!pmcmsptwi_data.iobase) {
 294                 dev_err(&pldev->dev,
 295                         "Unable to ioremap address 0x%08x\n", res->start);
 296                 rc = -EIO;
 297                 goto ret_unreserve;
 298         }
 299
 300         /* request the irq */
 301         pmcmsptwi_data.irq = platform_get_irq(pldev, 0);
 302         if (pmcmsptwi_data.irq) {
 303                 rc = request_irq(pmcmsptwi_data.irq, &pmcmsptwi_interrupt,
 304                                  IRQF_SHARED, pldev->name, &pmcmsptwi_data);
 305                 if (rc == 0) {
 306                         /*
 307                          * Enable 'DONE' interrupt only.
 308                          *
 309                          * If you enable all interrupts, you will get one on
 310                          * error and another when the operation completes.
 311                          * This way you only have to handle one interrupt,
 312                          * but you can still check all result flags.
 313                          */
 314                         pmcmsptwi_writel(MSP_TWI_INT_STS_DONE,
 315                                         pmcmsptwi_data.iobase +
 316                                         MSP_TWI_INT_MSK_REG_OFFSET);
 317                 } else {
 318                         dev_warn(&pldev->dev,
 319                                 "Could not assign TWI IRQ handler "
 320                                 "to irq %d (continuing with poll)\n",
 321                                 pmcmsptwi_data.irq);
 322                         pmcmsptwi_data.irq = 0;
 323                 }
 324         }
 325
 326         init_completion(&pmcmsptwi_data.wait);
 327         mutex_init(&pmcmsptwi_data.lock);
 328
 329         pmcmsptwi_set_clock_config(&pmcmsptwi_defclockcfg, &pmcmsptwi_data);
 330         pmcmsptwi_set_twi_config(&pmcmsptwi_defcfg, &pmcmsptwi_data);
 331
 332         printk(KERN_INFO DRV_NAME ": Registering MSP71xx I2C adapter\n");
 333
 334         pmcmsptwi_adapter.dev.parent = &pldev->dev;
 335         platform_set_drvdata(pldev, &pmcmsptwi_adapter);
 336         i2c_set_adapdata(&pmcmsptwi_adapter, &pmcmsptwi_data);
 337
 338         rc = i2c_add_adapter(&pmcmsptwi_adapter);
 339         if (rc) {
 340                 dev_err(&pldev->dev, "Unable to register I2C adapter\n");
 341                 goto ret_unmap;
 342         }
 343
 344         return 0;
 345
 346 ret_unmap:
 347         if (pmcmsptwi_data.irq) {
 348                 pmcmsptwi_writel(0,
 349                         pmcmsptwi_data.iobase + MSP_TWI_INT_MSK_REG_OFFSET);
 350                 free_irq(pmcmsptwi_data.irq, &pmcmsptwi_data);
 351         }
 352
 353         iounmap(pmcmsptwi_data.iobase);
 354
 355 ret_unreserve:
 356         release_mem_region(res->start, resource_size(res));
 357
 358 ret_err:
 359         return rc;
 360 }
 361
 362 /*
 363  * Release the device and return 0 if there is one.
 364  */
 365 static int pmcmsptwi_remove(struct platform_device *pldev)
 366 {
 367         struct resource *res;
 368
 369         i2c_del_adapter(&pmcmsptwi_adapter);
 370
 371         if (pmcmsptwi_data.irq) {
 372                 pmcmsptwi_writel(0,
 373                         pmcmsptwi_data.iobase + MSP_TWI_INT_MSK_REG_OFFSET);
 374                 free_irq(pmcmsptwi_data.irq, &pmcmsptwi_data);
 375         }
 376
 377         iounmap(pmcmsptwi_data.iobase);
 378
 379         res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
 380         release_mem_region(res->start, resource_size(res));
 381
 382         return 0;
 383 }
 384
 385 /*
 386  * Polls the 'busy' register until the command is complete.
 387  * NOTE: Assumes data->lock is held.
 388  */
 389 static void pmcmsptwi_poll_complete(struct pmcmsptwi_data *data)
 390 {
 391         int i;
 392
 393         for (i = 0; i < MSP_MAX_POLL; i++) {
 394                 u32 val = pmcmsptwi_readl(data->iobase +
 395                                                 MSP_TWI_BUSY_REG_OFFSET);
 396                 if (val == 0) {
 397                         u32 reason = pmcmsptwi_readl(data->iobase +
 398                                                 MSP_TWI_INT_STS_REG_OFFSET);
 399                         pmcmsptwi_writel(reason, data->iobase +
 400                                                 MSP_TWI_INT_STS_REG_OFFSET);
 401                         data->last_result = pmcmsptwi_get_result(reason);
 402                         return;
 403                 }
 404                 udelay(MSP_POLL_DELAY);
 405         }
 406
 407         dev_dbg(&pmcmsptwi_adapter.dev, "Result: Poll timeout\n");
 408         data->last_result = MSP_TWI_XFER_TIMEOUT;
 409 }
 410
 411 /*
 412  * Do the transfer (low level):
 413  *   May use interrupt-driven or polling, depending on if an IRQ is
 414  *   presently registered.
 415  * NOTE: Assumes data->lock is held.
 416  */
 417 static enum pmcmsptwi_xfer_result pmcmsptwi_do_xfer(
 418                         u32 reg, struct pmcmsptwi_data *data)
 419 {
 420         dev_dbg(&pmcmsptwi_adapter.dev, "Writing cmd reg 0x%08x\n", reg);
 421         pmcmsptwi_writel(reg, data->iobase + MSP_TWI_CMD_REG_OFFSET);
 422         if (data->irq) {
 423                 unsigned long timeleft = wait_for_completion_timeout(
 424                                                 &data->wait, MSP_IRQ_TIMEOUT);
 425                 if (timeleft == 0) {
 426                         dev_dbg(&pmcmsptwi_adapter.dev,
 427                                 "Result: IRQ timeout\n");
 428                         complete(&data->wait);
 429                         data->last_result = MSP_TWI_XFER_TIMEOUT;
 430                 }
 431         } else
 432                 pmcmsptwi_poll_complete(data);
 433
 434         return data->last_result;
 435 }
 436
 437 /*
 438  * Helper routine, converts 'pmctwi_cmd' struct to register format
 439  */
 440 static inline u32 pmcmsptwi_cmd_to_reg(const struct pmcmsptwi_cmd *cmd)
 441 {
 442         return ((cmd->type & 0x3) << 8) |
 443                 (((cmd->write_len - 1) & 0x7) << 4) |
 444                 ((cmd->read_len - 1) & 0x7);
 445 }
 446
 447 /*
 448  * Do the transfer (high level)
 449  */
 450 static enum pmcmsptwi_xfer_result pmcmsptwi_xfer_cmd(
 451                         struct pmcmsptwi_cmd *cmd,
 452                         struct pmcmsptwi_data *data)
 453 {
 454         enum pmcmsptwi_xfer_result retval;
 455
 456         if ((cmd->type == MSP_TWI_CMD_WRITE && cmd->write_len == 0) ||
 457             (cmd->type == MSP_TWI_CMD_READ && cmd->read_len == 0) ||
 458             (cmd->type == MSP_TWI_CMD_WRITE_READ &&
 459             (cmd->read_len == 0 || cmd->write_len == 0))) {
 460                 dev_err(&pmcmsptwi_adapter.dev,
 461                         "%s: Cannot transfer less than 1 byte\n",
 462                         __func__);
 463                 return -EINVAL;
 464         }
 465
 466         if (cmd->read_len > MSP_MAX_BYTES_PER_RW ||
 467             cmd->write_len > MSP_MAX_BYTES_PER_RW) {
 468                 dev_err(&pmcmsptwi_adapter.dev,
 469                         "%s: Cannot transfer more than %d bytes\n",
 470                         __func__, MSP_MAX_BYTES_PER_RW);
 471                 return -EINVAL;
 472         }
 473
 474         mutex_lock(&data->lock);
 475         dev_dbg(&pmcmsptwi_adapter.dev,
 476                 "Setting address to 0x%04x\n", cmd->addr);
 477         pmcmsptwi_writel(cmd->addr, data->iobase + MSP_TWI_ADD_REG_OFFSET);
 478
 479         if (cmd->type == MSP_TWI_CMD_WRITE ||
 480             cmd->type == MSP_TWI_CMD_WRITE_READ) {
 481                 u64 tmp = be64_to_cpup((__be64 *)cmd->write_data);
 482                 tmp >>= (MSP_MAX_BYTES_PER_RW - cmd->write_len) * 8;
 483                 dev_dbg(&pmcmsptwi_adapter.dev, "Writing 0x%016llx\n", tmp);
 484                 pmcmsptwi_writel(tmp & 0x00000000ffffffffLL,
 485                                 data->iobase + MSP_TWI_DAT_0_REG_OFFSET);
 486                 if (cmd->write_len > 4)
 487                         pmcmsptwi_writel(tmp >> 32,
 488                                 data->iobase + MSP_TWI_DAT_1_REG_OFFSET);
 489         }
 490
 491         retval = pmcmsptwi_do_xfer(pmcmsptwi_cmd_to_reg(cmd), data);
 492         if (retval != MSP_TWI_XFER_OK)
 493                 goto xfer_err;
 494
 495         if (cmd->type == MSP_TWI_CMD_READ ||
 496             cmd->type == MSP_TWI_CMD_WRITE_READ) {
 497                 int i;
 498                 u64 rmsk = ~(0xffffffffffffffffLL << (cmd->read_len * 8));
 499                 u64 tmp = (u64)pmcmsptwi_readl(data->iobase +
 500                                         MSP_TWI_DAT_0_REG_OFFSET);
 501                 if (cmd->read_len > 4)
 502                         tmp |= (u64)pmcmsptwi_readl(data->iobase +
 503                                         MSP_TWI_DAT_1_REG_OFFSET) << 32;
 504                 tmp &= rmsk;
 505                 dev_dbg(&pmcmsptwi_adapter.dev, "Read 0x%016llx\n", tmp);
 506
 507                 for (i = 0; i < cmd->read_len; i++)
 508                         cmd->read_data[i] = tmp >> i;
 509         }
 510
 511 xfer_err:
 512         mutex_unlock(&data->lock);
 513
 514         return retval;
 515 }
 516
 517 /* -- Algorithm functions -- */
 518
 519 /*
 520  * Sends an i2c command out on the adapter
 521  */
 522 static int pmcmsptwi_master_xfer(struct i2c_adapter *adap,
 523                                 struct i2c_msg *msg, int num)
 524 {
 525         struct pmcmsptwi_data *data = i2c_get_adapdata(adap);
 526         struct pmcmsptwi_cmd cmd;
 527         struct pmcmsptwi_cfg oldcfg, newcfg;
 528         int ret;
 529
 530         if (num > 2) {
 531                 dev_dbg(&adap->dev, "%d messages unsupported\n", num);
 532                 return -EINVAL;
 533         } else if (num == 2) {
 534                 /* Check for a dual write-then-read command */
 535                 struct i2c_msg *nextmsg = msg + 1;
 536                 if (!(msg->flags & I2C_M_RD) &&
 537                     (nextmsg->flags & I2C_M_RD) &&
 538                     msg->addr == nextmsg->addr) {
 539                         cmd.type = MSP_TWI_CMD_WRITE_READ;
 540                         cmd.write_len = msg->len;
 541                         cmd.write_data = msg->buf;
 542                         cmd.read_len = nextmsg->len;
 543                         cmd.read_data = nextmsg->buf;
 544                 } else {
 545                         dev_dbg(&adap->dev,
 546                                 "Non write-read dual messages unsupported\n");
 547                         return -EINVAL;
 548                 }
 549         } else if (msg->flags & I2C_M_RD) {
 550                 cmd.type = MSP_TWI_CMD_READ;
 551                 cmd.read_len = msg->len;
 552                 cmd.read_data = msg->buf;
 553                 cmd.write_len = 0;
 554                 cmd.write_data = NULL;
 555         } else {
 556                 cmd.type = MSP_TWI_CMD_WRITE;
 557                 cmd.read_len = 0;
 558                 cmd.read_data = NULL;
 559                 cmd.write_len = msg->len;
 560                 cmd.write_data = msg->buf;
 561         }
 562
 563         if (msg->len == 0) {
 564                 dev_err(&adap->dev, "Zero-byte messages unsupported\n");
 565                 return -EINVAL;
 566         }
 567
 568         cmd.addr = msg->addr;
 569
 570         if (msg->flags & I2C_M_TEN) {
 571                 pmcmsptwi_get_twi_config(&newcfg, data);
 572                 memcpy(&oldcfg, &newcfg, sizeof(oldcfg));
 573
 574                 /* Set the special 10-bit address flag */
 575                 newcfg.add10 = 1;
 576
 577                 pmcmsptwi_set_twi_config(&newcfg, data);
 578         }
 579
 580         /* Execute the command */
 581         ret = pmcmsptwi_xfer_cmd(&cmd, data);
 582
 583         if (msg->flags & I2C_M_TEN)
 584                 pmcmsptwi_set_twi_config(&oldcfg, data);
 585
 586         dev_dbg(&adap->dev, "I2C %s of %d bytes %s\n",
 587                 (msg->flags & I2C_M_RD) ? "read" : "write", msg->len,
 588                 (ret == MSP_TWI_XFER_OK) ? "succeeded" : "failed");
 589
 590         if (ret != MSP_TWI_XFER_OK) {
 591                 /*
 592                  * TODO: We could potentially loop and retry in the case
 593                  * of MSP_TWI_XFER_TIMEOUT.
 594                  */
 595                 return -1;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static u32 pmcmsptwi_i2c_func(struct i2c_adapter *adapter)
 602 {
 603         return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
 604                 I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA |
 605                 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_PROC_CALL;
 606 }
 607
 608 /* -- Initialization -- */
 609
 610 static struct i2c_algorithm pmcmsptwi_algo = {
 611         .master_xfer    = pmcmsptwi_master_xfer,
 612         .functionality  = pmcmsptwi_i2c_func,
 613 };
 614
 615 static struct i2c_adapter pmcmsptwi_adapter = {
 616         .owner          = THIS_MODULE,
 617         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 618         .algo           = &pmcmsptwi_algo,
 619         .name           = DRV_NAME,
 620 };
 621
 622 static struct platform_driver pmcmsptwi_driver = {
 623         .probe  = pmcmsptwi_probe,
 624         .remove = pmcmsptwi_remove,
 625         .driver = {
 626                 .name   = DRV_NAME,
 627                 .owner  = THIS_MODULE,
 628         },
 629 };
 630
 631 module_platform_driver(pmcmsptwi_driver);
 632
 633 MODULE_DESCRIPTION("PMC MSP TWI/SMBus/I2C driver");
 634 MODULE_LICENSE("GPL");
 635 MODULE_ALIAS("platform:" DRV_NAME);