drivers/i2c/busses/i2c-piix4.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3     Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
   4     Philip Edelbrock <phil@netroedge.com>
   5
   6 */
   7
   8 /*
   9    Supports:
  10         Intel PIIX4, 440MX
  11         Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
  12         ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
  13         AMD Hudson-2, ML, CZ
  14         Hygon CZ
  15         SMSC Victory66
  16
  17    Note: we assume there can only be one device, with one or more
  18    SMBus interfaces.
  19    The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS).
  20    For devices supporting multiple ports the i2c_adapter should provide
  21    an i2c_algorithm to access them.
  22 */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/pci.h>
  27 #include <linux/kernel.h>
  28 #include <linux/delay.h>
  29 #include <linux/stddef.h>
  30 #include <linux/ioport.h>
  31 #include <linux/i2c.h>
  32 #include <linux/slab.h>
  33 #include <linux/dmi.h>
  34 #include <linux/acpi.h>
  35 #include <linux/io.h>
  36
  37
  38 /* PIIX4 SMBus address offsets */
  39 #define SMBHSTSTS       (0 + piix4_smba)
  40 #define SMBHSLVSTS      (1 + piix4_smba)
  41 #define SMBHSTCNT       (2 + piix4_smba)
  42 #define SMBHSTCMD       (3 + piix4_smba)
  43 #define SMBHSTADD       (4 + piix4_smba)
  44 #define SMBHSTDAT0      (5 + piix4_smba)
  45 #define SMBHSTDAT1      (6 + piix4_smba)
  46 #define SMBBLKDAT       (7 + piix4_smba)
  47 #define SMBSLVCNT       (8 + piix4_smba)
  48 #define SMBSHDWCMD      (9 + piix4_smba)
  49 #define SMBSLVEVT       (0xA + piix4_smba)
  50 #define SMBSLVDAT       (0xC + piix4_smba)
  51
  52 /* count for request_region */
  53 #define SMBIOSIZE       9
  54
  55 /* PCI Address Constants */
  56 #define SMBBA           0x090
  57 #define SMBHSTCFG       0x0D2
  58 #define SMBSLVC         0x0D3
  59 #define SMBSHDW1        0x0D4
  60 #define SMBSHDW2        0x0D5
  61 #define SMBREV          0x0D6
  62
  63 /* Other settings */
  64 #define MAX_TIMEOUT     500
  65 #define  ENABLE_INT9    0
  66
  67 /* PIIX4 constants */
  68 #define PIIX4_QUICK             0x00
  69 #define PIIX4_BYTE              0x04
  70 #define PIIX4_BYTE_DATA         0x08
  71 #define PIIX4_WORD_DATA         0x0C
  72 #define PIIX4_BLOCK_DATA        0x14
  73
  74 /* Multi-port constants */
  75 #define PIIX4_MAX_ADAPTERS      4
  76 #define HUDSON2_MAIN_PORTS      2 /* HUDSON2, KERNCZ reserves ports 3, 4 */
  77
  78 /* SB800 constants */
  79 #define SB800_PIIX4_SMB_IDX             0xcd6
  80 #define SB800_PIIX4_SMB_MAP_SIZE        2
  81
  82 #define KERNCZ_IMC_IDX                  0x3e
  83 #define KERNCZ_IMC_DATA                 0x3f
  84
  85 /*
  86  * SB800 port is selected by bits 2:1 of the smb_en register (0x2c)
  87  * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f.
  88  * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f.
  89  */
  90 #define SB800_PIIX4_PORT_IDX            0x2c
  91 #define SB800_PIIX4_PORT_IDX_ALT        0x2e
  92 #define SB800_PIIX4_PORT_IDX_SEL        0x2f
  93 #define SB800_PIIX4_PORT_IDX_MASK       0x06
  94 #define SB800_PIIX4_PORT_IDX_SHIFT      1
  95
  96 /* On kerncz and Hudson2, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
  97 #define SB800_PIIX4_PORT_IDX_KERNCZ             0x02
  98 #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ        0x18
  99 #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ       3
 100
 101 #define SB800_PIIX4_FCH_PM_ADDR                 0xFED80300
 102 #define SB800_PIIX4_FCH_PM_SIZE                 8
 103
 104 /* insmod parameters */
 105
 106 /* If force is set to anything different from 0, we forcibly enable the
 107    PIIX4. DANGEROUS! */
 108 static int force;
 109 module_param (force, int, 0);
 110 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
 111
 112 /* If force_addr is set to anything different from 0, we forcibly enable
 113    the PIIX4 at the given address. VERY DANGEROUS! */
 114 static int force_addr;
 115 module_param_hw(force_addr, int, ioport, 0);
 116 MODULE_PARM_DESC(force_addr,
 117                  "Forcibly enable the PIIX4 at the given address. "
 118                  "EXTREMELY DANGEROUS!");
 119
 120 static int srvrworks_csb5_delay;
 121 static struct pci_driver piix4_driver;
 122
 123 static const struct dmi_system_id piix4_dmi_blacklist[] = {
 124         {
 125                 .ident = "Sapphire AM2RD790",
 126                 .matches = {
 127                         DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
 128                         DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
 129                 },
 130         },
 131         {
 132                 .ident = "DFI Lanparty UT 790FX",
 133                 .matches = {
 134                         DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
 135                         DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
 136                 },
 137         },
 138         { }
 139 };
 140
 141 /* The IBM entry is in a separate table because we only check it
 142    on Intel-based systems */
 143 static const struct dmi_system_id piix4_dmi_ibm[] = {
 144         {
 145                 .ident = "IBM",
 146                 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
 147         },
 148         { },
 149 };
 150
 151 /*
 152  * SB800 globals
 153  */
 154 static u8 piix4_port_sel_sb800;
 155 static u8 piix4_port_mask_sb800;
 156 static u8 piix4_port_shift_sb800;
 157 static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = {
 158         " port 0", " port 2", " port 3", " port 4"
 159 };
 160 static const char *piix4_aux_port_name_sb800 = " port 1";
 161
 162 struct sb800_mmio_cfg {
 163         void __iomem *addr;
 164         struct resource *res;
 165         bool use_mmio;
 166 };
 167
 168 struct i2c_piix4_adapdata {
 169         unsigned short smba;
 170
 171         /* SB800 */
 172         bool sb800_main;
 173         bool notify_imc;
 174         u8 port;                /* Port number, shifted */
 175         struct sb800_mmio_cfg mmio_cfg;
 176 };
 177
 178 static int piix4_sb800_region_request(struct device *dev,
 179                                       struct sb800_mmio_cfg *mmio_cfg)
 180 {
 181         if (mmio_cfg->use_mmio) {
 182                 struct resource *res;
 183                 void __iomem *addr;
 184
 185                 res = request_mem_region_muxed(SB800_PIIX4_FCH_PM_ADDR,
 186                                                SB800_PIIX4_FCH_PM_SIZE,
 187                                                "sb800_piix4_smb");
 188                 if (!res) {
 189                         dev_err(dev,
 190                                 "SMBus base address memory region 0x%x already in use.\n",
 191                                 SB800_PIIX4_FCH_PM_ADDR);
 192                         return -EBUSY;
 193                 }
 194
 195                 addr = ioremap(SB800_PIIX4_FCH_PM_ADDR,
 196                                SB800_PIIX4_FCH_PM_SIZE);
 197                 if (!addr) {
 198                         release_resource(res);
 199                         dev_err(dev, "SMBus base address mapping failed.\n");
 200                         return -ENOMEM;
 201                 }
 202
 203                 mmio_cfg->res = res;
 204                 mmio_cfg->addr = addr;
 205
 206                 return 0;
 207         }
 208
 209         if (!request_muxed_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE,
 210                                   "sb800_piix4_smb")) {
 211                 dev_err(dev,
 212                         "SMBus base address index region 0x%x already in use.\n",
 213                         SB800_PIIX4_SMB_IDX);
 214                 return -EBUSY;
 215         }
 216
 217         return 0;
 218 }
 219
 220 static void piix4_sb800_region_release(struct device *dev,
 221                                        struct sb800_mmio_cfg *mmio_cfg)
 222 {
 223         if (mmio_cfg->use_mmio) {
 224                 iounmap(mmio_cfg->addr);
 225                 release_resource(mmio_cfg->res);
 226                 return;
 227         }
 228
 229         release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE);
 230 }
 231
 232 static bool piix4_sb800_use_mmio(struct pci_dev *PIIX4_dev)
 233 {
 234         /*
 235          * cd6h/cd7h port I/O accesses can be disabled on AMD processors
 236          * w/ SMBus PCI revision ID 0x51 or greater. MMIO is supported on
 237          * the same processors and is the recommended access method.
 238          */
 239         return (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
 240                 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
 241                 PIIX4_dev->revision >= 0x51);
 242 }
 243
 244 static int piix4_setup(struct pci_dev *PIIX4_dev,
 245                        const struct pci_device_id *id)
 246 {
 247         unsigned char temp;
 248         unsigned short piix4_smba;
 249
 250         if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
 251             (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
 252                 srvrworks_csb5_delay = 1;
 253
 254         /* On some motherboards, it was reported that accessing the SMBus
 255            caused severe hardware problems */
 256         if (dmi_check_system(piix4_dmi_blacklist)) {
 257                 dev_err(&PIIX4_dev->dev,
 258                         "Accessing the SMBus on this system is unsafe!\n");
 259                 return -EPERM;
 260         }
 261
 262         /* Don't access SMBus on IBM systems which get corrupted eeproms */
 263         if (dmi_check_system(piix4_dmi_ibm) &&
 264                         PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
 265                 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
 266                         "may corrupt your serial eeprom! Refusing to load "
 267                         "module!\n");
 268                 return -EPERM;
 269         }
 270
 271         /* Determine the address of the SMBus areas */
 272         if (force_addr) {
 273                 piix4_smba = force_addr & 0xfff0;
 274                 force = 0;
 275         } else {
 276                 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
 277                 piix4_smba &= 0xfff0;
 278                 if(piix4_smba == 0) {
 279                         dev_err(&PIIX4_dev->dev, "SMBus base address "
 280                                 "uninitialized - upgrade BIOS or use "
 281                                 "force_addr=0xaddr\n");
 282                         return -ENODEV;
 283                 }
 284         }
 285
 286         if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
 287                 return -ENODEV;
 288
 289         if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 290                 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
 291                         piix4_smba);
 292                 return -EBUSY;
 293         }
 294
 295         pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
 296
 297         /* If force_addr is set, we program the new address here. Just to make
 298            sure, we disable the PIIX4 first. */
 299         if (force_addr) {
 300                 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
 301                 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
 302                 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
 303                 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
 304                         "new address %04x!\n", piix4_smba);
 305         } else if ((temp & 1) == 0) {
 306                 if (force) {
 307                         /* This should never need to be done, but has been
 308                          * noted that many Dell machines have the SMBus
 309                          * interface on the PIIX4 disabled!? NOTE: This assumes
 310                          * I/O space and other allocations WERE done by the
 311                          * Bios!  Don't complain if your hardware does weird
 312                          * things after enabling this. :') Check for Bios
 313                          * updates before resorting to this.
 314                          */
 315                         pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
 316                                               temp | 1);
 317                         dev_notice(&PIIX4_dev->dev,
 318                                    "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n");
 319                 } else {
 320                         dev_err(&PIIX4_dev->dev,
 321                                 "SMBus Host Controller not enabled!\n");
 322                         release_region(piix4_smba, SMBIOSIZE);
 323                         return -ENODEV;
 324                 }
 325         }
 326
 327         if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
 328                 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
 329         else if ((temp & 0x0E) == 0)
 330                 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
 331         else
 332                 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
 333                         "(or code out of date)!\n");
 334
 335         pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
 336         dev_info(&PIIX4_dev->dev,
 337                  "SMBus Host Controller at 0x%x, revision %d\n",
 338                  piix4_smba, temp);
 339
 340         return piix4_smba;
 341 }
 342
 343 static int piix4_setup_sb800_smba(struct pci_dev *PIIX4_dev,
 344                                   u8 smb_en,
 345                                   u8 aux,
 346                                   u8 *smb_en_status,
 347                                   unsigned short *piix4_smba)
 348 {
 349         struct sb800_mmio_cfg mmio_cfg;
 350         u8 smba_en_lo;
 351         u8 smba_en_hi;
 352         int retval;
 353
 354         mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev);
 355         retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg);
 356         if (retval)
 357                 return retval;
 358
 359         if (mmio_cfg.use_mmio) {
 360                 smba_en_lo = ioread8(mmio_cfg.addr);
 361                 smba_en_hi = ioread8(mmio_cfg.addr + 1);
 362         } else {
 363                 outb_p(smb_en, SB800_PIIX4_SMB_IDX);
 364                 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
 365                 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX);
 366                 smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1);
 367         }
 368
 369         piix4_sb800_region_release(&PIIX4_dev->dev, &mmio_cfg);
 370
 371         if (!smb_en) {
 372                 *smb_en_status = smba_en_lo & 0x10;
 373                 *piix4_smba = smba_en_hi << 8;
 374                 if (aux)
 375                         *piix4_smba |= 0x20;
 376         } else {
 377                 *smb_en_status = smba_en_lo & 0x01;
 378                 *piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
 379         }
 380
 381         if (!*smb_en_status) {
 382                 dev_err(&PIIX4_dev->dev,
 383                         "SMBus Host Controller not enabled!\n");
 384                 return -ENODEV;
 385         }
 386
 387         return 0;
 388 }
 389
 390 static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
 391                              const struct pci_device_id *id, u8 aux)
 392 {
 393         unsigned short piix4_smba;
 394         u8 smb_en, smb_en_status, port_sel;
 395         u8 i2ccfg, i2ccfg_offset = 0x10;
 396         struct sb800_mmio_cfg mmio_cfg;
 397         int retval;
 398
 399         /* SB800 and later SMBus does not support forcing address */
 400         if (force || force_addr) {
 401                 dev_err(&PIIX4_dev->dev, "SMBus does not support "
 402                         "forcing address!\n");
 403                 return -EINVAL;
 404         }
 405
 406         /* Determine the address of the SMBus areas */
 407         if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
 408              PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
 409              PIIX4_dev->revision >= 0x41) ||
 410             (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
 411              PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
 412              PIIX4_dev->revision >= 0x49) ||
 413             (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON &&
 414              PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS))
 415                 smb_en = 0x00;
 416         else
 417                 smb_en = (aux) ? 0x28 : 0x2c;
 418
 419         retval = piix4_setup_sb800_smba(PIIX4_dev, smb_en, aux, &smb_en_status,
 420                                         &piix4_smba);
 421
 422         if (retval)
 423                 return retval;
 424
 425         if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
 426                 return -ENODEV;
 427
 428         if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 429                 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
 430                         piix4_smba);
 431                 return -EBUSY;
 432         }
 433
 434         /* Aux SMBus does not support IRQ information */
 435         if (aux) {
 436                 dev_info(&PIIX4_dev->dev,
 437                          "Auxiliary SMBus Host Controller at 0x%x\n",
 438                          piix4_smba);
 439                 return piix4_smba;
 440         }
 441
 442         /* Request the SMBus I2C bus config region */
 443         if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
 444                 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
 445                         "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
 446                 release_region(piix4_smba, SMBIOSIZE);
 447                 return -EBUSY;
 448         }
 449         i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
 450         release_region(piix4_smba + i2ccfg_offset, 1);
 451
 452         if (i2ccfg & 1)
 453                 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
 454         else
 455                 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
 456
 457         dev_info(&PIIX4_dev->dev,
 458                  "SMBus Host Controller at 0x%x, revision %d\n",
 459                  piix4_smba, i2ccfg >> 4);
 460
 461         /* Find which register is used for port selection */
 462         if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD ||
 463             PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) {
 464                 if (PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
 465                     (PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
 466                      PIIX4_dev->revision >= 0x1F)) {
 467                         piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
 468                         piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ;
 469                         piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ;
 470                 } else {
 471                         piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT;
 472                         piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
 473                         piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
 474                 }
 475         } else {
 476                 mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev);
 477                 retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg);
 478                 if (retval) {
 479                         release_region(piix4_smba, SMBIOSIZE);
 480                         return retval;
 481                 }
 482
 483                 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX);
 484                 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1);
 485                 piix4_port_sel_sb800 = (port_sel & 0x01) ?
 486                                        SB800_PIIX4_PORT_IDX_ALT :
 487                                        SB800_PIIX4_PORT_IDX;
 488                 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
 489                 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
 490                 piix4_sb800_region_release(&PIIX4_dev->dev, &mmio_cfg);
 491         }
 492
 493         dev_info(&PIIX4_dev->dev,
 494                  "Using register 0x%02x for SMBus port selection\n",
 495                  (unsigned int)piix4_port_sel_sb800);
 496
 497         return piix4_smba;
 498 }
 499
 500 static int piix4_setup_aux(struct pci_dev *PIIX4_dev,
 501                            const struct pci_device_id *id,
 502                            unsigned short base_reg_addr)
 503 {
 504         /* Set up auxiliary SMBus controllers found on some
 505          * AMD chipsets e.g. SP5100 (SB700 derivative) */
 506
 507         unsigned short piix4_smba;
 508
 509         /* Read address of auxiliary SMBus controller */
 510         pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba);
 511         if ((piix4_smba & 1) == 0) {
 512                 dev_dbg(&PIIX4_dev->dev,
 513                         "Auxiliary SMBus controller not enabled\n");
 514                 return -ENODEV;
 515         }
 516
 517         piix4_smba &= 0xfff0;
 518         if (piix4_smba == 0) {
 519                 dev_dbg(&PIIX4_dev->dev,
 520                         "Auxiliary SMBus base address uninitialized\n");
 521                 return -ENODEV;
 522         }
 523
 524         if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
 525                 return -ENODEV;
 526
 527         if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 528                 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x "
 529                         "already in use!\n", piix4_smba);
 530                 return -EBUSY;
 531         }
 532
 533         dev_info(&PIIX4_dev->dev,
 534                  "Auxiliary SMBus Host Controller at 0x%x\n",
 535                  piix4_smba);
 536
 537         return piix4_smba;
 538 }
 539
 540 static int piix4_transaction(struct i2c_adapter *piix4_adapter)
 541 {
 542         struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
 543         unsigned short piix4_smba = adapdata->smba;
 544         int temp;
 545         int result = 0;
 546         int timeout = 0;
 547
 548         dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
 549                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 550                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 551                 inb_p(SMBHSTDAT1));
 552
 553         /* Make sure the SMBus host is ready to start transmitting */
 554         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 555                 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
 556                         "Resetting...\n", temp);
 557                 outb_p(temp, SMBHSTSTS);
 558                 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 559                         dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
 560                         return -EBUSY;
 561                 } else {
 562                         dev_dbg(&piix4_adapter->dev, "Successful!\n");
 563                 }
 564         }
 565
 566         /* start the transaction by setting bit 6 */
 567         outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
 568
 569         /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
 570         if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
 571                 usleep_range(2000, 2100);
 572         else
 573                 usleep_range(250, 500);
 574
 575         while ((++timeout < MAX_TIMEOUT) &&
 576                ((temp = inb_p(SMBHSTSTS)) & 0x01))
 577                 usleep_range(250, 500);
 578
 579         /* If the SMBus is still busy, we give up */
 580         if (timeout == MAX_TIMEOUT) {
 581                 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
 582                 result = -ETIMEDOUT;
 583         }
 584
 585         if (temp & 0x10) {
 586                 result = -EIO;
 587                 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
 588         }
 589
 590         if (temp & 0x08) {
 591                 result = -EIO;
 592                 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
 593                         "locked until next hard reset. (sorry!)\n");
 594                 /* Clock stops and slave is stuck in mid-transmission */
 595         }
 596
 597         if (temp & 0x04) {
 598                 result = -ENXIO;
 599                 dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
 600         }
 601
 602         if (inb_p(SMBHSTSTS) != 0x00)
 603                 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
 604
 605         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 606                 dev_err(&piix4_adapter->dev, "Failed reset at end of "
 607                         "transaction (%02x)\n", temp);
 608         }
 609         dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
 610                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 611                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 612                 inb_p(SMBHSTDAT1));
 613         return result;
 614 }
 615
 616 /* Return negative errno on error. */
 617 static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
 618                  unsigned short flags, char read_write,
 619                  u8 command, int size, union i2c_smbus_data * data)
 620 {
 621         struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
 622         unsigned short piix4_smba = adapdata->smba;
 623         int i, len;
 624         int status;
 625
 626         switch (size) {
 627         case I2C_SMBUS_QUICK:
 628                 outb_p((addr << 1) | read_write,
 629                        SMBHSTADD);
 630                 size = PIIX4_QUICK;
 631                 break;
 632         case I2C_SMBUS_BYTE:
 633                 outb_p((addr << 1) | read_write,
 634                        SMBHSTADD);
 635                 if (read_write == I2C_SMBUS_WRITE)
 636                         outb_p(command, SMBHSTCMD);
 637                 size = PIIX4_BYTE;
 638                 break;
 639         case I2C_SMBUS_BYTE_DATA:
 640                 outb_p((addr << 1) | read_write,
 641                        SMBHSTADD);
 642                 outb_p(command, SMBHSTCMD);
 643                 if (read_write == I2C_SMBUS_WRITE)
 644                         outb_p(data->byte, SMBHSTDAT0);
 645                 size = PIIX4_BYTE_DATA;
 646                 break;
 647         case I2C_SMBUS_WORD_DATA:
 648                 outb_p((addr << 1) | read_write,
 649                        SMBHSTADD);
 650                 outb_p(command, SMBHSTCMD);
 651                 if (read_write == I2C_SMBUS_WRITE) {
 652                         outb_p(data->word & 0xff, SMBHSTDAT0);
 653                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
 654                 }
 655                 size = PIIX4_WORD_DATA;
 656                 break;
 657         case I2C_SMBUS_BLOCK_DATA:
 658                 outb_p((addr << 1) | read_write,
 659                        SMBHSTADD);
 660                 outb_p(command, SMBHSTCMD);
 661                 if (read_write == I2C_SMBUS_WRITE) {
 662                         len = data->block[0];
 663                         if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
 664                                 return -EINVAL;
 665                         outb_p(len, SMBHSTDAT0);
 666                         inb_p(SMBHSTCNT);       /* Reset SMBBLKDAT */
 667                         for (i = 1; i <= len; i++)
 668                                 outb_p(data->block[i], SMBBLKDAT);
 669                 }
 670                 size = PIIX4_BLOCK_DATA;
 671                 break;
 672         default:
 673                 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
 674                 return -EOPNOTSUPP;
 675         }
 676
 677         outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
 678
 679         status = piix4_transaction(adap);
 680         if (status)
 681                 return status;
 682
 683         if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
 684                 return 0;
 685
 686
 687         switch (size) {
 688         case PIIX4_BYTE:
 689         case PIIX4_BYTE_DATA:
 690                 data->byte = inb_p(SMBHSTDAT0);
 691                 break;
 692         case PIIX4_WORD_DATA:
 693                 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
 694                 break;
 695         case PIIX4_BLOCK_DATA:
 696                 data->block[0] = inb_p(SMBHSTDAT0);
 697                 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 698                         return -EPROTO;
 699                 inb_p(SMBHSTCNT);       /* Reset SMBBLKDAT */
 700                 for (i = 1; i <= data->block[0]; i++)
 701                         data->block[i] = inb_p(SMBBLKDAT);
 702                 break;
 703         }
 704         return 0;
 705 }
 706
 707 static uint8_t piix4_imc_read(uint8_t idx)
 708 {
 709         outb_p(idx, KERNCZ_IMC_IDX);
 710         return inb_p(KERNCZ_IMC_DATA);
 711 }
 712
 713 static void piix4_imc_write(uint8_t idx, uint8_t value)
 714 {
 715         outb_p(idx, KERNCZ_IMC_IDX);
 716         outb_p(value, KERNCZ_IMC_DATA);
 717 }
 718
 719 static int piix4_imc_sleep(void)
 720 {
 721         int timeout = MAX_TIMEOUT;
 722
 723         if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
 724                 return -EBUSY;
 725
 726         /* clear response register */
 727         piix4_imc_write(0x82, 0x00);
 728         /* request ownership flag */
 729         piix4_imc_write(0x83, 0xB4);
 730         /* kick off IMC Mailbox command 96 */
 731         piix4_imc_write(0x80, 0x96);
 732
 733         while (timeout--) {
 734                 if (piix4_imc_read(0x82) == 0xfa) {
 735                         release_region(KERNCZ_IMC_IDX, 2);
 736                         return 0;
 737                 }
 738                 usleep_range(1000, 2000);
 739         }
 740
 741         release_region(KERNCZ_IMC_IDX, 2);
 742         return -ETIMEDOUT;
 743 }
 744
 745 static void piix4_imc_wakeup(void)
 746 {
 747         int timeout = MAX_TIMEOUT;
 748
 749         if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
 750                 return;
 751
 752         /* clear response register */
 753         piix4_imc_write(0x82, 0x00);
 754         /* release ownership flag */
 755         piix4_imc_write(0x83, 0xB5);
 756         /* kick off IMC Mailbox command 96 */
 757         piix4_imc_write(0x80, 0x96);
 758
 759         while (timeout--) {
 760                 if (piix4_imc_read(0x82) == 0xfa)
 761                         break;
 762                 usleep_range(1000, 2000);
 763         }
 764
 765         release_region(KERNCZ_IMC_IDX, 2);
 766 }
 767
 768 static int piix4_sb800_port_sel(u8 port, struct sb800_mmio_cfg *mmio_cfg)
 769 {
 770         u8 smba_en_lo, val;
 771
 772         if (mmio_cfg->use_mmio) {
 773                 smba_en_lo = ioread8(mmio_cfg->addr + piix4_port_sel_sb800);
 774                 val = (smba_en_lo & ~piix4_port_mask_sb800) | port;
 775                 if (smba_en_lo != val)
 776                         iowrite8(val, mmio_cfg->addr + piix4_port_sel_sb800);
 777
 778                 return (smba_en_lo & piix4_port_mask_sb800);
 779         }
 780
 781         outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX);
 782         smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
 783
 784         val = (smba_en_lo & ~piix4_port_mask_sb800) | port;
 785         if (smba_en_lo != val)
 786                 outb_p(val, SB800_PIIX4_SMB_IDX + 1);
 787
 788         return (smba_en_lo & piix4_port_mask_sb800);
 789 }
 790
 791 /*
 792  * Handles access to multiple SMBus ports on the SB800.
 793  * The port is selected by bits 2:1 of the smb_en register (0x2c).
 794  * Returns negative errno on error.
 795  *
 796  * Note: The selected port must be returned to the initial selection to avoid
 797  * problems on certain systems.
 798  */
 799 static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr,
 800                  unsigned short flags, char read_write,
 801                  u8 command, int size, union i2c_smbus_data *data)
 802 {
 803         struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
 804         unsigned short piix4_smba = adapdata->smba;
 805         int retries = MAX_TIMEOUT;
 806         int smbslvcnt;
 807         u8 prev_port;
 808         int retval;
 809
 810         retval = piix4_sb800_region_request(&adap->dev, &adapdata->mmio_cfg);
 811         if (retval)
 812                 return retval;
 813
 814         /* Request the SMBUS semaphore, avoid conflicts with the IMC */
 815         smbslvcnt  = inb_p(SMBSLVCNT);
 816         do {
 817                 outb_p(smbslvcnt | 0x10, SMBSLVCNT);
 818
 819                 /* Check the semaphore status */
 820                 smbslvcnt  = inb_p(SMBSLVCNT);
 821                 if (smbslvcnt & 0x10)
 822                         break;
 823
 824                 usleep_range(1000, 2000);
 825         } while (--retries);
 826         /* SMBus is still owned by the IMC, we give up */
 827         if (!retries) {
 828                 retval = -EBUSY;
 829                 goto release;
 830         }
 831
 832         /*
 833          * Notify the IMC (Integrated Micro Controller) if required.
 834          * Among other responsibilities, the IMC is in charge of monitoring
 835          * the System fans and temperature sensors, and act accordingly.
 836          * All this is done through SMBus and can/will collide
 837          * with our transactions if they are long (BLOCK_DATA).
 838          * Therefore we need to request the ownership flag during those
 839          * transactions.
 840          */
 841         if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) {
 842                 int ret;
 843
 844                 ret = piix4_imc_sleep();
 845                 switch (ret) {
 846                 case -EBUSY:
 847                         dev_warn(&adap->dev,
 848                                  "IMC base address index region 0x%x already in use.\n",
 849                                  KERNCZ_IMC_IDX);
 850                         break;
 851                 case -ETIMEDOUT:
 852                         dev_warn(&adap->dev,
 853                                  "Failed to communicate with the IMC.\n");
 854                         break;
 855                 default:
 856                         break;
 857                 }
 858
 859                 /* If IMC communication fails do not retry */
 860                 if (ret) {
 861                         dev_warn(&adap->dev,
 862                                  "Continuing without IMC notification.\n");
 863                         adapdata->notify_imc = false;
 864                 }
 865         }
 866
 867         prev_port = piix4_sb800_port_sel(adapdata->port, &adapdata->mmio_cfg);
 868
 869         retval = piix4_access(adap, addr, flags, read_write,
 870                               command, size, data);
 871
 872         piix4_sb800_port_sel(prev_port, &adapdata->mmio_cfg);
 873
 874         /* Release the semaphore */
 875         outb_p(smbslvcnt | 0x20, SMBSLVCNT);
 876
 877         if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc)
 878                 piix4_imc_wakeup();
 879
 880 release:
 881         piix4_sb800_region_release(&adap->dev, &adapdata->mmio_cfg);
 882         return retval;
 883 }
 884
 885 static u32 piix4_func(struct i2c_adapter *adapter)
 886 {
 887         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 888             I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 889             I2C_FUNC_SMBUS_BLOCK_DATA;
 890 }
 891
 892 static const struct i2c_algorithm smbus_algorithm = {
 893         .smbus_xfer     = piix4_access,
 894         .functionality  = piix4_func,
 895 };
 896
 897 static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = {
 898         .smbus_xfer     = piix4_access_sb800,
 899         .functionality  = piix4_func,
 900 };
 901
 902 static const struct pci_device_id piix4_ids[] = {
 903         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
 904         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
 905         { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
 906         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
 907         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
 908         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
 909         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
 910         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
 911         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
 912         { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
 913         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 914                      PCI_DEVICE_ID_SERVERWORKS_OSB4) },
 915         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 916                      PCI_DEVICE_ID_SERVERWORKS_CSB5) },
 917         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 918                      PCI_DEVICE_ID_SERVERWORKS_CSB6) },
 919         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 920                      PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
 921         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 922                      PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
 923         { 0, }
 924 };
 925
 926 MODULE_DEVICE_TABLE (pci, piix4_ids);
 927
 928 static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS];
 929 static struct i2c_adapter *piix4_aux_adapter;
 930 static int piix4_adapter_count;
 931
 932 static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
 933                              bool sb800_main, u8 port, bool notify_imc,
 934                              u8 hw_port_nr, const char *name,
 935                              struct i2c_adapter **padap)
 936 {
 937         struct i2c_adapter *adap;
 938         struct i2c_piix4_adapdata *adapdata;
 939         int retval;
 940
 941         adap = kzalloc(sizeof(*adap), GFP_KERNEL);
 942         if (adap == NULL) {
 943                 release_region(smba, SMBIOSIZE);
 944                 return -ENOMEM;
 945         }
 946
 947         adap->owner = THIS_MODULE;
 948         adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 949         adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800
 950                                 : &smbus_algorithm;
 951
 952         adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
 953         if (adapdata == NULL) {
 954                 kfree(adap);
 955                 release_region(smba, SMBIOSIZE);
 956                 return -ENOMEM;
 957         }
 958
 959         adapdata->mmio_cfg.use_mmio = piix4_sb800_use_mmio(dev);
 960         adapdata->smba = smba;
 961         adapdata->sb800_main = sb800_main;
 962         adapdata->port = port << piix4_port_shift_sb800;
 963         adapdata->notify_imc = notify_imc;
 964
 965         /* set up the sysfs linkage to our parent device */
 966         adap->dev.parent = &dev->dev;
 967
 968         if (has_acpi_companion(&dev->dev)) {
 969                 acpi_preset_companion(&adap->dev,
 970                                       ACPI_COMPANION(&dev->dev),
 971                                       hw_port_nr);
 972         }
 973
 974         snprintf(adap->name, sizeof(adap->name),
 975                 "SMBus PIIX4 adapter%s at %04x", name, smba);
 976
 977         i2c_set_adapdata(adap, adapdata);
 978
 979         retval = i2c_add_adapter(adap);
 980         if (retval) {
 981                 kfree(adapdata);
 982                 kfree(adap);
 983                 release_region(smba, SMBIOSIZE);
 984                 return retval;
 985         }
 986
 987         *padap = adap;
 988         return 0;
 989 }
 990
 991 static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba,
 992                                     bool notify_imc)
 993 {
 994         struct i2c_piix4_adapdata *adapdata;
 995         int port;
 996         int retval;
 997
 998         if (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
 999             (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
1000              dev->revision >= 0x1F)) {
1001                 piix4_adapter_count = HUDSON2_MAIN_PORTS;
1002         } else {
1003                 piix4_adapter_count = PIIX4_MAX_ADAPTERS;
1004         }
1005
1006         for (port = 0; port < piix4_adapter_count; port++) {
1007                 u8 hw_port_nr = port == 0 ? 0 : port + 1;
1008
1009                 retval = piix4_add_adapter(dev, smba, true, port, notify_imc,
1010                                            hw_port_nr,
1011                                            piix4_main_port_names_sb800[port],
1012                                            &piix4_main_adapters[port]);
1013                 if (retval < 0)
1014                         goto error;
1015         }
1016
1017         return retval;
1018
1019 error:
1020         dev_err(&dev->dev,
1021                 "Error setting up SB800 adapters. Unregistering!\n");
1022         while (--port >= 0) {
1023                 adapdata = i2c_get_adapdata(piix4_main_adapters[port]);
1024                 if (adapdata->smba) {
1025                         i2c_del_adapter(piix4_main_adapters[port]);
1026                         kfree(adapdata);
1027                         kfree(piix4_main_adapters[port]);
1028                         piix4_main_adapters[port] = NULL;
1029                 }
1030         }
1031
1032         return retval;
1033 }
1034
1035 static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
1036 {
1037         int retval;
1038         bool is_sb800 = false;
1039
1040         if ((dev->vendor == PCI_VENDOR_ID_ATI &&
1041              dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
1042              dev->revision >= 0x40) ||
1043             dev->vendor == PCI_VENDOR_ID_AMD ||
1044             dev->vendor == PCI_VENDOR_ID_HYGON) {
1045                 bool notify_imc = false;
1046                 is_sb800 = true;
1047
1048                 if ((dev->vendor == PCI_VENDOR_ID_AMD ||
1049                      dev->vendor == PCI_VENDOR_ID_HYGON) &&
1050                     dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
1051                         u8 imc;
1052
1053                         /*
1054                          * Detect if IMC is active or not, this method is
1055                          * described on coreboot's AMD IMC notes
1056                          */
1057                         pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3),
1058                                                  0x40, &imc);
1059                         if (imc & 0x80)
1060                                 notify_imc = true;
1061                 }
1062
1063                 /* base address location etc changed in SB800 */
1064                 retval = piix4_setup_sb800(dev, id, 0);
1065                 if (retval < 0)
1066                         return retval;
1067
1068                 /*
1069                  * Try to register multiplexed main SMBus adapter,
1070                  * give up if we can't
1071                  */
1072                 retval = piix4_add_adapters_sb800(dev, retval, notify_imc);
1073                 if (retval < 0)
1074                         return retval;
1075         } else {
1076                 retval = piix4_setup(dev, id);
1077                 if (retval < 0)
1078                         return retval;
1079
1080                 /* Try to register main SMBus adapter, give up if we can't */
1081                 retval = piix4_add_adapter(dev, retval, false, 0, false, 0,
1082                                            "", &piix4_main_adapters[0]);
1083                 if (retval < 0)
1084                         return retval;
1085         }
1086
1087         /* Check for auxiliary SMBus on some AMD chipsets */
1088         retval = -ENODEV;
1089
1090         if (dev->vendor == PCI_VENDOR_ID_ATI &&
1091             dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) {
1092                 if (dev->revision < 0x40) {
1093                         retval = piix4_setup_aux(dev, id, 0x58);
1094                 } else {
1095                         /* SB800 added aux bus too */
1096                         retval = piix4_setup_sb800(dev, id, 1);
1097                 }
1098         }
1099
1100         if (dev->vendor == PCI_VENDOR_ID_AMD &&
1101             (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS ||
1102              dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) {
1103                 retval = piix4_setup_sb800(dev, id, 1);
1104         }
1105
1106         if (retval > 0) {
1107                 /* Try to add the aux adapter if it exists,
1108                  * piix4_add_adapter will clean up if this fails */
1109                 piix4_add_adapter(dev, retval, false, 0, false, 1,
1110                                   is_sb800 ? piix4_aux_port_name_sb800 : "",
1111                                   &piix4_aux_adapter);
1112         }
1113
1114         return 0;
1115 }
1116
1117 static void piix4_adap_remove(struct i2c_adapter *adap)
1118 {
1119         struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
1120
1121         if (adapdata->smba) {
1122                 i2c_del_adapter(adap);
1123                 if (adapdata->port == (0 << piix4_port_shift_sb800))
1124                         release_region(adapdata->smba, SMBIOSIZE);
1125                 kfree(adapdata);
1126                 kfree(adap);
1127         }
1128 }
1129
1130 static void piix4_remove(struct pci_dev *dev)
1131 {
1132         int port = piix4_adapter_count;
1133
1134         while (--port >= 0) {
1135                 if (piix4_main_adapters[port]) {
1136                         piix4_adap_remove(piix4_main_adapters[port]);
1137                         piix4_main_adapters[port] = NULL;
1138                 }
1139         }
1140
1141         if (piix4_aux_adapter) {
1142                 piix4_adap_remove(piix4_aux_adapter);
1143                 piix4_aux_adapter = NULL;
1144         }
1145 }
1146
1147 static struct pci_driver piix4_driver = {
1148         .name           = "piix4_smbus",
1149         .id_table       = piix4_ids,
1150         .probe          = piix4_probe,
1151         .remove         = piix4_remove,
1152 };
1153
1154 module_pci_driver(piix4_driver);
1155
1156 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>");
1157 MODULE_AUTHOR("Philip Edelbrock <phil@netroedge.com>");
1158 MODULE_DESCRIPTION("PIIX4 SMBus driver");
1159 MODULE_LICENSE("GPL");