drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Copyright (C) 2004 - 2007 Texas Instruments.
   7  *
   8  * Originally written by MontaVista Software, Inc.
   9  * Additional contributions by:
  10  *      Tony Lindgren <tony@atomide.com>
  11  *      Imre Deak <imre.deak@nokia.com>
  12  *      Juha Yrjölä <juha.yrjola@solidboot.com>
  13  *      Syed Khasim <x0khasim@ti.com>
  14  *      Nishant Menon <nm@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 #include <linux/module.h>
  32 #include <linux/delay.h>
  33 #include <linux/i2c.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/completion.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/clk.h>
  39 #include <linux/io.h>
  40 #include <linux/of.h>
  41 #include <linux/of_device.h>
  42 #include <linux/slab.h>
  43 #include <linux/i2c-omap.h>
  44 #include <linux/pm_runtime.h>
  45
  46 /* I2C controller revisions */
  47 #define OMAP_I2C_OMAP1_REV_2            0x20
  48
  49 /* I2C controller revisions present on specific hardware */
  50 #define OMAP_I2C_REV_ON_2430            0x00000036
  51 #define OMAP_I2C_REV_ON_3430_3530       0x0000003C
  52 #define OMAP_I2C_REV_ON_3630            0x00000040
  53 #define OMAP_I2C_REV_ON_4430_PLUS       0x50400002
  54
  55 /* timeout waiting for the controller to respond */
  56 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  57
  58 /* timeout for pm runtime autosuspend */
  59 #define OMAP_I2C_PM_TIMEOUT             1000    /* ms */
  60
  61 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
  62 enum {
  63         OMAP_I2C_REV_REG = 0,
  64         OMAP_I2C_IE_REG,
  65         OMAP_I2C_STAT_REG,
  66         OMAP_I2C_IV_REG,
  67         OMAP_I2C_WE_REG,
  68         OMAP_I2C_SYSS_REG,
  69         OMAP_I2C_BUF_REG,
  70         OMAP_I2C_CNT_REG,
  71         OMAP_I2C_DATA_REG,
  72         OMAP_I2C_SYSC_REG,
  73         OMAP_I2C_CON_REG,
  74         OMAP_I2C_OA_REG,
  75         OMAP_I2C_SA_REG,
  76         OMAP_I2C_PSC_REG,
  77         OMAP_I2C_SCLL_REG,
  78         OMAP_I2C_SCLH_REG,
  79         OMAP_I2C_SYSTEST_REG,
  80         OMAP_I2C_BUFSTAT_REG,
  81         /* only on OMAP4430 */
  82         OMAP_I2C_IP_V2_REVNB_LO,
  83         OMAP_I2C_IP_V2_REVNB_HI,
  84         OMAP_I2C_IP_V2_IRQSTATUS_RAW,
  85         OMAP_I2C_IP_V2_IRQENABLE_SET,
  86         OMAP_I2C_IP_V2_IRQENABLE_CLR,
  87 };
  88
  89 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  90 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
  91 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
  92 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  93 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  94 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  95 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  96 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  97
  98 /* I2C Status Register (OMAP_I2C_STAT): */
  99 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
 100 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
 101 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
 102 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
 103 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
 104 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
 105 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
 106 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
 107 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
 108 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
 109 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
 110 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
 111
 112 /* I2C WE wakeup enable register */
 113 #define OMAP_I2C_WE_XDR_WE      (1 << 14)       /* TX drain wakup */
 114 #define OMAP_I2C_WE_RDR_WE      (1 << 13)       /* RX drain wakeup */
 115 #define OMAP_I2C_WE_AAS_WE      (1 << 9)        /* Address as slave wakeup*/
 116 #define OMAP_I2C_WE_BF_WE       (1 << 8)        /* Bus free wakeup */
 117 #define OMAP_I2C_WE_STC_WE      (1 << 6)        /* Start condition wakeup */
 118 #define OMAP_I2C_WE_GC_WE       (1 << 5)        /* General call wakeup */
 119 #define OMAP_I2C_WE_DRDY_WE     (1 << 3)        /* TX/RX data ready wakeup */
 120 #define OMAP_I2C_WE_ARDY_WE     (1 << 2)        /* Reg access ready wakeup */
 121 #define OMAP_I2C_WE_NACK_WE     (1 << 1)        /* No acknowledgment wakeup */
 122 #define OMAP_I2C_WE_AL_WE       (1 << 0)        /* Arbitration lost wakeup */
 123
 124 #define OMAP_I2C_WE_ALL         (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
 125                                 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
 126                                 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
 127                                 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
 128                                 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
 129
 130 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
 131 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
 132 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
 133 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
 134 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
 135
 136 /* I2C Configuration Register (OMAP_I2C_CON): */
 137 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
 138 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
 139 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
 140 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 141 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 142 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 143 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 144 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 145 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 146 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 147
 148 /* I2C SCL time value when Master */
 149 #define OMAP_I2C_SCLL_HSSCLL    8
 150 #define OMAP_I2C_SCLH_HSSCLH    8
 151
 152 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 153 #ifdef DEBUG
 154 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 155 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 156 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 157 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 158 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 159 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 160 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 161 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 162 #endif
 163
 164 /* OCP_SYSSTATUS bit definitions */
 165 #define SYSS_RESETDONE_MASK             (1 << 0)
 166
 167 /* OCP_SYSCONFIG bit definitions */
 168 #define SYSC_CLOCKACTIVITY_MASK         (0x3 << 8)
 169 #define SYSC_SIDLEMODE_MASK             (0x3 << 3)
 170 #define SYSC_ENAWAKEUP_MASK             (1 << 2)
 171 #define SYSC_SOFTRESET_MASK             (1 << 1)
 172 #define SYSC_AUTOIDLE_MASK              (1 << 0)
 173
 174 #define SYSC_IDLEMODE_SMART             0x2
 175 #define SYSC_CLOCKACTIVITY_FCLK         0x2
 176
 177 /* Errata definitions */
 178 #define I2C_OMAP_ERRATA_I207            (1 << 0)
 179 #define I2C_OMAP_ERRATA_I462            (1 << 1)
 180
 181 #define OMAP_I2C_IP_V2_INTERRUPTS_MASK  0x6FFF
 182
 183 struct omap_i2c_dev {
 184         spinlock_t              lock;           /* IRQ synchronization */
 185         struct device           *dev;
 186         void __iomem            *base;          /* virtual */
 187         int                     irq;
 188         int                     reg_shift;      /* bit shift for I2C register addresses */
 189         struct completion       cmd_complete;
 190         struct resource         *ioarea;
 191         u32                     latency;        /* maximum mpu wkup latency */
 192         void                    (*set_mpu_wkup_lat)(struct device *dev,
 193                                                     long latency);
 194         u32                     speed;          /* Speed of bus in kHz */
 195         u32                     flags;
 196         u16                     scheme;
 197         u16                     cmd_err;
 198         u8                      *buf;
 199         u8                      *regs;
 200         size_t                  buf_len;
 201         struct i2c_adapter      adapter;
 202         u8                      threshold;
 203         u8                      fifo_size;      /* use as flag and value
 204                                                  * fifo_size==0 implies no fifo
 205                                                  * if set, should be trsh+1
 206                                                  */
 207         u32                     rev;
 208         unsigned                b_hw:1;         /* bad h/w fixes */
 209         unsigned                receiver:1;     /* true when we're in receiver mode */
 210         u16                     iestate;        /* Saved interrupt register */
 211         u16                     pscstate;
 212         u16                     scllstate;
 213         u16                     sclhstate;
 214         u16                     syscstate;
 215         u16                     westate;
 216         u16                     errata;
 217 };
 218
 219 static const u8 reg_map_ip_v1[] = {
 220         [OMAP_I2C_REV_REG] = 0x00,
 221         [OMAP_I2C_IE_REG] = 0x01,
 222         [OMAP_I2C_STAT_REG] = 0x02,
 223         [OMAP_I2C_IV_REG] = 0x03,
 224         [OMAP_I2C_WE_REG] = 0x03,
 225         [OMAP_I2C_SYSS_REG] = 0x04,
 226         [OMAP_I2C_BUF_REG] = 0x05,
 227         [OMAP_I2C_CNT_REG] = 0x06,
 228         [OMAP_I2C_DATA_REG] = 0x07,
 229         [OMAP_I2C_SYSC_REG] = 0x08,
 230         [OMAP_I2C_CON_REG] = 0x09,
 231         [OMAP_I2C_OA_REG] = 0x0a,
 232         [OMAP_I2C_SA_REG] = 0x0b,
 233         [OMAP_I2C_PSC_REG] = 0x0c,
 234         [OMAP_I2C_SCLL_REG] = 0x0d,
 235         [OMAP_I2C_SCLH_REG] = 0x0e,
 236         [OMAP_I2C_SYSTEST_REG] = 0x0f,
 237         [OMAP_I2C_BUFSTAT_REG] = 0x10,
 238 };
 239
 240 static const u8 reg_map_ip_v2[] = {
 241         [OMAP_I2C_REV_REG] = 0x04,
 242         [OMAP_I2C_IE_REG] = 0x2c,
 243         [OMAP_I2C_STAT_REG] = 0x28,
 244         [OMAP_I2C_IV_REG] = 0x34,
 245         [OMAP_I2C_WE_REG] = 0x34,
 246         [OMAP_I2C_SYSS_REG] = 0x90,
 247         [OMAP_I2C_BUF_REG] = 0x94,
 248         [OMAP_I2C_CNT_REG] = 0x98,
 249         [OMAP_I2C_DATA_REG] = 0x9c,
 250         [OMAP_I2C_SYSC_REG] = 0x10,
 251         [OMAP_I2C_CON_REG] = 0xa4,
 252         [OMAP_I2C_OA_REG] = 0xa8,
 253         [OMAP_I2C_SA_REG] = 0xac,
 254         [OMAP_I2C_PSC_REG] = 0xb0,
 255         [OMAP_I2C_SCLL_REG] = 0xb4,
 256         [OMAP_I2C_SCLH_REG] = 0xb8,
 257         [OMAP_I2C_SYSTEST_REG] = 0xbC,
 258         [OMAP_I2C_BUFSTAT_REG] = 0xc0,
 259         [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
 260         [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
 261         [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
 262         [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
 263         [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
 264 };
 265
 266 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 267                                       int reg, u16 val)
 268 {
 269         writew_relaxed(val, i2c_dev->base +
 270                         (i2c_dev->regs[reg] << i2c_dev->reg_shift));
 271 }
 272
 273 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 274 {
 275         return readw_relaxed(i2c_dev->base +
 276                                 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
 277 }
 278
 279 static void __omap_i2c_init(struct omap_i2c_dev *dev)
 280 {
 281
 282         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 283
 284         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 285         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
 286
 287         /* SCL low and high time values */
 288         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
 289         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
 290         if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
 291                 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
 292
 293         /* Take the I2C module out of reset: */
 294         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 295
 296         /*
 297          * Don't write to this register if the IE state is 0 as it can
 298          * cause deadlock.
 299          */
 300         if (dev->iestate)
 301                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 302 }
 303
 304 static int omap_i2c_reset(struct omap_i2c_dev *dev)
 305 {
 306         unsigned long timeout;
 307         u16 sysc;
 308
 309         if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
 310                 sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG);
 311
 312                 /* Disable I2C controller before soft reset */
 313                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 314                         omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
 315                                 ~(OMAP_I2C_CON_EN));
 316
 317                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
 318                 /* For some reason we need to set the EN bit before the
 319                  * reset done bit gets set. */
 320                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 321                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 322                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 323                          SYSS_RESETDONE_MASK)) {
 324                         if (time_after(jiffies, timeout)) {
 325                                 dev_warn(dev->dev, "timeout waiting "
 326                                                 "for controller reset\n");
 327                                 return -ETIMEDOUT;
 328                         }
 329                         msleep(1);
 330                 }
 331
 332                 /* SYSC register is cleared by the reset; rewrite it */
 333                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);
 334
 335         }
 336         return 0;
 337 }
 338
 339 static int omap_i2c_init(struct omap_i2c_dev *dev)
 340 {
 341         u16 psc = 0, scll = 0, sclh = 0;
 342         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 343         unsigned long fclk_rate = 12000000;
 344         unsigned long internal_clk = 0;
 345         struct clk *fclk;
 346
 347         if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
 348                 /*
 349                  * Enabling all wakup sources to stop I2C freezing on
 350                  * WFI instruction.
 351                  * REVISIT: Some wkup sources might not be needed.
 352                  */
 353                 dev->westate = OMAP_I2C_WE_ALL;
 354         }
 355
 356         if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
 357                 /*
 358                  * The I2C functional clock is the armxor_ck, so there's
 359                  * no need to get "armxor_ck" separately.  Now, if OMAP2420
 360                  * always returns 12MHz for the functional clock, we can
 361                  * do this bit unconditionally.
 362                  */
 363                 fclk = clk_get(dev->dev, "fck");
 364                 fclk_rate = clk_get_rate(fclk);
 365                 clk_put(fclk);
 366
 367                 /* TRM for 5912 says the I2C clock must be prescaled to be
 368                  * between 7 - 12 MHz. The XOR input clock is typically
 369                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 370                  *
 371                  * XOR MHz      Divider         Prescaler
 372                  * 12           1               0
 373                  * 13           2               1
 374                  * 19.2         2               1
 375                  */
 376                 if (fclk_rate > 12000000)
 377                         psc = fclk_rate / 12000000;
 378         }
 379
 380         if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
 381
 382                 /*
 383                  * HSI2C controller internal clk rate should be 19.2 Mhz for
 384                  * HS and for all modes on 2430. On 34xx we can use lower rate
 385                  * to get longer filter period for better noise suppression.
 386                  * The filter is iclk (fclk for HS) period.
 387                  */
 388                 if (dev->speed > 400 ||
 389                                dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
 390                         internal_clk = 19200;
 391                 else if (dev->speed > 100)
 392                         internal_clk = 9600;
 393                 else
 394                         internal_clk = 4000;
 395                 fclk = clk_get(dev->dev, "fck");
 396                 fclk_rate = clk_get_rate(fclk) / 1000;
 397                 clk_put(fclk);
 398
 399                 /* Compute prescaler divisor */
 400                 psc = fclk_rate / internal_clk;
 401                 psc = psc - 1;
 402
 403                 /* If configured for High Speed */
 404                 if (dev->speed > 400) {
 405                         unsigned long scl;
 406
 407                         /* For first phase of HS mode */
 408                         scl = internal_clk / 400;
 409                         fsscll = scl - (scl / 3) - 7;
 410                         fssclh = (scl / 3) - 5;
 411
 412                         /* For second phase of HS mode */
 413                         scl = fclk_rate / dev->speed;
 414                         hsscll = scl - (scl / 3) - 7;
 415                         hssclh = (scl / 3) - 5;
 416                 } else if (dev->speed > 100) {
 417                         unsigned long scl;
 418
 419                         /* Fast mode */
 420                         scl = internal_clk / dev->speed;
 421                         fsscll = scl - (scl / 3) - 7;
 422                         fssclh = (scl / 3) - 5;
 423                 } else {
 424                         /* Standard mode */
 425                         fsscll = internal_clk / (dev->speed * 2) - 7;
 426                         fssclh = internal_clk / (dev->speed * 2) - 5;
 427                 }
 428                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 429                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 430         } else {
 431                 /* Program desired operating rate */
 432                 fclk_rate /= (psc + 1) * 1000;
 433                 if (psc > 2)
 434                         psc = 2;
 435                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
 436                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
 437         }
 438
 439         dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 440                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 441                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
 442                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
 443
 444         dev->pscstate = psc;
 445         dev->scllstate = scll;
 446         dev->sclhstate = sclh;
 447
 448         __omap_i2c_init(dev);
 449
 450         return 0;
 451 }
 452
 453 /*
 454  * Waiting on Bus Busy
 455  */
 456 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 457 {
 458         unsigned long timeout;
 459
 460         timeout = jiffies + OMAP_I2C_TIMEOUT;
 461         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 462                 if (time_after(jiffies, timeout)) {
 463                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 464                         return -ETIMEDOUT;
 465                 }
 466                 msleep(1);
 467         }
 468
 469         return 0;
 470 }
 471
 472 static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
 473 {
 474         u16             buf;
 475
 476         if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
 477                 return;
 478
 479         /*
 480          * Set up notification threshold based on message size. We're doing
 481          * this to try and avoid draining feature as much as possible. Whenever
 482          * we have big messages to transfer (bigger than our total fifo size)
 483          * then we might use draining feature to transfer the remaining bytes.
 484          */
 485
 486         dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
 487
 488         buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
 489
 490         if (is_rx) {
 491                 /* Clear RX Threshold */
 492                 buf &= ~(0x3f << 8);
 493                 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
 494         } else {
 495                 /* Clear TX Threshold */
 496                 buf &= ~0x3f;
 497                 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
 498         }
 499
 500         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
 501
 502         if (dev->rev < OMAP_I2C_REV_ON_3630)
 503                 dev->b_hw = 1; /* Enable hardware fixes */
 504
 505         /* calculate wakeup latency constraint for MPU */
 506         if (dev->set_mpu_wkup_lat != NULL)
 507                 dev->latency = (1000000 * dev->threshold) /
 508                         (1000 * dev->speed / 8);
 509 }
 510
 511 /*
 512  * Low level master read/write transaction.
 513  */
 514 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 515                              struct i2c_msg *msg, int stop)
 516 {
 517         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 518         unsigned long timeout;
 519         u16 w;
 520
 521         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 522                 msg->addr, msg->len, msg->flags, stop);
 523
 524         if (msg->len == 0)
 525                 return -EINVAL;
 526
 527         dev->receiver = !!(msg->flags & I2C_M_RD);
 528         omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
 529
 530         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 531
 532         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 533         dev->buf = msg->buf;
 534         dev->buf_len = msg->len;
 535
 536         /* make sure writes to dev->buf_len are ordered */
 537         barrier();
 538
 539         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 540
 541         /* Clear the FIFO Buffers */
 542         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
 543         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
 544         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
 545
 546         reinit_completion(&dev->cmd_complete);
 547         dev->cmd_err = 0;
 548
 549         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 550
 551         /* High speed configuration */
 552         if (dev->speed > 400)
 553                 w |= OMAP_I2C_CON_OPMODE_HS;
 554
 555         if (msg->flags & I2C_M_STOP)
 556                 stop = 1;
 557         if (msg->flags & I2C_M_TEN)
 558                 w |= OMAP_I2C_CON_XA;
 559         if (!(msg->flags & I2C_M_RD))
 560                 w |= OMAP_I2C_CON_TRX;
 561
 562         if (!dev->b_hw && stop)
 563                 w |= OMAP_I2C_CON_STP;
 564
 565         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 566
 567         /*
 568          * Don't write stt and stp together on some hardware.
 569          */
 570         if (dev->b_hw && stop) {
 571                 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
 572                 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 573                 while (con & OMAP_I2C_CON_STT) {
 574                         con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 575
 576                         /* Let the user know if i2c is in a bad state */
 577                         if (time_after(jiffies, delay)) {
 578                                 dev_err(dev->dev, "controller timed out "
 579                                 "waiting for start condition to finish\n");
 580                                 return -ETIMEDOUT;
 581                         }
 582                         cpu_relax();
 583                 }
 584
 585                 w |= OMAP_I2C_CON_STP;
 586                 w &= ~OMAP_I2C_CON_STT;
 587                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 588         }
 589
 590         /*
 591          * REVISIT: We should abort the transfer on signals, but the bus goes
 592          * into arbitration and we're currently unable to recover from it.
 593          */
 594         timeout = wait_for_completion_timeout(&dev->cmd_complete,
 595                                                 OMAP_I2C_TIMEOUT);
 596         if (timeout == 0) {
 597                 dev_err(dev->dev, "controller timed out\n");
 598                 omap_i2c_reset(dev);
 599                 __omap_i2c_init(dev);
 600                 return -ETIMEDOUT;
 601         }
 602
 603         if (likely(!dev->cmd_err))
 604                 return 0;
 605
 606         /* We have an error */
 607         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 608                             OMAP_I2C_STAT_XUDF)) {
 609                 omap_i2c_reset(dev);
 610                 __omap_i2c_init(dev);
 611                 return -EIO;
 612         }
 613
 614         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 615                 if (msg->flags & I2C_M_IGNORE_NAK)
 616                         return 0;
 617
 618                 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 619                 w |= OMAP_I2C_CON_STP;
 620                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 621                 return -EREMOTEIO;
 622         }
 623         return -EIO;
 624 }
 625
 626
 627 /*
 628  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 629  * to do the work during IRQ processing.
 630  */
 631 static int
 632 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 633 {
 634         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 635         int i;
 636         int r;
 637
 638         r = pm_runtime_get_sync(dev->dev);
 639         if (IS_ERR_VALUE(r))
 640                 goto out;
 641
 642         r = omap_i2c_wait_for_bb(dev);
 643         if (r < 0)
 644                 goto out;
 645
 646         if (dev->set_mpu_wkup_lat != NULL)
 647                 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
 648
 649         for (i = 0; i < num; i++) {
 650                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 651                 if (r != 0)
 652                         break;
 653         }
 654
 655         if (r == 0)
 656                 r = num;
 657
 658         omap_i2c_wait_for_bb(dev);
 659
 660         if (dev->set_mpu_wkup_lat != NULL)
 661                 dev->set_mpu_wkup_lat(dev->dev, -1);
 662
 663 out:
 664         pm_runtime_mark_last_busy(dev->dev);
 665         pm_runtime_put_autosuspend(dev->dev);
 666         return r;
 667 }
 668
 669 static u32
 670 omap_i2c_func(struct i2c_adapter *adap)
 671 {
 672         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
 673                I2C_FUNC_PROTOCOL_MANGLING;
 674 }
 675
 676 static inline void
 677 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 678 {
 679         dev->cmd_err |= err;
 680         complete(&dev->cmd_complete);
 681 }
 682
 683 static inline void
 684 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 685 {
 686         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 687 }
 688
 689 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
 690 {
 691         /*
 692          * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
 693          * Not applicable for OMAP4.
 694          * Under certain rare conditions, RDR could be set again
 695          * when the bus is busy, then ignore the interrupt and
 696          * clear the interrupt.
 697          */
 698         if (stat & OMAP_I2C_STAT_RDR) {
 699                 /* Step 1: If RDR is set, clear it */
 700                 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
 701
 702                 /* Step 2: */
 703                 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
 704                                                 & OMAP_I2C_STAT_BB)) {
 705
 706                         /* Step 3: */
 707                         if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
 708                                                 & OMAP_I2C_STAT_RDR) {
 709                                 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
 710                                 dev_dbg(dev->dev, "RDR when bus is busy.\n");
 711                         }
 712
 713                 }
 714         }
 715 }
 716
 717 /* rev1 devices are apparently only on some 15xx */
 718 #ifdef CONFIG_ARCH_OMAP15XX
 719
 720 static irqreturn_t
 721 omap_i2c_omap1_isr(int this_irq, void *dev_id)
 722 {
 723         struct omap_i2c_dev *dev = dev_id;
 724         u16 iv, w;
 725
 726         if (pm_runtime_suspended(dev->dev))
 727                 return IRQ_NONE;
 728
 729         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 730         switch (iv) {
 731         case 0x00:      /* None */
 732                 break;
 733         case 0x01:      /* Arbitration lost */
 734                 dev_err(dev->dev, "Arbitration lost\n");
 735                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 736                 break;
 737         case 0x02:      /* No acknowledgement */
 738                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 739                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 740                 break;
 741         case 0x03:      /* Register access ready */
 742                 omap_i2c_complete_cmd(dev, 0);
 743                 break;
 744         case 0x04:      /* Receive data ready */
 745                 if (dev->buf_len) {
 746                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 747                         *dev->buf++ = w;
 748                         dev->buf_len--;
 749                         if (dev->buf_len) {
 750                                 *dev->buf++ = w >> 8;
 751                                 dev->buf_len--;
 752                         }
 753                 } else
 754                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 755                 break;
 756         case 0x05:      /* Transmit data ready */
 757                 if (dev->buf_len) {
 758                         w = *dev->buf++;
 759                         dev->buf_len--;
 760                         if (dev->buf_len) {
 761                                 w |= *dev->buf++ << 8;
 762                                 dev->buf_len--;
 763                         }
 764                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 765                 } else
 766                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 767                 break;
 768         default:
 769                 return IRQ_NONE;
 770         }
 771
 772         return IRQ_HANDLED;
 773 }
 774 #else
 775 #define omap_i2c_omap1_isr              NULL
 776 #endif
 777
 778 /*
 779  * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
 780  * data to DATA_REG. Otherwise some data bytes can be lost while transferring
 781  * them from the memory to the I2C interface.
 782  */
 783 static int errata_omap3_i462(struct omap_i2c_dev *dev)
 784 {
 785         unsigned long timeout = 10000;
 786         u16 stat;
 787
 788         do {
 789                 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 790                 if (stat & OMAP_I2C_STAT_XUDF)
 791                         break;
 792
 793                 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
 794                         omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
 795                                                         OMAP_I2C_STAT_XDR));
 796                         if (stat & OMAP_I2C_STAT_NACK) {
 797                                 dev->cmd_err |= OMAP_I2C_STAT_NACK;
 798                                 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
 799                         }
 800
 801                         if (stat & OMAP_I2C_STAT_AL) {
 802                                 dev_err(dev->dev, "Arbitration lost\n");
 803                                 dev->cmd_err |= OMAP_I2C_STAT_AL;
 804                                 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
 805                         }
 806
 807                         return -EIO;
 808                 }
 809
 810                 cpu_relax();
 811         } while (--timeout);
 812
 813         if (!timeout) {
 814                 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
 815                 return 0;
 816         }
 817
 818         return 0;
 819 }
 820
 821 static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
 822                 bool is_rdr)
 823 {
 824         u16             w;
 825
 826         while (num_bytes--) {
 827                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 828                 *dev->buf++ = w;
 829                 dev->buf_len--;
 830
 831                 /*
 832                  * Data reg in 2430, omap3 and
 833                  * omap4 is 8 bit wide
 834                  */
 835                 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
 836                         *dev->buf++ = w >> 8;
 837                         dev->buf_len--;
 838                 }
 839         }
 840 }
 841
 842 static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
 843                 bool is_xdr)
 844 {
 845         u16             w;
 846
 847         while (num_bytes--) {
 848                 w = *dev->buf++;
 849                 dev->buf_len--;
 850
 851                 /*
 852                  * Data reg in 2430, omap3 and
 853                  * omap4 is 8 bit wide
 854                  */
 855                 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
 856                         w |= *dev->buf++ << 8;
 857                         dev->buf_len--;
 858                 }
 859
 860                 if (dev->errata & I2C_OMAP_ERRATA_I462) {
 861                         int ret;
 862
 863                         ret = errata_omap3_i462(dev);
 864                         if (ret < 0)
 865                                 return ret;
 866                 }
 867
 868                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 869         }
 870
 871         return 0;
 872 }
 873
 874 static irqreturn_t
 875 omap_i2c_isr(int irq, void *dev_id)
 876 {
 877         struct omap_i2c_dev *dev = dev_id;
 878         irqreturn_t ret = IRQ_HANDLED;
 879         u16 mask;
 880         u16 stat;
 881
 882         spin_lock(&dev->lock);
 883         mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 884         stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 885
 886         if (stat & mask)
 887                 ret = IRQ_WAKE_THREAD;
 888
 889         spin_unlock(&dev->lock);
 890
 891         return ret;
 892 }
 893
 894 static irqreturn_t
 895 omap_i2c_isr_thread(int this_irq, void *dev_id)
 896 {
 897         struct omap_i2c_dev *dev = dev_id;
 898         unsigned long flags;
 899         u16 bits;
 900         u16 stat;
 901         int err = 0, count = 0;
 902
 903         spin_lock_irqsave(&dev->lock, flags);
 904         do {
 905                 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 906                 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
 907                 stat &= bits;
 908
 909                 /* If we're in receiver mode, ignore XDR/XRDY */
 910                 if (dev->receiver)
 911                         stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
 912                 else
 913                         stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
 914
 915                 if (!stat) {
 916                         /* my work here is done */
 917                         goto out;
 918                 }
 919
 920                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 921                 if (count++ == 100) {
 922                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 923                         break;
 924                 }
 925
 926                 if (stat & OMAP_I2C_STAT_NACK) {
 927                         err |= OMAP_I2C_STAT_NACK;
 928                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
 929                         break;
 930                 }
 931
 932                 if (stat & OMAP_I2C_STAT_AL) {
 933                         dev_err(dev->dev, "Arbitration lost\n");
 934                         err |= OMAP_I2C_STAT_AL;
 935                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
 936                         break;
 937                 }
 938
 939                 /*
 940                  * ProDB0017052: Clear ARDY bit twice
 941                  */
 942                 if (stat & OMAP_I2C_STAT_ARDY)
 943                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ARDY);
 944
 945                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 946                                         OMAP_I2C_STAT_AL)) {
 947                         omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
 948                                                 OMAP_I2C_STAT_RDR |
 949                                                 OMAP_I2C_STAT_XRDY |
 950                                                 OMAP_I2C_STAT_XDR |
 951                                                 OMAP_I2C_STAT_ARDY));
 952                         break;
 953                 }
 954
 955                 if (stat & OMAP_I2C_STAT_RDR) {
 956                         u8 num_bytes = 1;
 957
 958                         if (dev->fifo_size)
 959                                 num_bytes = dev->buf_len;
 960
 961                         omap_i2c_receive_data(dev, num_bytes, true);
 962
 963                         if (dev->errata & I2C_OMAP_ERRATA_I207)
 964                                 i2c_omap_errata_i207(dev, stat);
 965
 966                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
 967                         continue;
 968                 }
 969
 970                 if (stat & OMAP_I2C_STAT_RRDY) {
 971                         u8 num_bytes = 1;
 972
 973                         if (dev->threshold)
 974                                 num_bytes = dev->threshold;
 975
 976                         omap_i2c_receive_data(dev, num_bytes, false);
 977                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
 978                         continue;
 979                 }
 980
 981                 if (stat & OMAP_I2C_STAT_XDR) {
 982                         u8 num_bytes = 1;
 983                         int ret;
 984
 985                         if (dev->fifo_size)
 986                                 num_bytes = dev->buf_len;
 987
 988                         ret = omap_i2c_transmit_data(dev, num_bytes, true);
 989                         if (ret < 0)
 990                                 break;
 991
 992                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
 993                         continue;
 994                 }
 995
 996                 if (stat & OMAP_I2C_STAT_XRDY) {
 997                         u8 num_bytes = 1;
 998                         int ret;
 999
1000                         if (dev->threshold)
1001                                 num_bytes = dev->threshold;
1002
1003                         ret = omap_i2c_transmit_data(dev, num_bytes, false);
1004                         if (ret < 0)
1005                                 break;
1006
1007                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
1008                         continue;
1009                 }
1010
1011                 if (stat & OMAP_I2C_STAT_ROVR) {
1012                         dev_err(dev->dev, "Receive overrun\n");
1013                         err |= OMAP_I2C_STAT_ROVR;
1014                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
1015                         break;
1016                 }
1017
1018                 if (stat & OMAP_I2C_STAT_XUDF) {
1019                         dev_err(dev->dev, "Transmit underflow\n");
1020                         err |= OMAP_I2C_STAT_XUDF;
1021                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
1022                         break;
1023                 }
1024         } while (stat);
1025
1026         omap_i2c_complete_cmd(dev, err);
1027
1028 out:
1029         spin_unlock_irqrestore(&dev->lock, flags);
1030
1031         return IRQ_HANDLED;
1032 }
1033
1034 static const struct i2c_algorithm omap_i2c_algo = {
1035         .master_xfer    = omap_i2c_xfer,
1036         .functionality  = omap_i2c_func,
1037 };
1038
1039 #ifdef CONFIG_OF
1040 static struct omap_i2c_bus_platform_data omap2420_pdata = {
1041         .rev = OMAP_I2C_IP_VERSION_1,
1042         .flags = OMAP_I2C_FLAG_NO_FIFO |
1043                         OMAP_I2C_FLAG_SIMPLE_CLOCK |
1044                         OMAP_I2C_FLAG_16BIT_DATA_REG |
1045                         OMAP_I2C_FLAG_BUS_SHIFT_2,
1046 };
1047
1048 static struct omap_i2c_bus_platform_data omap2430_pdata = {
1049         .rev = OMAP_I2C_IP_VERSION_1,
1050         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
1051                         OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1052 };
1053
1054 static struct omap_i2c_bus_platform_data omap3_pdata = {
1055         .rev = OMAP_I2C_IP_VERSION_1,
1056         .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
1057 };
1058
1059 static struct omap_i2c_bus_platform_data omap4_pdata = {
1060         .rev = OMAP_I2C_IP_VERSION_2,
1061 };
1062
1063 static const struct of_device_id omap_i2c_of_match[] = {
1064         {
1065                 .compatible = "ti,omap4-i2c",
1066                 .data = &omap4_pdata,
1067         },
1068         {
1069                 .compatible = "ti,omap3-i2c",
1070                 .data = &omap3_pdata,
1071         },
1072         {
1073                 .compatible = "ti,omap2430-i2c",
1074                 .data = &omap2430_pdata,
1075         },
1076         {
1077                 .compatible = "ti,omap2420-i2c",
1078                 .data = &omap2420_pdata,
1079         },
1080         { },
1081 };
1082 MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1083 #endif
1084
1085 #define OMAP_I2C_SCHEME(rev)            ((rev & 0xc000) >> 14)
1086
1087 #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1088 #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1089
1090 #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1091 #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1092 #define OMAP_I2C_SCHEME_0               0
1093 #define OMAP_I2C_SCHEME_1               1
1094
1095 static int
1096 omap_i2c_probe(struct platform_device *pdev)
1097 {
1098         struct omap_i2c_dev     *dev;
1099         struct i2c_adapter      *adap;
1100         struct resource         *mem;
1101         const struct omap_i2c_bus_platform_data *pdata =
1102                 dev_get_platdata(&pdev->dev);
1103         struct device_node      *node = pdev->dev.of_node;
1104         const struct of_device_id *match;
1105         int irq;
1106         int r;
1107         u32 rev;
1108         u16 minor, major;
1109
1110         irq = platform_get_irq(pdev, 0);
1111         if (irq < 0) {
1112                 dev_err(&pdev->dev, "no irq resource?\n");
1113                 return irq;
1114         }
1115
1116         dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1117         if (!dev) {
1118                 dev_err(&pdev->dev, "Menory allocation failed\n");
1119                 return -ENOMEM;
1120         }
1121
1122         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1123         dev->base = devm_ioremap_resource(&pdev->dev, mem);
1124         if (IS_ERR(dev->base))
1125                 return PTR_ERR(dev->base);
1126
1127         match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
1128         if (match) {
1129                 u32 freq = 100000; /* default to 100000 Hz */
1130
1131                 pdata = match->data;
1132                 dev->flags = pdata->flags;
1133
1134                 of_property_read_u32(node, "clock-frequency", &freq);
1135                 /* convert DT freq value in Hz into kHz for speed */
1136                 dev->speed = freq / 1000;
1137         } else if (pdata != NULL) {
1138                 dev->speed = pdata->clkrate;
1139                 dev->flags = pdata->flags;
1140                 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1141         }
1142
1143         dev->dev = &pdev->dev;
1144         dev->irq = irq;
1145
1146         spin_lock_init(&dev->lock);
1147
1148         platform_set_drvdata(pdev, dev);
1149         init_completion(&dev->cmd_complete);
1150
1151         dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1152
1153         pm_runtime_enable(dev->dev);
1154         pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
1155         pm_runtime_use_autosuspend(dev->dev);
1156
1157         r = pm_runtime_get_sync(dev->dev);
1158         if (IS_ERR_VALUE(r))
1159                 goto err_free_mem;
1160
1161         /*
1162          * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1163          * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1164          * Also since the omap_i2c_read_reg uses reg_map_ip_* a
1165          * readw_relaxed is done.
1166          */
1167         rev = readw_relaxed(dev->base + 0x04);
1168
1169         dev->scheme = OMAP_I2C_SCHEME(rev);
1170         switch (dev->scheme) {
1171         case OMAP_I2C_SCHEME_0:
1172                 dev->regs = (u8 *)reg_map_ip_v1;
1173                 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
1174                 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1175                 major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1176                 break;
1177         case OMAP_I2C_SCHEME_1:
1178                 /* FALLTHROUGH */
1179         default:
1180                 dev->regs = (u8 *)reg_map_ip_v2;
1181                 rev = (rev << 16) |
1182                         omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
1183                 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1184                 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1185                 dev->rev = rev;
1186         }
1187
1188         dev->errata = 0;
1189
1190         if (dev->rev >= OMAP_I2C_REV_ON_2430 &&
1191                         dev->rev < OMAP_I2C_REV_ON_4430_PLUS)
1192                 dev->errata |= I2C_OMAP_ERRATA_I207;
1193
1194         if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
1195                 dev->errata |= I2C_OMAP_ERRATA_I462;
1196
1197         if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1198                 u16 s;
1199
1200                 /* Set up the fifo size - Get total size */
1201                 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1202                 dev->fifo_size = 0x8 << s;
1203
1204                 /*
1205                  * Set up notification threshold as half the total available
1206                  * size. This is to ensure that we can handle the status on int
1207                  * call back latencies.
1208                  */
1209
1210                 dev->fifo_size = (dev->fifo_size / 2);
1211
1212                 if (dev->rev < OMAP_I2C_REV_ON_3630)
1213                         dev->b_hw = 1; /* Enable hardware fixes */
1214
1215                 /* calculate wakeup latency constraint for MPU */
1216                 if (dev->set_mpu_wkup_lat != NULL)
1217                         dev->latency = (1000000 * dev->fifo_size) /
1218                                        (1000 * dev->speed / 8);
1219         }
1220
1221         /* reset ASAP, clearing any IRQs */
1222         omap_i2c_init(dev);
1223
1224         if (dev->rev < OMAP_I2C_OMAP1_REV_2)
1225                 r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
1226                                 IRQF_NO_SUSPEND, pdev->name, dev);
1227         else
1228                 r = devm_request_threaded_irq(&pdev->dev, dev->irq,
1229                                 omap_i2c_isr, omap_i2c_isr_thread,
1230                                 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1231                                 pdev->name, dev);
1232
1233         if (r) {
1234                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1235                 goto err_unuse_clocks;
1236         }
1237
1238         adap = &dev->adapter;
1239         i2c_set_adapdata(adap, dev);
1240         adap->owner = THIS_MODULE;
1241         adap->class = I2C_CLASS_HWMON;
1242         strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1243         adap->algo = &omap_i2c_algo;
1244         adap->dev.parent = &pdev->dev;
1245         adap->dev.of_node = pdev->dev.of_node;
1246
1247         /* i2c device drivers may be active on return from add_adapter() */
1248         adap->nr = pdev->id;
1249         r = i2c_add_numbered_adapter(adap);
1250         if (r) {
1251                 dev_err(dev->dev, "failure adding adapter\n");
1252                 goto err_unuse_clocks;
1253         }
1254
1255         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1256                  major, minor, dev->speed);
1257
1258         pm_runtime_mark_last_busy(dev->dev);
1259         pm_runtime_put_autosuspend(dev->dev);
1260
1261         return 0;
1262
1263 err_unuse_clocks:
1264         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1265         pm_runtime_put(dev->dev);
1266         pm_runtime_disable(&pdev->dev);
1267 err_free_mem:
1268
1269         return r;
1270 }
1271
1272 static int omap_i2c_remove(struct platform_device *pdev)
1273 {
1274         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
1275         int ret;
1276
1277         i2c_del_adapter(&dev->adapter);
1278         ret = pm_runtime_get_sync(&pdev->dev);
1279         if (IS_ERR_VALUE(ret))
1280                 return ret;
1281
1282         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1283         pm_runtime_put(&pdev->dev);
1284         pm_runtime_disable(&pdev->dev);
1285         return 0;
1286 }
1287
1288 #ifdef CONFIG_PM
1289 #ifdef CONFIG_PM_RUNTIME
1290 static int omap_i2c_runtime_suspend(struct device *dev)
1291 {
1292         struct platform_device *pdev = to_platform_device(dev);
1293         struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1294
1295         _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
1296
1297         if (_dev->scheme == OMAP_I2C_SCHEME_0)
1298                 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
1299         else
1300                 omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1301                                    OMAP_I2C_IP_V2_INTERRUPTS_MASK);
1302
1303         if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1304                 omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
1305         } else {
1306                 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
1307
1308                 /* Flush posted write */
1309                 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1310         }
1311
1312         return 0;
1313 }
1314
1315 static int omap_i2c_runtime_resume(struct device *dev)
1316 {
1317         struct platform_device *pdev = to_platform_device(dev);
1318         struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1319
1320         if (!_dev->regs)
1321                 return 0;
1322
1323         __omap_i2c_init(_dev);
1324
1325         return 0;
1326 }
1327 #endif /* CONFIG_PM_RUNTIME */
1328
1329 static struct dev_pm_ops omap_i2c_pm_ops = {
1330         SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1331                            omap_i2c_runtime_resume, NULL)
1332 };
1333 #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1334 #else
1335 #define OMAP_I2C_PM_OPS NULL
1336 #endif /* CONFIG_PM */
1337
1338 static struct platform_driver omap_i2c_driver = {
1339         .probe          = omap_i2c_probe,
1340         .remove         = omap_i2c_remove,
1341         .driver         = {
1342                 .name   = "omap_i2c",
1343                 .owner  = THIS_MODULE,
1344                 .pm     = OMAP_I2C_PM_OPS,
1345                 .of_match_table = of_match_ptr(omap_i2c_of_match),
1346         },
1347 };
1348
1349 /* I2C may be needed to bring up other drivers */
1350 static int __init
1351 omap_i2c_init_driver(void)
1352 {
1353         return platform_driver_register(&omap_i2c_driver);
1354 }
1355 subsys_initcall(omap_i2c_init_driver);
1356
1357 static void __exit omap_i2c_exit_driver(void)
1358 {
1359         platform_driver_unregister(&omap_i2c_driver);
1360 }
1361 module_exit(omap_i2c_exit_driver);
1362
1363 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1364 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1365 MODULE_LICENSE("GPL");
1366 MODULE_ALIAS("platform:omap_i2c");