drivers/i2c/busses/i2c-npcm7xx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Nuvoton NPCM7xx I2C Controller driver
   4  *
   5  * Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com
   6  */
   7 #include <linux/bitfield.h>
   8 #include <linux/clk.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/errno.h>
  11 #include <linux/i2c.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/irq.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/kernel.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22
  23 enum i2c_mode {
  24         I2C_MASTER,
  25         I2C_SLAVE,
  26 };
  27
  28 /*
  29  * External I2C Interface driver xfer indication values, which indicate status
  30  * of the bus.
  31  */
  32 enum i2c_state_ind {
  33         I2C_NO_STATUS_IND = 0,
  34         I2C_SLAVE_RCV_IND,
  35         I2C_SLAVE_XMIT_IND,
  36         I2C_SLAVE_XMIT_MISSING_DATA_IND,
  37         I2C_SLAVE_RESTART_IND,
  38         I2C_SLAVE_DONE_IND,
  39         I2C_MASTER_DONE_IND,
  40         I2C_NACK_IND,
  41         I2C_BUS_ERR_IND,
  42         I2C_WAKE_UP_IND,
  43         I2C_BLOCK_BYTES_ERR_IND,
  44         I2C_SLAVE_RCV_MISSING_DATA_IND,
  45 };
  46
  47 /*
  48  * Operation type values (used to define the operation currently running)
  49  * module is interrupt driven, on each interrupt the current operation is
  50  * checked to see if the module is currently reading or writing.
  51  */
  52 enum i2c_oper {
  53         I2C_NO_OPER = 0,
  54         I2C_WRITE_OPER,
  55         I2C_READ_OPER,
  56 };
  57
  58 /* I2C Bank (module had 2 banks of registers) */
  59 enum i2c_bank {
  60         I2C_BANK_0 = 0,
  61         I2C_BANK_1,
  62 };
  63
  64 /* Internal I2C states values (for the I2C module state machine). */
  65 enum i2c_state {
  66         I2C_DISABLE = 0,
  67         I2C_IDLE,
  68         I2C_MASTER_START,
  69         I2C_SLAVE_MATCH,
  70         I2C_OPER_STARTED,
  71         I2C_STOP_PENDING,
  72 };
  73
  74 #if IS_ENABLED(CONFIG_I2C_SLAVE)
  75 /* Module supports setting multiple own slave addresses */
  76 enum i2c_addr {
  77         I2C_SLAVE_ADDR1 = 0,
  78         I2C_SLAVE_ADDR2,
  79         I2C_SLAVE_ADDR3,
  80         I2C_SLAVE_ADDR4,
  81         I2C_SLAVE_ADDR5,
  82         I2C_SLAVE_ADDR6,
  83         I2C_SLAVE_ADDR7,
  84         I2C_SLAVE_ADDR8,
  85         I2C_SLAVE_ADDR9,
  86         I2C_SLAVE_ADDR10,
  87         I2C_GC_ADDR,
  88         I2C_ARP_ADDR,
  89 };
  90 #endif
  91
  92 /* init register and default value required to enable module */
  93 #define NPCM_I2CSEGCTL                  0xE4
  94
  95 /* Common regs */
  96 #define NPCM_I2CSDA                     0x00
  97 #define NPCM_I2CST                      0x02
  98 #define NPCM_I2CCST                     0x04
  99 #define NPCM_I2CCTL1                    0x06
 100 #define NPCM_I2CADDR1                   0x08
 101 #define NPCM_I2CCTL2                    0x0A
 102 #define NPCM_I2CADDR2                   0x0C
 103 #define NPCM_I2CCTL3                    0x0E
 104 #define NPCM_I2CCST2                    0x18
 105 #define NPCM_I2CCST3                    0x19
 106 #define I2C_VER                         0x1F
 107
 108 /* BANK 0 regs */
 109 #define NPCM_I2CADDR3                   0x10
 110 #define NPCM_I2CADDR7                   0x11
 111 #define NPCM_I2CADDR4                   0x12
 112 #define NPCM_I2CADDR8                   0x13
 113 #define NPCM_I2CADDR5                   0x14
 114 #define NPCM_I2CADDR9                   0x15
 115 #define NPCM_I2CADDR6                   0x16
 116 #define NPCM_I2CADDR10                  0x17
 117 #define NPCM_I2CCTL4                    0x1A
 118 #define NPCM_I2CCTL5                    0x1B
 119 #define NPCM_I2CSCLLT                   0x1C /* SCL Low Time */
 120 #define NPCM_I2CFIF_CTL                 0x1D /* FIFO Control */
 121 #define NPCM_I2CSCLHT                   0x1E /* SCL High Time */
 122
 123 /* BANK 1 regs */
 124 #define NPCM_I2CFIF_CTS                 0x10 /* Both FIFOs Control and Status */
 125 #define NPCM_I2CTXF_CTL                 0x12 /* Tx-FIFO Control */
 126 #define NPCM_I2CT_OUT                   0x14 /* Bus T.O. */
 127 #define NPCM_I2CPEC                     0x16 /* PEC Data */
 128 #define NPCM_I2CTXF_STS                 0x1A /* Tx-FIFO Status */
 129 #define NPCM_I2CRXF_STS                 0x1C /* Rx-FIFO Status */
 130 #define NPCM_I2CRXF_CTL                 0x1E /* Rx-FIFO Control */
 131
 132 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 133 /*
 134  * npcm_i2caddr array:
 135  * The module supports having multiple own slave addresses.
 136  * Since the addr regs are sprinkled all over the address space,
 137  * use this array to get the address or each register.
 138  */
 139 #define I2C_NUM_OWN_ADDR 2
 140 #define I2C_NUM_OWN_ADDR_SUPPORTED 2
 141
 142 static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = {
 143         NPCM_I2CADDR1, NPCM_I2CADDR2,
 144 };
 145 #endif
 146
 147 /* NPCM_I2CST reg fields */
 148 #define NPCM_I2CST_XMIT                 BIT(0)  /* Transmit mode */
 149 #define NPCM_I2CST_MASTER               BIT(1)  /* Master mode */
 150 #define NPCM_I2CST_NMATCH               BIT(2)  /* New match */
 151 #define NPCM_I2CST_STASTR               BIT(3)  /* Stall after start */
 152 #define NPCM_I2CST_NEGACK               BIT(4)  /* Negative ACK */
 153 #define NPCM_I2CST_BER                  BIT(5)  /* Bus error */
 154 #define NPCM_I2CST_SDAST                BIT(6)  /* SDA status */
 155 #define NPCM_I2CST_SLVSTP               BIT(7)  /* Slave stop */
 156
 157 /* NPCM_I2CCST reg fields */
 158 #define NPCM_I2CCST_BUSY                BIT(0)  /* Busy */
 159 #define NPCM_I2CCST_BB                  BIT(1)  /* Bus busy */
 160 #define NPCM_I2CCST_MATCH               BIT(2)  /* Address match */
 161 #define NPCM_I2CCST_GCMATCH             BIT(3)  /* Global call match */
 162 #define NPCM_I2CCST_TSDA                BIT(4)  /* Test SDA line */
 163 #define NPCM_I2CCST_TGSCL               BIT(5)  /* Toggle SCL line */
 164 #define NPCM_I2CCST_MATCHAF             BIT(6)  /* Match address field */
 165 #define NPCM_I2CCST_ARPMATCH            BIT(7)  /* ARP address match */
 166
 167 /* NPCM_I2CCTL1 reg fields */
 168 #define NPCM_I2CCTL1_START              BIT(0)  /* Generate start condition */
 169 #define NPCM_I2CCTL1_STOP               BIT(1)  /* Generate stop condition */
 170 #define NPCM_I2CCTL1_INTEN              BIT(2)  /* Interrupt enable */
 171 #define NPCM_I2CCTL1_EOBINTE            BIT(3)
 172 #define NPCM_I2CCTL1_ACK                BIT(4)
 173 #define NPCM_I2CCTL1_GCMEN              BIT(5)  /* Global call match enable */
 174 #define NPCM_I2CCTL1_NMINTE             BIT(6)  /* New match interrupt enable */
 175 #define NPCM_I2CCTL1_STASTRE            BIT(7)  /* Stall after start enable */
 176
 177 /* RW1S fields (inside a RW reg): */
 178 #define NPCM_I2CCTL1_RWS   \
 179         (NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK)
 180
 181 /* npcm_i2caddr reg fields */
 182 #define NPCM_I2CADDR_A                  GENMASK(6, 0)   /* Address */
 183 #define NPCM_I2CADDR_SAEN               BIT(7)          /* Slave address enable */
 184
 185 /* NPCM_I2CCTL2 reg fields */
 186 #define I2CCTL2_ENABLE                  BIT(0)          /* Module enable */
 187 #define I2CCTL2_SCLFRQ6_0               GENMASK(7, 1)   /* Bits 0:6 of frequency divisor */
 188
 189 /* NPCM_I2CCTL3 reg fields */
 190 #define I2CCTL3_SCLFRQ8_7               GENMASK(1, 0)   /* Bits 7:8 of frequency divisor */
 191 #define I2CCTL3_ARPMEN                  BIT(2)  /* ARP match enable */
 192 #define I2CCTL3_IDL_START               BIT(3)
 193 #define I2CCTL3_400K_MODE               BIT(4)
 194 #define I2CCTL3_BNK_SEL                 BIT(5)
 195 #define I2CCTL3_SDA_LVL                 BIT(6)
 196 #define I2CCTL3_SCL_LVL                 BIT(7)
 197
 198 /* NPCM_I2CCST2 reg fields */
 199 #define NPCM_I2CCST2_MATCHA1F           BIT(0)
 200 #define NPCM_I2CCST2_MATCHA2F           BIT(1)
 201 #define NPCM_I2CCST2_MATCHA3F           BIT(2)
 202 #define NPCM_I2CCST2_MATCHA4F           BIT(3)
 203 #define NPCM_I2CCST2_MATCHA5F           BIT(4)
 204 #define NPCM_I2CCST2_MATCHA6F           BIT(5)
 205 #define NPCM_I2CCST2_MATCHA7F           BIT(5)
 206 #define NPCM_I2CCST2_INTSTS             BIT(7)
 207
 208 /* NPCM_I2CCST3 reg fields */
 209 #define NPCM_I2CCST3_MATCHA8F           BIT(0)
 210 #define NPCM_I2CCST3_MATCHA9F           BIT(1)
 211 #define NPCM_I2CCST3_MATCHA10F          BIT(2)
 212 #define NPCM_I2CCST3_EO_BUSY            BIT(7)
 213
 214 /* NPCM_I2CCTL4 reg fields */
 215 #define I2CCTL4_HLDT                    GENMASK(5, 0)
 216 #define I2CCTL4_LVL_WE                  BIT(7)
 217
 218 /* NPCM_I2CCTL5 reg fields */
 219 #define I2CCTL5_DBNCT                   GENMASK(3, 0)
 220
 221 /* NPCM_I2CFIF_CTS reg fields */
 222 #define NPCM_I2CFIF_CTS_RXF_TXE         BIT(1)
 223 #define NPCM_I2CFIF_CTS_RFTE_IE         BIT(3)
 224 #define NPCM_I2CFIF_CTS_CLR_FIFO        BIT(6)
 225 #define NPCM_I2CFIF_CTS_SLVRSTR         BIT(7)
 226
 227 /* NPCM_I2CTXF_CTL reg field */
 228 #define NPCM_I2CTXF_CTL_THR_TXIE        BIT(6)
 229
 230 /* NPCM_I2CT_OUT reg fields */
 231 #define NPCM_I2CT_OUT_TO_CKDIV          GENMASK(5, 0)
 232 #define NPCM_I2CT_OUT_T_OUTIE           BIT(6)
 233 #define NPCM_I2CT_OUT_T_OUTST           BIT(7)
 234
 235 /* NPCM_I2CTXF_STS reg fields */
 236 #define NPCM_I2CTXF_STS_TX_THST         BIT(6)
 237
 238 /* NPCM_I2CRXF_STS reg fields */
 239 #define NPCM_I2CRXF_STS_RX_THST         BIT(6)
 240
 241 /* NPCM_I2CFIF_CTL reg fields */
 242 #define NPCM_I2CFIF_CTL_FIFO_EN         BIT(4)
 243
 244 /* NPCM_I2CRXF_CTL reg fields */
 245 #define NPCM_I2CRXF_CTL_THR_RXIE        BIT(6)
 246
 247 #define MAX_I2C_HW_FIFO_SIZE            32
 248
 249 /* I2C_VER reg fields */
 250 #define I2C_VER_VERSION                 GENMASK(6, 0)
 251 #define I2C_VER_FIFO_EN                 BIT(7)
 252
 253 /* stall/stuck timeout in us */
 254 #define DEFAULT_STALL_COUNT             25
 255
 256 /* SCLFRQ field position */
 257 #define SCLFRQ_0_TO_6                   GENMASK(6, 0)
 258 #define SCLFRQ_7_TO_8                   GENMASK(8, 7)
 259
 260 /* supported clk settings. values in Hz. */
 261 #define I2C_FREQ_MIN_HZ                 10000
 262 #define I2C_FREQ_MAX_HZ                 I2C_MAX_FAST_MODE_PLUS_FREQ
 263
 264 struct npcm_i2c_data {
 265         u8 fifo_size;
 266         u32 segctl_init_val;
 267         u8 txf_sts_tx_bytes;
 268         u8 rxf_sts_rx_bytes;
 269         u8 rxf_ctl_last_pec;
 270 };
 271
 272 static const struct npcm_i2c_data npxm7xx_i2c_data = {
 273         .fifo_size = 16,
 274         .segctl_init_val = 0x0333F000,
 275         .txf_sts_tx_bytes = GENMASK(4, 0),
 276         .rxf_sts_rx_bytes = GENMASK(4, 0),
 277         .rxf_ctl_last_pec = BIT(5),
 278 };
 279
 280 static const struct npcm_i2c_data npxm8xx_i2c_data = {
 281         .fifo_size = 32,
 282         .segctl_init_val = 0x9333F000,
 283         .txf_sts_tx_bytes = GENMASK(5, 0),
 284         .rxf_sts_rx_bytes = GENMASK(5, 0),
 285         .rxf_ctl_last_pec = BIT(7),
 286 };
 287
 288 /* Status of one I2C module */
 289 struct npcm_i2c {
 290         struct i2c_adapter adap;
 291         struct device *dev;
 292         unsigned char __iomem *reg;
 293         const struct npcm_i2c_data *data;
 294         spinlock_t lock;   /* IRQ synchronization */
 295         struct completion cmd_complete;
 296         int cmd_err;
 297         struct i2c_msg *msgs;
 298         int msgs_num;
 299         int num;
 300         u32 apb_clk;
 301         struct i2c_bus_recovery_info rinfo;
 302         enum i2c_state state;
 303         enum i2c_oper operation;
 304         enum i2c_mode master_or_slave;
 305         enum i2c_state_ind stop_ind;
 306         u8 dest_addr;
 307         u8 *rd_buf;
 308         u16 rd_size;
 309         u16 rd_ind;
 310         u8 *wr_buf;
 311         u16 wr_size;
 312         u16 wr_ind;
 313         bool fifo_use;
 314         u16 PEC_mask; /* PEC bit mask per slave address */
 315         bool PEC_use;
 316         bool read_block_use;
 317         unsigned long int_time_stamp;
 318         unsigned long bus_freq; /* in Hz */
 319 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 320         u8 own_slave_addr;
 321         struct i2c_client *slave;
 322         int slv_rd_size;
 323         int slv_rd_ind;
 324         int slv_wr_size;
 325         int slv_wr_ind;
 326         u8 slv_rd_buf[MAX_I2C_HW_FIFO_SIZE];
 327         u8 slv_wr_buf[MAX_I2C_HW_FIFO_SIZE];
 328 #endif
 329         struct dentry *debugfs; /* debugfs device directory */
 330         u64 ber_cnt;
 331         u64 rec_succ_cnt;
 332         u64 rec_fail_cnt;
 333         u64 nack_cnt;
 334         u64 timeout_cnt;
 335         u64 tx_complete_cnt;
 336 };
 337
 338 static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
 339                                         enum i2c_bank bank)
 340 {
 341         u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
 342
 343         if (bank == I2C_BANK_0)
 344                 i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL;
 345         else
 346                 i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL;
 347         iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
 348 }
 349
 350 static void npcm_i2c_init_params(struct npcm_i2c *bus)
 351 {
 352         bus->stop_ind = I2C_NO_STATUS_IND;
 353         bus->rd_size = 0;
 354         bus->wr_size = 0;
 355         bus->rd_ind = 0;
 356         bus->wr_ind = 0;
 357         bus->read_block_use = false;
 358         bus->int_time_stamp = 0;
 359         bus->PEC_use = false;
 360         bus->PEC_mask = 0;
 361 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 362         if (bus->slave)
 363                 bus->master_or_slave = I2C_SLAVE;
 364 #endif
 365 }
 366
 367 static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
 368 {
 369         iowrite8(data, bus->reg + NPCM_I2CSDA);
 370 }
 371
 372 static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
 373 {
 374         return ioread8(bus->reg + NPCM_I2CSDA);
 375 }
 376
 377 static int npcm_i2c_get_SCL(struct i2c_adapter *_adap)
 378 {
 379         struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
 380
 381         return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
 382 }
 383
 384 static int npcm_i2c_get_SDA(struct i2c_adapter *_adap)
 385 {
 386         struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
 387
 388         return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
 389 }
 390
 391 static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
 392 {
 393         if (bus->operation == I2C_READ_OPER)
 394                 return bus->rd_ind;
 395         if (bus->operation == I2C_WRITE_OPER)
 396                 return bus->wr_ind;
 397         return 0;
 398 }
 399
 400 /* quick protocol (just address) */
 401 static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
 402 {
 403         return bus->wr_size == 0 && bus->rd_size == 0;
 404 }
 405
 406 static void npcm_i2c_disable(struct npcm_i2c *bus)
 407 {
 408         u8 i2cctl2;
 409
 410 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 411         int i;
 412
 413         /* Slave addresses removal */
 414         for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++)
 415                 iowrite8(0, bus->reg + npcm_i2caddr[i]);
 416
 417 #endif
 418         /* Disable module */
 419         i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
 420         i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE;
 421         iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
 422
 423         bus->state = I2C_DISABLE;
 424 }
 425
 426 static void npcm_i2c_enable(struct npcm_i2c *bus)
 427 {
 428         u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
 429
 430         i2cctl2 = i2cctl2 | I2CCTL2_ENABLE;
 431         iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
 432         bus->state = I2C_IDLE;
 433 }
 434
 435 /* enable\disable end of busy (EOB) interrupts */
 436 static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
 437 {
 438         u8 val;
 439
 440         /* Clear EO_BUSY pending bit: */
 441         val = ioread8(bus->reg + NPCM_I2CCST3);
 442         val = val | NPCM_I2CCST3_EO_BUSY;
 443         iowrite8(val, bus->reg + NPCM_I2CCST3);
 444
 445         val = ioread8(bus->reg + NPCM_I2CCTL1);
 446         val &= ~NPCM_I2CCTL1_RWS;
 447         if (enable)
 448                 val |= NPCM_I2CCTL1_EOBINTE;
 449         else
 450                 val &= ~NPCM_I2CCTL1_EOBINTE;
 451         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 452 }
 453
 454 static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
 455 {
 456         u8 tx_fifo_sts;
 457
 458         tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
 459         /* check if TX FIFO is not empty */
 460         if ((tx_fifo_sts & bus->data->txf_sts_tx_bytes) == 0)
 461                 return false;
 462
 463         /* check if TX FIFO status bit is set: */
 464         return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts);
 465 }
 466
 467 static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
 468 {
 469         u8 rx_fifo_sts;
 470
 471         rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
 472         /* check if RX FIFO is not empty: */
 473         if ((rx_fifo_sts & bus->data->rxf_sts_rx_bytes) == 0)
 474                 return false;
 475
 476         /* check if rx fifo full status is set: */
 477         return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts);
 478 }
 479
 480 static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
 481 {
 482         u8 val;
 483
 484         val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
 485         val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE;
 486         iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
 487 }
 488
 489 static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
 490 {
 491         u8 val;
 492
 493         val = ioread8(bus->reg + NPCM_I2CTXF_STS);
 494         val = val | NPCM_I2CTXF_STS_TX_THST;
 495         iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
 496 }
 497
 498 static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
 499 {
 500         u8 val;
 501
 502         val = ioread8(bus->reg + NPCM_I2CRXF_STS);
 503         val = val | NPCM_I2CRXF_STS_RX_THST;
 504         iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
 505 }
 506
 507 static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
 508 {
 509         u8 val;
 510
 511         val = ioread8(bus->reg + NPCM_I2CCTL1);
 512         val &= ~NPCM_I2CCTL1_RWS;
 513         if (enable)
 514                 val |= NPCM_I2CCTL1_INTEN;
 515         else
 516                 val &= ~NPCM_I2CCTL1_INTEN;
 517         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 518 }
 519
 520 static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
 521 {
 522         u8 val;
 523
 524         val = ioread8(bus->reg + NPCM_I2CCTL1);
 525         val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK);
 526         val |= NPCM_I2CCTL1_START;
 527         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 528 }
 529
 530 static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
 531 {
 532         u8 val;
 533
 534         /*
 535          * override HW issue: I2C may fail to supply stop condition in Master
 536          * Write operation.
 537          * Need to delay at least 5 us from the last int, before issueing a stop
 538          */
 539         udelay(10); /* function called from interrupt, can't sleep */
 540         val = ioread8(bus->reg + NPCM_I2CCTL1);
 541         val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK);
 542         val |= NPCM_I2CCTL1_STOP;
 543         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 544
 545         if (!bus->fifo_use)
 546                 return;
 547
 548         npcm_i2c_select_bank(bus, I2C_BANK_1);
 549
 550         if (bus->operation == I2C_READ_OPER)
 551                 npcm_i2c_clear_rx_fifo(bus);
 552         else
 553                 npcm_i2c_clear_tx_fifo(bus);
 554         npcm_i2c_clear_fifo_int(bus);
 555         iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
 556 }
 557
 558 static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
 559 {
 560         u8 val;
 561
 562         val = ioread8(bus->reg + NPCM_I2CCTL1);
 563         val &= ~NPCM_I2CCTL1_RWS;
 564         if (stall)
 565                 val |= NPCM_I2CCTL1_STASTRE;
 566         else
 567                 val &= ~NPCM_I2CCTL1_STASTRE;
 568         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 569 }
 570
 571 static inline void npcm_i2c_nack(struct npcm_i2c *bus)
 572 {
 573         u8 val;
 574
 575         val = ioread8(bus->reg + NPCM_I2CCTL1);
 576         val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START);
 577         val |= NPCM_I2CCTL1_ACK;
 578         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 579 }
 580
 581 static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
 582 {
 583         u8 val;
 584
 585         /* Clear NEGACK, STASTR and BER bits */
 586         val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR;
 587         iowrite8(val, bus->reg + NPCM_I2CST);
 588 }
 589
 590 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 591 static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
 592 {
 593         u8 i2cctl1;
 594
 595         /* enable interrupt on slave match: */
 596         i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
 597         i2cctl1 &= ~NPCM_I2CCTL1_RWS;
 598         if (enable)
 599                 i2cctl1 |= NPCM_I2CCTL1_NMINTE;
 600         else
 601                 i2cctl1 &= ~NPCM_I2CCTL1_NMINTE;
 602         iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
 603 }
 604
 605 static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
 606                                  u8 addr, bool enable)
 607 {
 608         u8 i2cctl1;
 609         u8 i2cctl3;
 610         u8 sa_reg;
 611
 612         sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable);
 613         if (addr_type == I2C_GC_ADDR) {
 614                 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
 615                 if (enable)
 616                         i2cctl1 |= NPCM_I2CCTL1_GCMEN;
 617                 else
 618                         i2cctl1 &= ~NPCM_I2CCTL1_GCMEN;
 619                 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
 620                 return 0;
 621         } else if (addr_type == I2C_ARP_ADDR) {
 622                 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
 623                 if (enable)
 624                         i2cctl3 |= I2CCTL3_ARPMEN;
 625                 else
 626                         i2cctl3 &= ~I2CCTL3_ARPMEN;
 627                 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
 628                 return 0;
 629         }
 630         if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
 631                 dev_err(bus->dev, "try to enable more than 2 SA not supported\n");
 632
 633         if (addr_type >= I2C_ARP_ADDR)
 634                 return -EFAULT;
 635
 636         /* Set and enable the address */
 637         iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
 638         npcm_i2c_slave_int_enable(bus, enable);
 639
 640         return 0;
 641 }
 642 #endif
 643
 644 static void npcm_i2c_reset(struct npcm_i2c *bus)
 645 {
 646         /*
 647          * Save I2CCTL1 relevant bits. It is being cleared when the module
 648          *  is disabled.
 649          */
 650         u8 i2cctl1;
 651 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 652         u8 addr;
 653 #endif
 654
 655         i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
 656
 657         npcm_i2c_disable(bus);
 658         npcm_i2c_enable(bus);
 659
 660         /* Restore NPCM_I2CCTL1 Status */
 661         i2cctl1 &= ~NPCM_I2CCTL1_RWS;
 662         iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
 663
 664         /* Clear BB (BUS BUSY) bit */
 665         iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
 666         iowrite8(0xFF, bus->reg + NPCM_I2CST);
 667
 668         /* Clear and disable EOB */
 669         npcm_i2c_eob_int(bus, false);
 670
 671         /* Clear all fifo bits: */
 672         iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
 673
 674 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 675         if (bus->slave) {
 676                 addr = bus->slave->addr;
 677                 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
 678         }
 679 #endif
 680
 681         /* Clear status bits for spurious interrupts */
 682         npcm_i2c_clear_master_status(bus);
 683
 684         bus->state = I2C_IDLE;
 685 }
 686
 687 static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
 688 {
 689         return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
 690 }
 691
 692 static void npcm_i2c_callback(struct npcm_i2c *bus,
 693                               enum i2c_state_ind op_status, u16 info)
 694 {
 695         struct i2c_msg *msgs;
 696         int msgs_num;
 697
 698         msgs = bus->msgs;
 699         msgs_num = bus->msgs_num;
 700         /*
 701          * check that transaction was not timed-out, and msgs still
 702          * holds a valid value.
 703          */
 704         if (!msgs)
 705                 return;
 706
 707         if (completion_done(&bus->cmd_complete))
 708                 return;
 709
 710         switch (op_status) {
 711         case I2C_MASTER_DONE_IND:
 712                 bus->cmd_err = bus->msgs_num;
 713                 if (bus->tx_complete_cnt < ULLONG_MAX)
 714                         bus->tx_complete_cnt++;
 715                 fallthrough;
 716         case I2C_BLOCK_BYTES_ERR_IND:
 717                 /* Master tx finished and all transmit bytes were sent */
 718                 if (bus->msgs) {
 719                         if (msgs[0].flags & I2C_M_RD)
 720                                 msgs[0].len = info;
 721                         else if (msgs_num == 2 &&
 722                                  msgs[1].flags & I2C_M_RD)
 723                                 msgs[1].len = info;
 724                 }
 725                 if (completion_done(&bus->cmd_complete) == false)
 726                         complete(&bus->cmd_complete);
 727         break;
 728
 729         case I2C_NACK_IND:
 730                 /* MASTER transmit got a NACK before tx all bytes */
 731                 bus->cmd_err = -ENXIO;
 732                 if (bus->master_or_slave == I2C_MASTER)
 733                         complete(&bus->cmd_complete);
 734
 735                 break;
 736         case I2C_BUS_ERR_IND:
 737                 /* Bus error */
 738                 bus->cmd_err = -EAGAIN;
 739                 if (bus->master_or_slave == I2C_MASTER)
 740                         complete(&bus->cmd_complete);
 741
 742                 break;
 743         case I2C_WAKE_UP_IND:
 744                 /* I2C wake up */
 745                 break;
 746         default:
 747                 break;
 748         }
 749
 750         bus->operation = I2C_NO_OPER;
 751 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 752         if (bus->slave)
 753                 bus->master_or_slave = I2C_SLAVE;
 754 #endif
 755 }
 756
 757 static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
 758 {
 759         if (bus->operation == I2C_WRITE_OPER)
 760                 return (bus->data->txf_sts_tx_bytes &
 761                         ioread8(bus->reg + NPCM_I2CTXF_STS));
 762         if (bus->operation == I2C_READ_OPER)
 763                 return (bus->data->rxf_sts_rx_bytes &
 764                         ioread8(bus->reg + NPCM_I2CRXF_STS));
 765         return 0;
 766 }
 767
 768 static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
 769 {
 770         u8 size_free_fifo;
 771
 772         /*
 773          * Fill the FIFO, while the FIFO is not full and there are more bytes
 774          * to write
 775          */
 776         size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
 777         while (max_bytes-- && size_free_fifo) {
 778                 if (bus->wr_ind < bus->wr_size)
 779                         npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
 780                 else
 781                         npcm_i2c_wr_byte(bus, 0xFF);
 782                 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
 783         }
 784 }
 785
 786 /*
 787  * npcm_i2c_set_fifo:
 788  * configure the FIFO before using it. If nread is -1 RX FIFO will not be
 789  * configured. same for nwrite
 790  */
 791 static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
 792 {
 793         u8 rxf_ctl = 0;
 794
 795         if (!bus->fifo_use)
 796                 return;
 797         npcm_i2c_select_bank(bus, I2C_BANK_1);
 798         npcm_i2c_clear_tx_fifo(bus);
 799         npcm_i2c_clear_rx_fifo(bus);
 800
 801         /* configure RX FIFO */
 802         if (nread > 0) {
 803                 rxf_ctl = min_t(int, nread, bus->data->fifo_size);
 804
 805                 /* set LAST bit. if LAST is set next FIFO packet is nacked */
 806                 if (nread <= bus->data->fifo_size)
 807                         rxf_ctl |= bus->data->rxf_ctl_last_pec;
 808
 809                 /*
 810                  * if we are about to read the first byte in blk rd mode,
 811                  * don't NACK it. If slave returns zero size HW can't NACK
 812                  * it immediately, it will read extra byte and then NACK.
 813                  */
 814                 if (bus->rd_ind == 0 && bus->read_block_use) {
 815                         /* set fifo to read one byte, no last: */
 816                         rxf_ctl = 1;
 817                 }
 818
 819                 /* set fifo size: */
 820                 iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
 821         }
 822
 823         /* configure TX FIFO */
 824         if (nwrite > 0) {
 825                 if (nwrite > bus->data->fifo_size)
 826                         /* data to send is more then FIFO size. */
 827                         iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CTXF_CTL);
 828                 else
 829                         iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
 830
 831                 npcm_i2c_clear_tx_fifo(bus);
 832         }
 833 }
 834
 835 static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
 836 {
 837         u8 data;
 838
 839         while (bytes_in_fifo--) {
 840                 data = npcm_i2c_rd_byte(bus);
 841                 if (bus->rd_ind < bus->rd_size)
 842                         bus->rd_buf[bus->rd_ind++] = data;
 843         }
 844 }
 845
 846 static void npcm_i2c_master_abort(struct npcm_i2c *bus)
 847 {
 848         /* Only current master is allowed to issue a stop condition */
 849         if (!npcm_i2c_is_master(bus))
 850                 return;
 851
 852         npcm_i2c_eob_int(bus, true);
 853         npcm_i2c_master_stop(bus);
 854         npcm_i2c_clear_master_status(bus);
 855 }
 856
 857 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 858 static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
 859 {
 860         u8 slave_add;
 861
 862         if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
 863                 dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n");
 864
 865         slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]);
 866
 867         return slave_add;
 868 }
 869
 870 static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
 871 {
 872         int i;
 873
 874         /* Set the enable bit */
 875         slave_add |= 0x80;
 876
 877         for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) {
 878                 if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
 879                         iowrite8(0, bus->reg + npcm_i2caddr[i]);
 880         }
 881
 882         return 0;
 883 }
 884
 885 static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
 886 {
 887         /*
 888          * Fill the FIFO, while the FIFO is not full and there are more bytes
 889          * to write
 890          */
 891         npcm_i2c_clear_fifo_int(bus);
 892         npcm_i2c_clear_tx_fifo(bus);
 893         iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
 894         while (max_bytes-- && bus->data->fifo_size != npcm_i2c_fifo_usage(bus)) {
 895                 if (bus->slv_wr_size <= 0)
 896                         break;
 897                 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
 898                 npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
 899                 bus->slv_wr_ind++;
 900                 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
 901                 bus->slv_wr_size--;
 902         }
 903 }
 904
 905 static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
 906 {
 907         u8 data;
 908
 909         if (!bus->slave)
 910                 return;
 911
 912         while (bytes_in_fifo--) {
 913                 data = npcm_i2c_rd_byte(bus);
 914
 915                 bus->slv_rd_ind = bus->slv_rd_ind & (bus->data->fifo_size - 1);
 916                 bus->slv_rd_buf[bus->slv_rd_ind] = data;
 917                 bus->slv_rd_ind++;
 918
 919                 /* 1st byte is length in block protocol: */
 920                 if (bus->slv_rd_ind == 1 && bus->read_block_use)
 921                         bus->slv_rd_size = data + bus->PEC_use + 1;
 922         }
 923 }
 924
 925 static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
 926 {
 927         int i;
 928         u8 value;
 929         int ind;
 930         int ret = bus->slv_wr_ind;
 931
 932         /* fill a cyclic buffer */
 933         for (i = 0; i < bus->data->fifo_size; i++) {
 934                 if (bus->slv_wr_size >= bus->data->fifo_size)
 935                         break;
 936                 if (bus->state == I2C_SLAVE_MATCH) {
 937                         i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
 938                         bus->state = I2C_OPER_STARTED;
 939                 } else {
 940                         i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
 941                 }
 942                 ind = (bus->slv_wr_ind + bus->slv_wr_size) & (bus->data->fifo_size - 1);
 943                 bus->slv_wr_buf[ind] = value;
 944                 bus->slv_wr_size++;
 945         }
 946         return bus->data->fifo_size - ret;
 947 }
 948
 949 static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
 950 {
 951         int i;
 952
 953         for (i = 0; i < bus->slv_rd_ind; i++)
 954                 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
 955                                 &bus->slv_rd_buf[i]);
 956         /*
 957          * once we send bytes up, need to reset the counter of the wr buf
 958          * got data from master (new offset in device), ignore wr fifo:
 959          */
 960         if (bus->slv_rd_ind) {
 961                 bus->slv_wr_size = 0;
 962                 bus->slv_wr_ind = 0;
 963         }
 964
 965         bus->slv_rd_ind = 0;
 966         bus->slv_rd_size = bus->adap.quirks->max_read_len;
 967
 968         npcm_i2c_clear_fifo_int(bus);
 969         npcm_i2c_clear_rx_fifo(bus);
 970 }
 971
 972 static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
 973                                    u8 *read_data)
 974 {
 975         bus->state = I2C_OPER_STARTED;
 976         bus->operation = I2C_READ_OPER;
 977         bus->slv_rd_size = nread;
 978         bus->slv_rd_ind = 0;
 979
 980         iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
 981         iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
 982         npcm_i2c_clear_tx_fifo(bus);
 983         npcm_i2c_clear_rx_fifo(bus);
 984 }
 985
 986 static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
 987                                 u8 *write_data)
 988 {
 989         if (nwrite == 0)
 990                 return;
 991
 992         bus->operation = I2C_WRITE_OPER;
 993
 994         /* get the next buffer */
 995         npcm_i2c_slave_get_wr_buf(bus);
 996         npcm_i2c_write_fifo_slave(bus, nwrite);
 997 }
 998
 999 /*
1000  * npcm_i2c_slave_wr_buf_sync:
1001  * currently slave IF only supports single byte operations.
1002  * in order to utilize the npcm HW FIFO, the driver will ask for 16 bytes
1003  * at a time, pack them in buffer, and then transmit them all together
1004  * to the FIFO and onward to the bus.
1005  * NACK on read will be once reached to bus->adap->quirks->max_read_len.
1006  * sending a NACK wherever the backend requests for it is not supported.
1007  * the next two functions allow reading to local buffer before writing it all
1008  * to the HW FIFO.
1009  */
1010 static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus)
1011 {
1012         int left_in_fifo;
1013
1014         left_in_fifo = bus->data->txf_sts_tx_bytes &
1015                         ioread8(bus->reg + NPCM_I2CTXF_STS);
1016
1017         /* fifo already full: */
1018         if (left_in_fifo >= bus->data->fifo_size ||
1019             bus->slv_wr_size >= bus->data->fifo_size)
1020                 return;
1021
1022         /* update the wr fifo index back to the untransmitted bytes: */
1023         bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo;
1024         bus->slv_wr_size = bus->slv_wr_size + left_in_fifo;
1025
1026         if (bus->slv_wr_ind < 0)
1027                 bus->slv_wr_ind += bus->data->fifo_size;
1028 }
1029
1030 static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus)
1031 {
1032         if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) {
1033                 /*
1034                  * Slave got an address match with direction bit 1 so it should
1035                  * transmit data. Write till the master will NACK
1036                  */
1037                 bus->operation = I2C_WRITE_OPER;
1038                 npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len,
1039                                     bus->slv_wr_buf);
1040         } else {
1041                 /*
1042                  * Slave got an address match with direction bit 0 so it should
1043                  * receive data.
1044                  * this module does not support saying no to bytes.
1045                  * it will always ACK.
1046                  */
1047                 bus->operation = I2C_READ_OPER;
1048                 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1049                 bus->stop_ind = I2C_SLAVE_RCV_IND;
1050                 npcm_i2c_slave_send_rd_buf(bus);
1051                 npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len,
1052                                        bus->slv_rd_buf);
1053         }
1054 }
1055
1056 static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus)
1057 {
1058         u8 val;
1059         irqreturn_t ret = IRQ_NONE;
1060         u8 i2cst = ioread8(bus->reg + NPCM_I2CST);
1061
1062         /* Slave: A NACK has occurred */
1063         if (NPCM_I2CST_NEGACK & i2cst) {
1064                 bus->stop_ind = I2C_NACK_IND;
1065                 npcm_i2c_slave_wr_buf_sync(bus);
1066                 if (bus->fifo_use)
1067                         /* clear the FIFO */
1068                         iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1069                                  bus->reg + NPCM_I2CFIF_CTS);
1070
1071                 /* In slave write, NACK is OK, otherwise it is a problem */
1072                 bus->stop_ind = I2C_NO_STATUS_IND;
1073                 bus->operation = I2C_NO_OPER;
1074                 bus->own_slave_addr = 0xFF;
1075
1076                 /*
1077                  * Slave has to wait for STOP to decide this is the end
1078                  * of the transaction. tx is not yet considered as done
1079                  */
1080                 iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST);
1081
1082                 ret = IRQ_HANDLED;
1083         }
1084
1085         /* Slave mode: a Bus Error (BER) has been identified */
1086         if (NPCM_I2CST_BER & i2cst) {
1087                 /*
1088                  * Check whether bus arbitration or Start or Stop during data
1089                  * xfer bus arbitration problem should not result in recovery
1090                  */
1091                 bus->stop_ind = I2C_BUS_ERR_IND;
1092
1093                 /* wait for bus busy before clear fifo */
1094                 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1095
1096                 bus->state = I2C_IDLE;
1097
1098                 /*
1099                  * in BER case we might get 2 interrupts: one for slave one for
1100                  * master ( for a channel which is master\slave switching)
1101                  */
1102                 if (completion_done(&bus->cmd_complete) == false) {
1103                         bus->cmd_err = -EIO;
1104                         complete(&bus->cmd_complete);
1105                 }
1106                 bus->own_slave_addr = 0xFF;
1107                 iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST);
1108                 ret = IRQ_HANDLED;
1109         }
1110
1111         /* A Slave Stop Condition has been identified */
1112         if (NPCM_I2CST_SLVSTP & i2cst) {
1113                 u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus);
1114
1115                 bus->stop_ind = I2C_SLAVE_DONE_IND;
1116
1117                 if (bus->operation == I2C_READ_OPER)
1118                         npcm_i2c_read_fifo_slave(bus, bytes_in_fifo);
1119
1120                 /* if the buffer is empty nothing will be sent */
1121                 npcm_i2c_slave_send_rd_buf(bus);
1122
1123                 /* Slave done transmitting or receiving */
1124                 bus->stop_ind = I2C_NO_STATUS_IND;
1125
1126                 /*
1127                  * Note, just because we got here, it doesn't mean we through
1128                  * away the wr buffer.
1129                  * we keep it until the next received offset.
1130                  */
1131                 bus->operation = I2C_NO_OPER;
1132                 bus->own_slave_addr = 0xFF;
1133                 i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0);
1134                 iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST);
1135                 if (bus->fifo_use) {
1136                         npcm_i2c_clear_fifo_int(bus);
1137                         npcm_i2c_clear_rx_fifo(bus);
1138                         npcm_i2c_clear_tx_fifo(bus);
1139
1140                         iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1141                                  bus->reg + NPCM_I2CFIF_CTS);
1142                 }
1143                 bus->state = I2C_IDLE;
1144                 ret = IRQ_HANDLED;
1145         }
1146
1147         /* restart condition occurred and Rx-FIFO was not empty */
1148         if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR,
1149                                        ioread8(bus->reg + NPCM_I2CFIF_CTS))) {
1150                 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1151                 bus->master_or_slave = I2C_SLAVE;
1152                 if (bus->operation == I2C_READ_OPER)
1153                         npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1154                 bus->operation = I2C_WRITE_OPER;
1155                 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1156                 val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR |
1157                       NPCM_I2CFIF_CTS_RXF_TXE;
1158                 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
1159                 npcm_i2c_slave_rd_wr(bus);
1160                 ret = IRQ_HANDLED;
1161         }
1162
1163         /* A Slave Address Match has been identified */
1164         if (NPCM_I2CST_NMATCH & i2cst) {
1165                 u8 info = 0;
1166
1167                 /* Address match automatically implies slave mode */
1168                 bus->master_or_slave = I2C_SLAVE;
1169                 npcm_i2c_clear_fifo_int(bus);
1170                 npcm_i2c_clear_rx_fifo(bus);
1171                 npcm_i2c_clear_tx_fifo(bus);
1172                 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1173                 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
1174                 if (NPCM_I2CST_XMIT & i2cst) {
1175                         bus->operation = I2C_WRITE_OPER;
1176                 } else {
1177                         i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED,
1178                                         &info);
1179                         bus->operation = I2C_READ_OPER;
1180                 }
1181                 if (bus->own_slave_addr == 0xFF) {
1182                         /* Check which type of address match */
1183                         val = ioread8(bus->reg + NPCM_I2CCST);
1184                         if (NPCM_I2CCST_MATCH & val) {
1185                                 u16 addr;
1186                                 enum i2c_addr eaddr;
1187                                 u8 i2ccst2;
1188                                 u8 i2ccst3;
1189
1190                                 i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3);
1191                                 i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2);
1192
1193                                 /*
1194                                  * the i2c module can response to 10 own SA.
1195                                  * check which one was addressed by the master.
1196                                  * respond to the first one.
1197                                  */
1198                                 addr = ((i2ccst3 & 0x07) << 7) |
1199                                         (i2ccst2 & 0x7F);
1200                                 info = ffs(addr);
1201                                 eaddr = (enum i2c_addr)info;
1202                                 addr = npcm_i2c_get_slave_addr(bus, eaddr);
1203                                 addr &= 0x7F;
1204                                 bus->own_slave_addr = addr;
1205                                 if (bus->PEC_mask & BIT(info))
1206                                         bus->PEC_use = true;
1207                                 else
1208                                         bus->PEC_use = false;
1209                         } else {
1210                                 if (NPCM_I2CCST_GCMATCH & val)
1211                                         bus->own_slave_addr = 0;
1212                                 if (NPCM_I2CCST_ARPMATCH & val)
1213                                         bus->own_slave_addr = 0x61;
1214                         }
1215                 } else {
1216                         /*
1217                          *  Slave match can happen in two options:
1218                          *  1. Start, SA, read (slave read without further ado)
1219                          *  2. Start, SA, read, data, restart, SA, read,  ...
1220                          *     (slave read in fragmented mode)
1221                          *  3. Start, SA, write, data, restart, SA, read, ..
1222                          *     (regular write-read mode)
1223                          */
1224                         if ((bus->state == I2C_OPER_STARTED &&
1225                              bus->operation == I2C_READ_OPER &&
1226                              bus->stop_ind == I2C_SLAVE_XMIT_IND) ||
1227                              bus->stop_ind == I2C_SLAVE_RCV_IND) {
1228                                 /* slave tx after slave rx w/o STOP */
1229                                 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1230                         }
1231                 }
1232
1233                 if (NPCM_I2CST_XMIT & i2cst)
1234                         bus->stop_ind = I2C_SLAVE_XMIT_IND;
1235                 else
1236                         bus->stop_ind = I2C_SLAVE_RCV_IND;
1237                 bus->state = I2C_SLAVE_MATCH;
1238                 npcm_i2c_slave_rd_wr(bus);
1239                 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1240                 ret = IRQ_HANDLED;
1241         }
1242
1243         /* Slave SDA status is set - tx or rx */
1244         if ((NPCM_I2CST_SDAST & i2cst) ||
1245             (bus->fifo_use &&
1246             (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1247                 npcm_i2c_slave_rd_wr(bus);
1248                 iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST);
1249                 ret = IRQ_HANDLED;
1250         } /* SDAST */
1251
1252         /*
1253          * If irq is not one of the above, make sure EOB is disabled and all
1254          * status bits are cleared.
1255          */
1256         if (ret == IRQ_NONE) {
1257                 npcm_i2c_eob_int(bus, false);
1258                 npcm_i2c_clear_master_status(bus);
1259         }
1260
1261         return IRQ_HANDLED;
1262 }
1263
1264 static int npcm_i2c_reg_slave(struct i2c_client *client)
1265 {
1266         unsigned long lock_flags;
1267         struct npcm_i2c *bus = i2c_get_adapdata(client->adapter);
1268
1269         bus->slave = client;
1270
1271         if (!bus->slave)
1272                 return -EINVAL;
1273
1274         if (client->flags & I2C_CLIENT_TEN)
1275                 return -EAFNOSUPPORT;
1276
1277         spin_lock_irqsave(&bus->lock, lock_flags);
1278
1279         npcm_i2c_init_params(bus);
1280         bus->slv_rd_size = 0;
1281         bus->slv_wr_size = 0;
1282         bus->slv_rd_ind = 0;
1283         bus->slv_wr_ind = 0;
1284         if (client->flags & I2C_CLIENT_PEC)
1285                 bus->PEC_use = true;
1286
1287         dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num,
1288                  client->addr, bus->PEC_use);
1289
1290         npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true);
1291         npcm_i2c_clear_fifo_int(bus);
1292         npcm_i2c_clear_rx_fifo(bus);
1293         npcm_i2c_clear_tx_fifo(bus);
1294         npcm_i2c_slave_int_enable(bus, true);
1295
1296         spin_unlock_irqrestore(&bus->lock, lock_flags);
1297         return 0;
1298 }
1299
1300 static int npcm_i2c_unreg_slave(struct i2c_client *client)
1301 {
1302         struct npcm_i2c *bus = client->adapter->algo_data;
1303         unsigned long lock_flags;
1304
1305         spin_lock_irqsave(&bus->lock, lock_flags);
1306         if (!bus->slave) {
1307                 spin_unlock_irqrestore(&bus->lock, lock_flags);
1308                 return -EINVAL;
1309         }
1310         npcm_i2c_slave_int_enable(bus, false);
1311         npcm_i2c_remove_slave_addr(bus, client->addr);
1312         bus->slave = NULL;
1313         spin_unlock_irqrestore(&bus->lock, lock_flags);
1314         return 0;
1315 }
1316 #endif /* CONFIG_I2C_SLAVE */
1317
1318 static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
1319 {
1320         int rcount;
1321         int fifo_bytes;
1322         enum i2c_state_ind ind = I2C_MASTER_DONE_IND;
1323
1324         fifo_bytes = npcm_i2c_fifo_usage(bus);
1325         rcount = bus->rd_size - bus->rd_ind;
1326
1327         /*
1328          * In order not to change the RX_TRH during transaction (we found that
1329          * this might be problematic if it takes too much time to read the FIFO)
1330          * we read the data in the following way. If the number of bytes to
1331          * read == FIFO Size + C (where C < FIFO Size)then first read C bytes
1332          * and in the next int we read rest of the data.
1333          */
1334         if (rcount < (2 * bus->data->fifo_size) && rcount > bus->data->fifo_size)
1335                 fifo_bytes = rcount - bus->data->fifo_size;
1336
1337         if (rcount <= fifo_bytes) {
1338                 /* last bytes are about to be read - end of tx */
1339                 bus->state = I2C_STOP_PENDING;
1340                 bus->stop_ind = ind;
1341                 npcm_i2c_eob_int(bus, true);
1342                 /* Stop should be set before reading last byte. */
1343                 npcm_i2c_master_stop(bus);
1344                 npcm_i2c_read_fifo(bus, fifo_bytes);
1345         } else {
1346                 npcm_i2c_read_fifo(bus, fifo_bytes);
1347                 rcount = bus->rd_size - bus->rd_ind;
1348                 npcm_i2c_set_fifo(bus, rcount, -1);
1349         }
1350 }
1351
1352 static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus)
1353 {
1354         u16 wcount;
1355
1356         if (bus->fifo_use)
1357                 npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */
1358
1359         /* Master write operation - last byte handling */
1360         if (bus->wr_ind == bus->wr_size) {
1361                 if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0)
1362                         /*
1363                          * No more bytes to send (to add to the FIFO),
1364                          * however the FIFO is not empty yet. It is
1365                          * still in the middle of tx. Currently there's nothing
1366                          * to do except for waiting to the end of the tx
1367                          * We will get an int when the FIFO will get empty.
1368                          */
1369                         return;
1370
1371                 if (bus->rd_size == 0) {
1372                         /* all bytes have been written, in wr only operation */
1373                         npcm_i2c_eob_int(bus, true);
1374                         bus->state = I2C_STOP_PENDING;
1375                         bus->stop_ind = I2C_MASTER_DONE_IND;
1376                         npcm_i2c_master_stop(bus);
1377                         /* Clear SDA Status bit (by writing dummy byte) */
1378                         npcm_i2c_wr_byte(bus, 0xFF);
1379
1380                 } else {
1381                         /* last write-byte written on previous int - restart */
1382                         npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1383                         /* Generate repeated start upon next write to SDA */
1384                         npcm_i2c_master_start(bus);
1385
1386                         /*
1387                          * Receiving one byte only - stall after successful
1388                          * completion of send address byte. If we NACK here, and
1389                          * slave doesn't ACK the address, we might
1390                          * unintentionally NACK the next multi-byte read.
1391                          */
1392                         if (bus->rd_size == 1)
1393                                 npcm_i2c_stall_after_start(bus, true);
1394
1395                         /* Next int will occur on read */
1396                         bus->operation = I2C_READ_OPER;
1397                         /* send the slave address in read direction */
1398                         npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1);
1399                 }
1400         } else {
1401                 /* write next byte not last byte and not slave address */
1402                 if (!bus->fifo_use || bus->wr_size == 1) {
1403                         npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
1404                 } else {
1405                         wcount = bus->wr_size - bus->wr_ind;
1406                         npcm_i2c_set_fifo(bus, -1, wcount);
1407                         if (wcount)
1408                                 npcm_i2c_write_to_fifo_master(bus, wcount);
1409                 }
1410         }
1411 }
1412
1413 static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)
1414 {
1415         u16 block_extra_bytes_size;
1416         u8 data;
1417
1418         /* added bytes to the packet: */
1419         block_extra_bytes_size = bus->read_block_use + bus->PEC_use;
1420
1421         /*
1422          * Perform master read, distinguishing between last byte and the rest of
1423          * the bytes. The last byte should be read when the clock is stopped
1424          */
1425         if (bus->rd_ind == 0) { /* first byte handling: */
1426                 if (bus->read_block_use) {
1427                         /* first byte in block protocol is the size: */
1428                         data = npcm_i2c_rd_byte(bus);
1429                         data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX);
1430                         bus->rd_size = data + block_extra_bytes_size;
1431                         bus->rd_buf[bus->rd_ind++] = data;
1432
1433                         /* clear RX FIFO interrupt status: */
1434                         if (bus->fifo_use) {
1435                                 data = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1436                                 data = data | NPCM_I2CFIF_CTS_RXF_TXE;
1437                                 iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);
1438                         }
1439
1440                         npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);
1441                         npcm_i2c_stall_after_start(bus, false);
1442                 } else {
1443                         npcm_i2c_clear_tx_fifo(bus);
1444                         npcm_i2c_master_fifo_read(bus);
1445                 }
1446         } else {
1447                 if (bus->rd_size == block_extra_bytes_size &&
1448                     bus->read_block_use) {
1449                         bus->state = I2C_STOP_PENDING;
1450                         bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;
1451                         bus->cmd_err = -EIO;
1452                         npcm_i2c_eob_int(bus, true);
1453                         npcm_i2c_master_stop(bus);
1454                         npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));
1455                 } else {
1456                         npcm_i2c_master_fifo_read(bus);
1457                 }
1458         }
1459 }
1460
1461 static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus)
1462 {
1463         iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1464         npcm_i2c_nack(bus);
1465         bus->stop_ind = I2C_BUS_ERR_IND;
1466         npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1467 }
1468
1469 /* A NACK has occurred */
1470 static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus)
1471 {
1472         u8 val;
1473
1474         if (bus->nack_cnt < ULLONG_MAX)
1475                 bus->nack_cnt++;
1476
1477         if (bus->fifo_use) {
1478                 /*
1479                  * if there are still untransmitted bytes in TX FIFO
1480                  * reduce them from wr_ind
1481                  */
1482                 if (bus->operation == I2C_WRITE_OPER)
1483                         bus->wr_ind -= npcm_i2c_fifo_usage(bus);
1484
1485                 /* clear the FIFO */
1486                 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1487         }
1488
1489         /* In master write operation, got unexpected NACK */
1490         bus->stop_ind = I2C_NACK_IND;
1491         /* Only current master is allowed to issue Stop Condition */
1492         if (npcm_i2c_is_master(bus)) {
1493                 /* stopping in the middle */
1494                 npcm_i2c_eob_int(bus, false);
1495                 npcm_i2c_master_stop(bus);
1496
1497                 /* Clear SDA Status bit (by reading dummy byte) */
1498                 npcm_i2c_rd_byte(bus);
1499
1500                 /*
1501                  * The bus is released from stall only after the SW clears
1502                  * NEGACK bit. Then a Stop condition is sent.
1503                  */
1504                 npcm_i2c_clear_master_status(bus);
1505                 readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val,
1506                                           !(val & NPCM_I2CCST_BUSY), 10, 200);
1507                 /* Verify no status bits are still set after bus is released */
1508                 npcm_i2c_clear_master_status(bus);
1509         }
1510         bus->state = I2C_IDLE;
1511
1512         /*
1513          * In Master mode, NACK should be cleared only after STOP.
1514          * In such case, the bus is released from stall only after the
1515          * software clears NACK bit. Then a Stop condition is sent.
1516          */
1517         npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind);
1518 }
1519
1520         /* Master mode: a Bus Error has been identified */
1521 static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus)
1522 {
1523         if (bus->ber_cnt < ULLONG_MAX)
1524                 bus->ber_cnt++;
1525         bus->stop_ind = I2C_BUS_ERR_IND;
1526         if (npcm_i2c_is_master(bus)) {
1527                 npcm_i2c_master_abort(bus);
1528         } else {
1529                 npcm_i2c_clear_master_status(bus);
1530
1531                 /* Clear BB (BUS BUSY) bit */
1532                 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1533
1534                 bus->cmd_err = -EAGAIN;
1535                 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1536         }
1537         bus->state = I2C_IDLE;
1538 }
1539
1540         /* EOB: a master End Of Busy (meaning STOP completed) */
1541 static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus)
1542 {
1543         npcm_i2c_eob_int(bus, false);
1544         bus->state = I2C_IDLE;
1545         npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind);
1546 }
1547
1548 /* Address sent and requested stall occurred (Master mode) */
1549 static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus)
1550 {
1551         if (npcm_i2c_is_quick(bus)) {
1552                 bus->state = I2C_STOP_PENDING;
1553                 bus->stop_ind = I2C_MASTER_DONE_IND;
1554                 npcm_i2c_eob_int(bus, true);
1555                 npcm_i2c_master_stop(bus);
1556         } else if ((bus->rd_size == 1) && !bus->read_block_use) {
1557                 /*
1558                  * Receiving one byte only - set NACK after ensuring
1559                  * slave ACKed the address byte.
1560                  */
1561                 npcm_i2c_nack(bus);
1562         }
1563
1564         /* Reset stall-after-address-byte */
1565         npcm_i2c_stall_after_start(bus, false);
1566
1567         /* Clear stall only after setting STOP */
1568         iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST);
1569 }
1570
1571 /* SDA status is set - TX or RX, master */
1572 static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst)
1573 {
1574         u8 fif_cts;
1575
1576         if (!npcm_i2c_is_master(bus))
1577                 return;
1578
1579         if (bus->state == I2C_IDLE) {
1580                 bus->stop_ind = I2C_WAKE_UP_IND;
1581
1582                 if (npcm_i2c_is_quick(bus) || bus->read_block_use)
1583                         /*
1584                          * Need to stall after successful
1585                          * completion of sending address byte
1586                          */
1587                         npcm_i2c_stall_after_start(bus, true);
1588                 else
1589                         npcm_i2c_stall_after_start(bus, false);
1590
1591                 /*
1592                  * Receiving one byte only - stall after successful completion
1593                  * of sending address byte If we NACK here, and slave doesn't
1594                  * ACK the address, we might unintentionally NACK the next
1595                  * multi-byte read
1596                  */
1597                 if (bus->wr_size == 0 && bus->rd_size == 1)
1598                         npcm_i2c_stall_after_start(bus, true);
1599
1600                 /* Initiate I2C master tx */
1601
1602                 /* select bank 1 for FIFO regs */
1603                 npcm_i2c_select_bank(bus, I2C_BANK_1);
1604
1605                 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1606                 fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR;
1607
1608                 /* clear FIFO and relevant status bits. */
1609                 fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO;
1610                 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1611
1612                 /* re-enable */
1613                 fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE;
1614                 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1615
1616                 /*
1617                  * Configure the FIFO threshold:
1618                  * according to the needed # of bytes to read.
1619                  * Note: due to HW limitation can't config the rx fifo before it
1620                  * got and ACK on the restart. LAST bit will not be reset unless
1621                  * RX completed. It will stay set on the next tx.
1622                  */
1623                 if (bus->wr_size)
1624                         npcm_i2c_set_fifo(bus, -1, bus->wr_size);
1625                 else
1626                         npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1627
1628                 bus->state = I2C_OPER_STARTED;
1629
1630                 if (npcm_i2c_is_quick(bus) || bus->wr_size)
1631                         npcm_i2c_wr_byte(bus, bus->dest_addr);
1632                 else
1633                         npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0));
1634         /* SDA interrupt, after start\restart */
1635         } else {
1636                 if (NPCM_I2CST_XMIT & i2cst) {
1637                         bus->operation = I2C_WRITE_OPER;
1638                         npcm_i2c_irq_master_handler_write(bus);
1639                 } else {
1640                         bus->operation = I2C_READ_OPER;
1641                         npcm_i2c_irq_master_handler_read(bus);
1642                 }
1643         }
1644 }
1645
1646 static int npcm_i2c_int_master_handler(struct npcm_i2c *bus)
1647 {
1648         u8 i2cst;
1649         int ret = -EIO;
1650
1651         i2cst = ioread8(bus->reg + NPCM_I2CST);
1652
1653         if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) {
1654                 npcm_i2c_irq_handle_nmatch(bus);
1655                 return 0;
1656         }
1657         /* A NACK has occurred */
1658         if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) {
1659                 npcm_i2c_irq_handle_nack(bus);
1660                 return 0;
1661         }
1662
1663         /* Master mode: a Bus Error has been identified */
1664         if (FIELD_GET(NPCM_I2CST_BER, i2cst)) {
1665                 npcm_i2c_irq_handle_ber(bus);
1666                 return 0;
1667         }
1668
1669         /* EOB: a master End Of Busy (meaning STOP completed) */
1670         if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE,
1671                        ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&
1672             (FIELD_GET(NPCM_I2CCST3_EO_BUSY,
1673                        ioread8(bus->reg + NPCM_I2CCST3)))) {
1674                 npcm_i2c_irq_handle_eob(bus);
1675                 return 0;
1676         }
1677
1678         /* Address sent and requested stall occurred (Master mode) */
1679         if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) {
1680                 npcm_i2c_irq_handle_stall_after_start(bus);
1681                 ret = 0;
1682         }
1683
1684         /* SDA status is set - TX or RX, master */
1685         if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) ||
1686             (bus->fifo_use &&
1687             (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1688                 npcm_i2c_irq_handle_sda(bus, i2cst);
1689                 ret = 0;
1690         }
1691
1692         return ret;
1693 }
1694
1695 /* recovery using TGCLK functionality of the module */
1696 static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap)
1697 {
1698         u8               val;
1699         u8               fif_cts;
1700         bool             done = false;
1701         int              status = -ENOTRECOVERABLE;
1702         struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1703         /* Allow 3 bytes (27 toggles) to be read from the slave: */
1704         int              iter = 27;
1705
1706         if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) {
1707                 dev_dbg(bus->dev, "bus%d-0x%x recovery skipped, bus not stuck",
1708                         bus->num, bus->dest_addr);
1709                 npcm_i2c_reset(bus);
1710                 return 0;
1711         }
1712
1713         npcm_i2c_int_enable(bus, false);
1714         npcm_i2c_disable(bus);
1715         npcm_i2c_enable(bus);
1716         iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1717         npcm_i2c_clear_tx_fifo(bus);
1718         npcm_i2c_clear_rx_fifo(bus);
1719         iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1720         iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1721         npcm_i2c_stall_after_start(bus, false);
1722
1723         /* select bank 1 for FIFO regs */
1724         npcm_i2c_select_bank(bus, I2C_BANK_1);
1725
1726         /* clear FIFO and relevant status bits. */
1727         fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1728         fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
1729         fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
1730         iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1731         npcm_i2c_set_fifo(bus, -1, 0);
1732
1733         /* Repeat the following sequence until SDA is released */
1734         do {
1735                 /* Issue a single SCL toggle */
1736                 iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);
1737                 usleep_range(20, 30);
1738                 /* If SDA line is inactive (high), stop */
1739                 if (npcm_i2c_get_SDA(_adap)) {
1740                         done = true;
1741                         status = 0;
1742                 }
1743         } while (!done && iter--);
1744
1745         /* If SDA line is released: send start-addr-stop, to re-sync. */
1746         if (npcm_i2c_get_SDA(_adap)) {
1747                 /* Send an address byte in write direction: */
1748                 npcm_i2c_wr_byte(bus, bus->dest_addr);
1749                 npcm_i2c_master_start(bus);
1750                 /* Wait until START condition is sent */
1751                 status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val,
1752                                             20, 200);
1753                 /* If START condition was sent */
1754                 if (npcm_i2c_is_master(bus) > 0) {
1755                         usleep_range(20, 30);
1756                         npcm_i2c_master_stop(bus);
1757                         usleep_range(200, 500);
1758                 }
1759         }
1760         npcm_i2c_reset(bus);
1761         npcm_i2c_int_enable(bus, true);
1762
1763         if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1))
1764                 status = 0;
1765         else
1766                 status = -ENOTRECOVERABLE;
1767         if (status) {
1768                 if (bus->rec_fail_cnt < ULLONG_MAX)
1769                         bus->rec_fail_cnt++;
1770         } else {
1771                 if (bus->rec_succ_cnt < ULLONG_MAX)
1772                         bus->rec_succ_cnt++;
1773         }
1774         return status;
1775 }
1776
1777 /* recovery using bit banging functionality of the module */
1778 static void npcm_i2c_recovery_init(struct i2c_adapter *_adap)
1779 {
1780         struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1781         struct i2c_bus_recovery_info *rinfo = &bus->rinfo;
1782
1783         rinfo->recover_bus = npcm_i2c_recovery_tgclk;
1784
1785         /*
1786          * npcm i2c HW allows direct reading of SCL and SDA.
1787          * However, it does not support setting SCL and SDA directly.
1788          * The recovery function can toggle SCL when SDA is low (but not set)
1789          * Getter functions used internally, and can be used externally.
1790          */
1791         rinfo->get_scl = npcm_i2c_get_SCL;
1792         rinfo->get_sda = npcm_i2c_get_SDA;
1793         _adap->bus_recovery_info = rinfo;
1794 }
1795
1796 /* SCLFRQ min/max field values */
1797 #define SCLFRQ_MIN  10
1798 #define SCLFRQ_MAX  511
1799 #define clk_coef(freq, mul)     DIV_ROUND_UP((freq) * (mul), 1000000)
1800
1801 /*
1802  * npcm_i2c_init_clk: init HW timing parameters.
1803  * NPCM7XX i2c module timing parameters are dependent on module core clk (APB)
1804  * and bus frequency.
1805  * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are symmetric.
1806  * 400kHz bus requires asymmetric HT and LT. A different equation is recommended
1807  * by the HW designer, given core clock range (equations in comments below).
1808  *
1809  */
1810 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
1811 {
1812         u32  k1 = 0;
1813         u32  k2 = 0;
1814         u8   dbnct = 0;
1815         u32  sclfrq = 0;
1816         u8   hldt = 7;
1817         u8   fast_mode = 0;
1818         u32  src_clk_khz;
1819         u32  bus_freq_khz;
1820
1821         src_clk_khz = bus->apb_clk / 1000;
1822         bus_freq_khz = bus_freq_hz / 1000;
1823         bus->bus_freq = bus_freq_hz;
1824
1825         /* 100KHz and below: */
1826         if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
1827                 sclfrq = src_clk_khz / (bus_freq_khz * 4);
1828
1829                 if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)
1830                         return -EDOM;
1831
1832                 if (src_clk_khz >= 40000)
1833                         hldt = 17;
1834                 else if (src_clk_khz >= 12500)
1835                         hldt = 15;
1836                 else
1837                         hldt = 7;
1838         }
1839
1840         /* 400KHz: */
1841         else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
1842                 sclfrq = 0;
1843                 fast_mode = I2CCTL3_400K_MODE;
1844
1845                 if (src_clk_khz < 7500)
1846                         /* 400KHZ cannot be supported for core clock < 7.5MHz */
1847                         return -EDOM;
1848
1849                 else if (src_clk_khz >= 50000) {
1850                         k1 = 80;
1851                         k2 = 48;
1852                         hldt = 12;
1853                         dbnct = 7;
1854                 }
1855
1856                 /* Master or Slave with frequency > 25MHz */
1857                 else if (src_clk_khz > 25000) {
1858                         hldt = clk_coef(src_clk_khz, 300) + 7;
1859                         k1 = clk_coef(src_clk_khz, 1600);
1860                         k2 = clk_coef(src_clk_khz, 900);
1861                 }
1862         }
1863
1864         /* 1MHz: */
1865         else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
1866                 sclfrq = 0;
1867                 fast_mode = I2CCTL3_400K_MODE;
1868
1869                 /* 1MHZ cannot be supported for core clock < 24 MHz */
1870                 if (src_clk_khz < 24000)
1871                         return -EDOM;
1872
1873                 k1 = clk_coef(src_clk_khz, 620);
1874                 k2 = clk_coef(src_clk_khz, 380);
1875
1876                 /* Core clk > 40 MHz */
1877                 if (src_clk_khz > 40000) {
1878                         /*
1879                          * Set HLDT:
1880                          * SDA hold time:  (HLDT-7) * T(CLK) >= 120
1881                          * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7
1882                          */
1883                         hldt = clk_coef(src_clk_khz, 120) + 7;
1884                 } else {
1885                         hldt = 7;
1886                         dbnct = 2;
1887                 }
1888         }
1889
1890         /* Frequency larger than 1 MHz is not supported */
1891         else
1892                 return -EINVAL;
1893
1894         if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1895                 k1 = round_up(k1, 2);
1896                 k2 = round_up(k2 + 1, 2);
1897                 if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX ||
1898                     k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX)
1899                         return -EDOM;
1900         }
1901
1902         /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */
1903         iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F),
1904                  bus->reg + NPCM_I2CCTL2);
1905
1906         /* bits [8:7] are in I2CCTL3 reg */
1907         iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3),
1908                  bus->reg + NPCM_I2CCTL3);
1909
1910         /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */
1911         npcm_i2c_select_bank(bus, I2C_BANK_0);
1912
1913         if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1914                 /*
1915                  * Set SCL Low/High Time:
1916                  * k1 = 2 * SCLLT7-0 -> Low Time  = k1 / 2
1917                  * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2
1918                  */
1919                 iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT);
1920                 iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT);
1921
1922                 iowrite8(dbnct, bus->reg + NPCM_I2CCTL5);
1923         }
1924
1925         iowrite8(hldt, bus->reg + NPCM_I2CCTL4);
1926
1927         /* Return to Bank 1, and stay there by default: */
1928         npcm_i2c_select_bank(bus, I2C_BANK_1);
1929
1930         return 0;
1931 }
1932
1933 static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode,
1934                                 u32 bus_freq_hz)
1935 {
1936         u8 val;
1937         int ret;
1938
1939         /* Check whether module already enabled or frequency is out of bounds */
1940         if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) ||
1941             bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ)
1942                 return -EINVAL;
1943
1944         npcm_i2c_int_enable(bus, false);
1945         npcm_i2c_disable(bus);
1946
1947         /* Configure FIFO mode : */
1948         if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) {
1949                 bus->fifo_use = true;
1950                 npcm_i2c_select_bank(bus, I2C_BANK_0);
1951                 val = ioread8(bus->reg + NPCM_I2CFIF_CTL);
1952                 val |= NPCM_I2CFIF_CTL_FIFO_EN;
1953                 iowrite8(val, bus->reg + NPCM_I2CFIF_CTL);
1954                 npcm_i2c_select_bank(bus, I2C_BANK_1);
1955         } else {
1956                 bus->fifo_use = false;
1957         }
1958
1959         /* Configure I2C module clock frequency */
1960         ret = npcm_i2c_init_clk(bus, bus_freq_hz);
1961         if (ret) {
1962                 dev_err(bus->dev, "npcm_i2c_init_clk failed\n");
1963                 return ret;
1964         }
1965
1966         /* Enable module (before configuring CTL1) */
1967         npcm_i2c_enable(bus);
1968         bus->state = I2C_IDLE;
1969         val = ioread8(bus->reg + NPCM_I2CCTL1);
1970         val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS;
1971         iowrite8(val, bus->reg + NPCM_I2CCTL1);
1972
1973         npcm_i2c_reset(bus);
1974
1975         /* Check HW is OK: SDA and SCL should be high at this point. */
1976         if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) {
1977                 dev_err(bus->dev, "I2C%d init fail: lines are low\n", bus->num);
1978                 dev_err(bus->dev, "SDA=%d SCL=%d\n", npcm_i2c_get_SDA(&bus->adap),
1979                         npcm_i2c_get_SCL(&bus->adap));
1980                 return -ENXIO;
1981         }
1982
1983         npcm_i2c_int_enable(bus, true);
1984         return 0;
1985 }
1986
1987 static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
1988 {
1989         u32 clk_freq_hz;
1990         int ret;
1991
1992         /* Initialize the internal data structures */
1993         bus->state = I2C_DISABLE;
1994         bus->master_or_slave = I2C_SLAVE;
1995         bus->int_time_stamp = 0;
1996 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1997         bus->slave = NULL;
1998 #endif
1999
2000         ret = device_property_read_u32(&pdev->dev, "clock-frequency",
2001                                        &clk_freq_hz);
2002         if (ret) {
2003                 dev_info(&pdev->dev, "Could not read clock-frequency property");
2004                 clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
2005         }
2006
2007         ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz);
2008         if (ret) {
2009                 dev_err(&pdev->dev, "npcm_i2c_init_module failed\n");
2010                 return ret;
2011         }
2012
2013         return 0;
2014 }
2015
2016 static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id)
2017 {
2018         struct npcm_i2c *bus = dev_id;
2019
2020         if (npcm_i2c_is_master(bus))
2021                 bus->master_or_slave = I2C_MASTER;
2022
2023         if (bus->master_or_slave == I2C_MASTER) {
2024                 bus->int_time_stamp = jiffies;
2025                 if (!npcm_i2c_int_master_handler(bus))
2026                         return IRQ_HANDLED;
2027         }
2028 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2029         if (bus->slave) {
2030                 bus->master_or_slave = I2C_SLAVE;
2031                 if (npcm_i2c_int_slave_handler(bus))
2032                         return IRQ_HANDLED;
2033         }
2034 #endif
2035         /* Clear status bits for spurious interrupts */
2036         npcm_i2c_clear_master_status(bus);
2037
2038         return IRQ_HANDLED;
2039 }
2040
2041 static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
2042                                        u8 slave_addr, u16 nwrite, u16 nread,
2043                                        u8 *write_data, u8 *read_data,
2044                                        bool use_PEC, bool use_read_block)
2045 {
2046         if (bus->state != I2C_IDLE) {
2047                 bus->cmd_err = -EBUSY;
2048                 return false;
2049         }
2050         bus->dest_addr = slave_addr << 1;
2051         bus->wr_buf = write_data;
2052         bus->wr_size = nwrite;
2053         bus->wr_ind = 0;
2054         bus->rd_buf = read_data;
2055         bus->rd_size = nread;
2056         bus->rd_ind = 0;
2057         bus->PEC_use = 0;
2058
2059         /* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */
2060         if (nread)
2061                 bus->PEC_use = use_PEC;
2062
2063         bus->read_block_use = use_read_block;
2064         if (nread && !nwrite)
2065                 bus->operation = I2C_READ_OPER;
2066         else
2067                 bus->operation = I2C_WRITE_OPER;
2068         if (bus->fifo_use) {
2069                 u8 i2cfif_cts;
2070
2071                 npcm_i2c_select_bank(bus, I2C_BANK_1);
2072                 /* clear FIFO and relevant status bits. */
2073                 i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
2074                 i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
2075                 i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
2076                 iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);
2077         }
2078
2079         bus->state = I2C_IDLE;
2080         npcm_i2c_stall_after_start(bus, true);
2081         npcm_i2c_master_start(bus);
2082         return true;
2083 }
2084
2085 static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
2086                                 int num)
2087 {
2088         struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap);
2089         struct i2c_msg *msg0, *msg1;
2090         unsigned long time_left, flags;
2091         u16 nwrite, nread;
2092         u8 *write_data, *read_data;
2093         u8 slave_addr;
2094         unsigned long timeout;
2095         bool read_block = false;
2096         bool read_PEC = false;
2097         u8 bus_busy;
2098         unsigned long timeout_usec;
2099
2100         if (bus->state == I2C_DISABLE) {
2101                 dev_err(bus->dev, "I2C%d module is disabled", bus->num);
2102                 return -EINVAL;
2103         }
2104
2105         msg0 = &msgs[0];
2106         slave_addr = msg0->addr;
2107         if (msg0->flags & I2C_M_RD) { /* read */
2108                 nwrite = 0;
2109                 write_data = NULL;
2110                 read_data = msg0->buf;
2111                 if (msg0->flags & I2C_M_RECV_LEN) {
2112                         nread = 1;
2113                         read_block = true;
2114                         if (msg0->flags & I2C_CLIENT_PEC)
2115                                 read_PEC = true;
2116                 } else {
2117                         nread = msg0->len;
2118                 }
2119         } else { /* write */
2120                 nwrite = msg0->len;
2121                 write_data = msg0->buf;
2122                 nread = 0;
2123                 read_data = NULL;
2124                 if (num == 2) {
2125                         msg1 = &msgs[1];
2126                         read_data = msg1->buf;
2127                         if (msg1->flags & I2C_M_RECV_LEN) {
2128                                 nread = 1;
2129                                 read_block = true;
2130                                 if (msg1->flags & I2C_CLIENT_PEC)
2131                                         read_PEC = true;
2132                         } else {
2133                                 nread = msg1->len;
2134                                 read_block = false;
2135                         }
2136                 }
2137         }
2138
2139         /*
2140          * Adaptive TimeOut: estimated time in usec + 100% margin:
2141          * 2: double the timeout for clock stretching case
2142          * 9: bits per transaction (including the ack/nack)
2143          */
2144         timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite);
2145         timeout = max_t(unsigned long, bus->adap.timeout, usecs_to_jiffies(timeout_usec));
2146         if (nwrite >= 32 * 1024 || nread >= 32 * 1024) {
2147                 dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
2148                 return -EINVAL;
2149         }
2150
2151         time_left = jiffies + timeout + 1;
2152         do {
2153                 /*
2154                  * we must clear slave address immediately when the bus is not
2155                  * busy, so we spinlock it, but we don't keep the lock for the
2156                  * entire while since it is too long.
2157                  */
2158                 spin_lock_irqsave(&bus->lock, flags);
2159                 bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
2160 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2161                 if (!bus_busy && bus->slave)
2162                         iowrite8((bus->slave->addr & 0x7F),
2163                                  bus->reg + NPCM_I2CADDR1);
2164 #endif
2165                 spin_unlock_irqrestore(&bus->lock, flags);
2166
2167         } while (time_is_after_jiffies(time_left) && bus_busy);
2168
2169         if (bus_busy) {
2170                 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
2171                 npcm_i2c_reset(bus);
2172                 i2c_recover_bus(adap);
2173                 return -EAGAIN;
2174         }
2175
2176         npcm_i2c_init_params(bus);
2177         bus->dest_addr = slave_addr;
2178         bus->msgs = msgs;
2179         bus->msgs_num = num;
2180         bus->cmd_err = 0;
2181         bus->read_block_use = read_block;
2182
2183         reinit_completion(&bus->cmd_complete);
2184
2185         npcm_i2c_int_enable(bus, true);
2186
2187         if (npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread,
2188                                        write_data, read_data, read_PEC,
2189                                        read_block)) {
2190                 time_left = wait_for_completion_timeout(&bus->cmd_complete,
2191                                                         timeout);
2192
2193                 if (time_left == 0) {
2194                         if (bus->timeout_cnt < ULLONG_MAX)
2195                                 bus->timeout_cnt++;
2196                         if (bus->master_or_slave == I2C_MASTER) {
2197                                 i2c_recover_bus(adap);
2198                                 bus->cmd_err = -EIO;
2199                                 bus->state = I2C_IDLE;
2200                         }
2201                 }
2202         }
2203
2204         /* if there was BER, check if need to recover the bus: */
2205         if (bus->cmd_err == -EAGAIN)
2206                 bus->cmd_err = i2c_recover_bus(adap);
2207
2208         /*
2209          * After any type of error, check if LAST bit is still set,
2210          * due to a HW issue.
2211          * It cannot be cleared without resetting the module.
2212          */
2213         else if (bus->cmd_err &&
2214                  (bus->data->rxf_ctl_last_pec & ioread8(bus->reg + NPCM_I2CRXF_CTL)))
2215                 npcm_i2c_reset(bus);
2216
2217         /* After any xfer, successful or not, stall and EOB must be disabled */
2218         npcm_i2c_stall_after_start(bus, false);
2219         npcm_i2c_eob_int(bus, false);
2220
2221 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2222         /* reenable slave if it was enabled */
2223         if (bus->slave)
2224                 iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN,
2225                          bus->reg + NPCM_I2CADDR1);
2226 #else
2227         npcm_i2c_int_enable(bus, false);
2228 #endif
2229         return bus->cmd_err;
2230 }
2231
2232 static u32 npcm_i2c_functionality(struct i2c_adapter *adap)
2233 {
2234         return I2C_FUNC_I2C |
2235                I2C_FUNC_SMBUS_EMUL |
2236                I2C_FUNC_SMBUS_BLOCK_DATA |
2237                I2C_FUNC_SMBUS_PEC |
2238                I2C_FUNC_SLAVE;
2239 }
2240
2241 static const struct i2c_adapter_quirks npcm_i2c_quirks = {
2242         .max_read_len = 32768,
2243         .max_write_len = 32768,
2244         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
2245 };
2246
2247 static const struct i2c_algorithm npcm_i2c_algo = {
2248         .master_xfer = npcm_i2c_master_xfer,
2249         .functionality = npcm_i2c_functionality,
2250 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2251         .reg_slave      = npcm_i2c_reg_slave,
2252         .unreg_slave    = npcm_i2c_unreg_slave,
2253 #endif
2254 };
2255
2256 /* i2c debugfs directory: used to keep health monitor of i2c devices */
2257 static struct dentry *npcm_i2c_debugfs_dir;
2258
2259 static void npcm_i2c_init_debugfs(struct platform_device *pdev,
2260                                   struct npcm_i2c *bus)
2261 {
2262         struct dentry *d;
2263
2264         if (!npcm_i2c_debugfs_dir)
2265                 return;
2266         d = debugfs_create_dir(dev_name(&pdev->dev), npcm_i2c_debugfs_dir);
2267         if (IS_ERR_OR_NULL(d))
2268                 return;
2269         debugfs_create_u64("ber_cnt", 0444, d, &bus->ber_cnt);
2270         debugfs_create_u64("nack_cnt", 0444, d, &bus->nack_cnt);
2271         debugfs_create_u64("rec_succ_cnt", 0444, d, &bus->rec_succ_cnt);
2272         debugfs_create_u64("rec_fail_cnt", 0444, d, &bus->rec_fail_cnt);
2273         debugfs_create_u64("timeout_cnt", 0444, d, &bus->timeout_cnt);
2274         debugfs_create_u64("tx_complete_cnt", 0444, d, &bus->tx_complete_cnt);
2275
2276         bus->debugfs = d;
2277 }
2278
2279 static int npcm_i2c_probe_bus(struct platform_device *pdev)
2280 {
2281         struct device_node *np = pdev->dev.of_node;
2282         static struct regmap *gcr_regmap;
2283         struct device *dev = &pdev->dev;
2284         struct i2c_adapter *adap;
2285         struct npcm_i2c *bus;
2286         struct clk *i2c_clk;
2287         int irq;
2288         int ret;
2289
2290         bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
2291         if (!bus)
2292                 return -ENOMEM;
2293
2294         bus->dev = &pdev->dev;
2295
2296         bus->data = of_device_get_match_data(dev);
2297         if (!bus->data) {
2298                 dev_err(dev, "OF data missing\n");
2299                 return -EINVAL;
2300         }
2301
2302         bus->num = of_alias_get_id(pdev->dev.of_node, "i2c");
2303         /* core clk must be acquired to calculate module timing settings */
2304         i2c_clk = devm_clk_get(&pdev->dev, NULL);
2305         if (IS_ERR(i2c_clk))
2306                 return PTR_ERR(i2c_clk);
2307         bus->apb_clk = clk_get_rate(i2c_clk);
2308
2309         gcr_regmap = syscon_regmap_lookup_by_phandle(np, "nuvoton,sys-mgr");
2310         if (IS_ERR(gcr_regmap))
2311                 gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
2312
2313         if (IS_ERR(gcr_regmap))
2314                 return PTR_ERR(gcr_regmap);
2315         regmap_write(gcr_regmap, NPCM_I2CSEGCTL, bus->data->segctl_init_val);
2316
2317         bus->reg = devm_platform_ioremap_resource(pdev, 0);
2318         if (IS_ERR(bus->reg))
2319                 return PTR_ERR(bus->reg);
2320
2321         spin_lock_init(&bus->lock);
2322         init_completion(&bus->cmd_complete);
2323
2324         adap = &bus->adap;
2325         adap->owner = THIS_MODULE;
2326         adap->retries = 3;
2327         adap->timeout = msecs_to_jiffies(35);
2328         adap->algo = &npcm_i2c_algo;
2329         adap->quirks = &npcm_i2c_quirks;
2330         adap->algo_data = bus;
2331         adap->dev.parent = &pdev->dev;
2332         adap->dev.of_node = pdev->dev.of_node;
2333         adap->nr = pdev->id;
2334
2335         irq = platform_get_irq(pdev, 0);
2336         if (irq < 0)
2337                 return irq;
2338
2339         ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0,
2340                                dev_name(bus->dev), bus);
2341         if (ret)
2342                 return ret;
2343
2344         ret = __npcm_i2c_init(bus, pdev);
2345         if (ret)
2346                 return ret;
2347
2348         npcm_i2c_recovery_init(adap);
2349
2350         i2c_set_adapdata(adap, bus);
2351
2352         snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d",
2353                  bus->num);
2354         ret = i2c_add_numbered_adapter(&bus->adap);
2355         if (ret)
2356                 return ret;
2357
2358         platform_set_drvdata(pdev, bus);
2359         npcm_i2c_init_debugfs(pdev, bus);
2360         return 0;
2361 }
2362
2363 static void npcm_i2c_remove_bus(struct platform_device *pdev)
2364 {
2365         unsigned long lock_flags;
2366         struct npcm_i2c *bus = platform_get_drvdata(pdev);
2367
2368         debugfs_remove_recursive(bus->debugfs);
2369         spin_lock_irqsave(&bus->lock, lock_flags);
2370         npcm_i2c_disable(bus);
2371         spin_unlock_irqrestore(&bus->lock, lock_flags);
2372         i2c_del_adapter(&bus->adap);
2373 }
2374
2375 static const struct of_device_id npcm_i2c_bus_of_table[] = {
2376         { .compatible = "nuvoton,npcm750-i2c", .data = &npxm7xx_i2c_data },
2377         { .compatible = "nuvoton,npcm845-i2c", .data = &npxm8xx_i2c_data },
2378         {}
2379 };
2380 MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table);
2381
2382 static struct platform_driver npcm_i2c_bus_driver = {
2383         .probe = npcm_i2c_probe_bus,
2384         .remove_new = npcm_i2c_remove_bus,
2385         .driver = {
2386                 .name = "nuvoton-i2c",
2387                 .of_match_table = npcm_i2c_bus_of_table,
2388         }
2389 };
2390
2391 static int __init npcm_i2c_init(void)
2392 {
2393         int ret;
2394
2395         npcm_i2c_debugfs_dir = debugfs_create_dir("npcm_i2c", NULL);
2396
2397         ret = platform_driver_register(&npcm_i2c_bus_driver);
2398         if (ret) {
2399                 debugfs_remove_recursive(npcm_i2c_debugfs_dir);
2400                 return ret;
2401         }
2402
2403         return 0;
2404 }
2405 module_init(npcm_i2c_init);
2406
2407 static void __exit npcm_i2c_exit(void)
2408 {
2409         platform_driver_unregister(&npcm_i2c_bus_driver);
2410         debugfs_remove_recursive(npcm_i2c_debugfs_dir);
2411 }
2412 module_exit(npcm_i2c_exit);
2413
2414 MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>");
2415 MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>");
2416 MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>");
2417 MODULE_DESCRIPTION("Nuvoton I2C Bus Driver");
2418 MODULE_LICENSE("GPL v2");