1 // SPDX-License-Identifier: GPL-2.0
3 * Nuvoton NPCM7xx I2C Controller driver
5 * Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com
7 #include <linux/bitfield.h>
9 #include <linux/debugfs.h>
10 #include <linux/errno.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/irq.h>
15 #include <linux/jiffies.h>
16 #include <linux/kernel.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
30 * External I2C Interface driver xfer indication values, which indicate status
34 I2C_NO_STATUS_IND = 0,
37 I2C_SLAVE_XMIT_MISSING_DATA_IND,
38 I2C_SLAVE_RESTART_IND,
44 I2C_BLOCK_BYTES_ERR_IND,
45 I2C_SLAVE_RCV_MISSING_DATA_IND,
49 * Operation type values (used to define the operation currently running)
50 * module is interrupt driven, on each interrupt the current operation is
51 * checked to see if the module is currently reading or writing.
59 /* I2C Bank (module had 2 banks of registers) */
65 /* Internal I2C states values (for the I2C module state machine). */
75 #if IS_ENABLED(CONFIG_I2C_SLAVE)
76 /* Module supports setting multiple own slave addresses */
93 /* init register and default value required to enable module */
94 #define NPCM_I2CSEGCTL 0xE4
97 #define NPCM_I2CSDA 0x00
98 #define NPCM_I2CST 0x02
99 #define NPCM_I2CCST 0x04
100 #define NPCM_I2CCTL1 0x06
101 #define NPCM_I2CADDR1 0x08
102 #define NPCM_I2CCTL2 0x0A
103 #define NPCM_I2CADDR2 0x0C
104 #define NPCM_I2CCTL3 0x0E
105 #define NPCM_I2CCST2 0x18
106 #define NPCM_I2CCST3 0x19
110 #define NPCM_I2CADDR3 0x10
111 #define NPCM_I2CADDR7 0x11
112 #define NPCM_I2CADDR4 0x12
113 #define NPCM_I2CADDR8 0x13
114 #define NPCM_I2CADDR5 0x14
115 #define NPCM_I2CADDR9 0x15
116 #define NPCM_I2CADDR6 0x16
117 #define NPCM_I2CADDR10 0x17
119 #if IS_ENABLED(CONFIG_I2C_SLAVE)
121 * npcm_i2caddr array:
122 * The module supports having multiple own slave addresses.
123 * Since the addr regs are sprinkled all over the address space,
124 * use this array to get the address or each register.
126 #define I2C_NUM_OWN_ADDR 2
127 #define I2C_NUM_OWN_ADDR_SUPPORTED 2
129 static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = {
130 NPCM_I2CADDR1, NPCM_I2CADDR2,
134 #define NPCM_I2CCTL4 0x1A
135 #define NPCM_I2CCTL5 0x1B
136 #define NPCM_I2CSCLLT 0x1C /* SCL Low Time */
137 #define NPCM_I2CFIF_CTL 0x1D /* FIFO Control */
138 #define NPCM_I2CSCLHT 0x1E /* SCL High Time */
141 #define NPCM_I2CFIF_CTS 0x10 /* Both FIFOs Control and Status */
142 #define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */
143 #define NPCM_I2CT_OUT 0x14 /* Bus T.O. */
144 #define NPCM_I2CPEC 0x16 /* PEC Data */
145 #define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */
146 #define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */
147 #define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */
149 /* NPCM_I2CST reg fields */
150 #define NPCM_I2CST_XMIT BIT(0)
151 #define NPCM_I2CST_MASTER BIT(1)
152 #define NPCM_I2CST_NMATCH BIT(2)
153 #define NPCM_I2CST_STASTR BIT(3)
154 #define NPCM_I2CST_NEGACK BIT(4)
155 #define NPCM_I2CST_BER BIT(5)
156 #define NPCM_I2CST_SDAST BIT(6)
157 #define NPCM_I2CST_SLVSTP BIT(7)
159 /* NPCM_I2CCST reg fields */
160 #define NPCM_I2CCST_BUSY BIT(0)
161 #define NPCM_I2CCST_BB BIT(1)
162 #define NPCM_I2CCST_MATCH BIT(2)
163 #define NPCM_I2CCST_GCMATCH BIT(3)
164 #define NPCM_I2CCST_TSDA BIT(4)
165 #define NPCM_I2CCST_TGSCL BIT(5)
166 #define NPCM_I2CCST_MATCHAF BIT(6)
167 #define NPCM_I2CCST_ARPMATCH BIT(7)
169 /* NPCM_I2CCTL1 reg fields */
170 #define NPCM_I2CCTL1_START BIT(0)
171 #define NPCM_I2CCTL1_STOP BIT(1)
172 #define NPCM_I2CCTL1_INTEN BIT(2)
173 #define NPCM_I2CCTL1_EOBINTE BIT(3)
174 #define NPCM_I2CCTL1_ACK BIT(4)
175 #define NPCM_I2CCTL1_GCMEN BIT(5)
176 #define NPCM_I2CCTL1_NMINTE BIT(6)
177 #define NPCM_I2CCTL1_STASTRE BIT(7)
179 /* RW1S fields (inside a RW reg): */
180 #define NPCM_I2CCTL1_RWS \
181 (NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK)
183 /* npcm_i2caddr reg fields */
184 #define NPCM_I2CADDR_A GENMASK(6, 0)
185 #define NPCM_I2CADDR_SAEN BIT(7)
187 /* NPCM_I2CCTL2 reg fields */
188 #define I2CCTL2_ENABLE BIT(0)
189 #define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1)
191 /* NPCM_I2CCTL3 reg fields */
192 #define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0)
193 #define I2CCTL3_ARPMEN BIT(2)
194 #define I2CCTL3_IDL_START BIT(3)
195 #define I2CCTL3_400K_MODE BIT(4)
196 #define I2CCTL3_BNK_SEL BIT(5)
197 #define I2CCTL3_SDA_LVL BIT(6)
198 #define I2CCTL3_SCL_LVL BIT(7)
200 /* NPCM_I2CCST2 reg fields */
201 #define NPCM_I2CCST2_MATCHA1F BIT(0)
202 #define NPCM_I2CCST2_MATCHA2F BIT(1)
203 #define NPCM_I2CCST2_MATCHA3F BIT(2)
204 #define NPCM_I2CCST2_MATCHA4F BIT(3)
205 #define NPCM_I2CCST2_MATCHA5F BIT(4)
206 #define NPCM_I2CCST2_MATCHA6F BIT(5)
207 #define NPCM_I2CCST2_MATCHA7F BIT(5)
208 #define NPCM_I2CCST2_INTSTS BIT(7)
210 /* NPCM_I2CCST3 reg fields */
211 #define NPCM_I2CCST3_MATCHA8F BIT(0)
212 #define NPCM_I2CCST3_MATCHA9F BIT(1)
213 #define NPCM_I2CCST3_MATCHA10F BIT(2)
214 #define NPCM_I2CCST3_EO_BUSY BIT(7)
216 /* NPCM_I2CCTL4 reg fields */
217 #define I2CCTL4_HLDT GENMASK(5, 0)
218 #define I2CCTL4_LVL_WE BIT(7)
220 /* NPCM_I2CCTL5 reg fields */
221 #define I2CCTL5_DBNCT GENMASK(3, 0)
223 /* NPCM_I2CFIF_CTS reg fields */
224 #define NPCM_I2CFIF_CTS_RXF_TXE BIT(1)
225 #define NPCM_I2CFIF_CTS_RFTE_IE BIT(3)
226 #define NPCM_I2CFIF_CTS_CLR_FIFO BIT(6)
227 #define NPCM_I2CFIF_CTS_SLVRSTR BIT(7)
229 /* NPCM_I2CTXF_CTL reg field */
230 #define NPCM_I2CTXF_CTL_THR_TXIE BIT(6)
232 /* NPCM_I2CT_OUT reg fields */
233 #define NPCM_I2CT_OUT_TO_CKDIV GENMASK(5, 0)
234 #define NPCM_I2CT_OUT_T_OUTIE BIT(6)
235 #define NPCM_I2CT_OUT_T_OUTST BIT(7)
237 /* NPCM_I2CTXF_STS reg fields */
238 #define NPCM_I2CTXF_STS_TX_THST BIT(6)
240 /* NPCM_I2CRXF_STS reg fields */
241 #define NPCM_I2CRXF_STS_RX_THST BIT(6)
243 /* NPCM_I2CFIF_CTL reg fields */
244 #define NPCM_I2CFIF_CTL_FIFO_EN BIT(4)
246 /* NPCM_I2CRXF_CTL reg fields */
247 #define NPCM_I2CRXF_CTL_THR_RXIE BIT(6)
249 #define MAX_I2C_HW_FIFO_SIZE 32
251 /* I2C_VER reg fields */
252 #define I2C_VER_VERSION GENMASK(6, 0)
253 #define I2C_VER_FIFO_EN BIT(7)
255 /* stall/stuck timeout in us */
256 #define DEFAULT_STALL_COUNT 25
258 /* SCLFRQ field position */
259 #define SCLFRQ_0_TO_6 GENMASK(6, 0)
260 #define SCLFRQ_7_TO_8 GENMASK(8, 7)
262 /* supported clk settings. values in Hz. */
263 #define I2C_FREQ_MIN_HZ 10000
264 #define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ
266 struct npcm_i2c_data {
274 static const struct npcm_i2c_data npxm7xx_i2c_data = {
276 .segctl_init_val = 0x0333F000,
277 .txf_sts_tx_bytes = GENMASK(4, 0),
278 .rxf_sts_rx_bytes = GENMASK(4, 0),
279 .rxf_ctl_last_pec = BIT(5),
282 static const struct npcm_i2c_data npxm8xx_i2c_data = {
284 .segctl_init_val = 0x9333F000,
285 .txf_sts_tx_bytes = GENMASK(5, 0),
286 .rxf_sts_rx_bytes = GENMASK(5, 0),
287 .rxf_ctl_last_pec = BIT(7),
290 /* Status of one I2C module */
292 struct i2c_adapter adap;
294 unsigned char __iomem *reg;
295 const struct npcm_i2c_data *data;
296 spinlock_t lock; /* IRQ synchronization */
297 struct completion cmd_complete;
299 struct i2c_msg *msgs;
303 struct i2c_bus_recovery_info rinfo;
304 enum i2c_state state;
305 enum i2c_oper operation;
306 enum i2c_mode master_or_slave;
307 enum i2c_state_ind stop_ind;
316 u16 PEC_mask; /* PEC bit mask per slave address */
319 unsigned long int_time_stamp;
320 unsigned long bus_freq; /* in Hz */
321 #if IS_ENABLED(CONFIG_I2C_SLAVE)
323 struct i2c_client *slave;
328 u8 slv_rd_buf[MAX_I2C_HW_FIFO_SIZE];
329 u8 slv_wr_buf[MAX_I2C_HW_FIFO_SIZE];
331 struct dentry *debugfs; /* debugfs device directory */
340 static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
343 u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
345 if (bank == I2C_BANK_0)
346 i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL;
348 i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL;
349 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
352 static void npcm_i2c_init_params(struct npcm_i2c *bus)
354 bus->stop_ind = I2C_NO_STATUS_IND;
359 bus->read_block_use = false;
360 bus->int_time_stamp = 0;
361 bus->PEC_use = false;
363 #if IS_ENABLED(CONFIG_I2C_SLAVE)
365 bus->master_or_slave = I2C_SLAVE;
369 static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
371 iowrite8(data, bus->reg + NPCM_I2CSDA);
374 static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
376 return ioread8(bus->reg + NPCM_I2CSDA);
379 static int npcm_i2c_get_SCL(struct i2c_adapter *_adap)
381 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
383 return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
386 static int npcm_i2c_get_SDA(struct i2c_adapter *_adap)
388 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
390 return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
393 static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
395 if (bus->operation == I2C_READ_OPER)
397 if (bus->operation == I2C_WRITE_OPER)
402 /* quick protocol (just address) */
403 static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
405 return bus->wr_size == 0 && bus->rd_size == 0;
408 static void npcm_i2c_disable(struct npcm_i2c *bus)
412 #if IS_ENABLED(CONFIG_I2C_SLAVE)
415 /* Slave addresses removal */
416 for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++)
417 iowrite8(0, bus->reg + npcm_i2caddr[i]);
421 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
422 i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE;
423 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
425 bus->state = I2C_DISABLE;
428 static void npcm_i2c_enable(struct npcm_i2c *bus)
430 u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
432 i2cctl2 = i2cctl2 | I2CCTL2_ENABLE;
433 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
434 bus->state = I2C_IDLE;
437 /* enable\disable end of busy (EOB) interrupts */
438 static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
442 /* Clear EO_BUSY pending bit: */
443 val = ioread8(bus->reg + NPCM_I2CCST3);
444 val = val | NPCM_I2CCST3_EO_BUSY;
445 iowrite8(val, bus->reg + NPCM_I2CCST3);
447 val = ioread8(bus->reg + NPCM_I2CCTL1);
448 val &= ~NPCM_I2CCTL1_RWS;
450 val |= NPCM_I2CCTL1_EOBINTE;
452 val &= ~NPCM_I2CCTL1_EOBINTE;
453 iowrite8(val, bus->reg + NPCM_I2CCTL1);
456 static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
460 tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
461 /* check if TX FIFO is not empty */
462 if ((tx_fifo_sts & bus->data->txf_sts_tx_bytes) == 0)
465 /* check if TX FIFO status bit is set: */
466 return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts);
469 static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
473 rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
474 /* check if RX FIFO is not empty: */
475 if ((rx_fifo_sts & bus->data->rxf_sts_rx_bytes) == 0)
478 /* check if rx fifo full status is set: */
479 return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts);
482 static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
486 val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
487 val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE;
488 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
491 static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
495 val = ioread8(bus->reg + NPCM_I2CTXF_STS);
496 val = val | NPCM_I2CTXF_STS_TX_THST;
497 iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
500 static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
504 val = ioread8(bus->reg + NPCM_I2CRXF_STS);
505 val = val | NPCM_I2CRXF_STS_RX_THST;
506 iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
509 static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
513 val = ioread8(bus->reg + NPCM_I2CCTL1);
514 val &= ~NPCM_I2CCTL1_RWS;
516 val |= NPCM_I2CCTL1_INTEN;
518 val &= ~NPCM_I2CCTL1_INTEN;
519 iowrite8(val, bus->reg + NPCM_I2CCTL1);
522 static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
526 val = ioread8(bus->reg + NPCM_I2CCTL1);
527 val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK);
528 val |= NPCM_I2CCTL1_START;
529 iowrite8(val, bus->reg + NPCM_I2CCTL1);
532 static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
537 * override HW issue: I2C may fail to supply stop condition in Master
539 * Need to delay at least 5 us from the last int, before issueing a stop
541 udelay(10); /* function called from interrupt, can't sleep */
542 val = ioread8(bus->reg + NPCM_I2CCTL1);
543 val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK);
544 val |= NPCM_I2CCTL1_STOP;
545 iowrite8(val, bus->reg + NPCM_I2CCTL1);
550 npcm_i2c_select_bank(bus, I2C_BANK_1);
552 if (bus->operation == I2C_READ_OPER)
553 npcm_i2c_clear_rx_fifo(bus);
555 npcm_i2c_clear_tx_fifo(bus);
556 npcm_i2c_clear_fifo_int(bus);
557 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
560 static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
564 val = ioread8(bus->reg + NPCM_I2CCTL1);
565 val &= ~NPCM_I2CCTL1_RWS;
567 val |= NPCM_I2CCTL1_STASTRE;
569 val &= ~NPCM_I2CCTL1_STASTRE;
570 iowrite8(val, bus->reg + NPCM_I2CCTL1);
573 static inline void npcm_i2c_nack(struct npcm_i2c *bus)
577 val = ioread8(bus->reg + NPCM_I2CCTL1);
578 val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START);
579 val |= NPCM_I2CCTL1_ACK;
580 iowrite8(val, bus->reg + NPCM_I2CCTL1);
583 static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
587 /* Clear NEGACK, STASTR and BER bits */
588 val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR;
589 iowrite8(val, bus->reg + NPCM_I2CST);
592 #if IS_ENABLED(CONFIG_I2C_SLAVE)
593 static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
597 /* enable interrupt on slave match: */
598 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
599 i2cctl1 &= ~NPCM_I2CCTL1_RWS;
601 i2cctl1 |= NPCM_I2CCTL1_NMINTE;
603 i2cctl1 &= ~NPCM_I2CCTL1_NMINTE;
604 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
607 static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
608 u8 addr, bool enable)
614 sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable);
615 if (addr_type == I2C_GC_ADDR) {
616 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
618 i2cctl1 |= NPCM_I2CCTL1_GCMEN;
620 i2cctl1 &= ~NPCM_I2CCTL1_GCMEN;
621 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
623 } else if (addr_type == I2C_ARP_ADDR) {
624 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
626 i2cctl3 |= I2CCTL3_ARPMEN;
628 i2cctl3 &= ~I2CCTL3_ARPMEN;
629 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
632 if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
633 dev_err(bus->dev, "try to enable more than 2 SA not supported\n");
635 if (addr_type >= I2C_ARP_ADDR)
638 /* Set and enable the address */
639 iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
640 npcm_i2c_slave_int_enable(bus, enable);
646 static void npcm_i2c_reset(struct npcm_i2c *bus)
649 * Save I2CCTL1 relevant bits. It is being cleared when the module
653 #if IS_ENABLED(CONFIG_I2C_SLAVE)
657 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
659 npcm_i2c_disable(bus);
660 npcm_i2c_enable(bus);
662 /* Restore NPCM_I2CCTL1 Status */
663 i2cctl1 &= ~NPCM_I2CCTL1_RWS;
664 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
666 /* Clear BB (BUS BUSY) bit */
667 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
668 iowrite8(0xFF, bus->reg + NPCM_I2CST);
670 /* Clear and disable EOB */
671 npcm_i2c_eob_int(bus, false);
673 /* Clear all fifo bits: */
674 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
676 #if IS_ENABLED(CONFIG_I2C_SLAVE)
678 addr = bus->slave->addr;
679 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
683 /* Clear status bits for spurious interrupts */
684 npcm_i2c_clear_master_status(bus);
686 bus->state = I2C_IDLE;
689 static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
691 return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
694 static void npcm_i2c_callback(struct npcm_i2c *bus,
695 enum i2c_state_ind op_status, u16 info)
697 struct i2c_msg *msgs;
701 msgs_num = bus->msgs_num;
703 * check that transaction was not timed-out, and msgs still
704 * holds a valid value.
709 if (completion_done(&bus->cmd_complete))
713 case I2C_MASTER_DONE_IND:
714 bus->cmd_err = bus->msgs_num;
715 if (bus->tx_complete_cnt < ULLONG_MAX)
716 bus->tx_complete_cnt++;
718 case I2C_BLOCK_BYTES_ERR_IND:
719 /* Master tx finished and all transmit bytes were sent */
721 if (msgs[0].flags & I2C_M_RD)
723 else if (msgs_num == 2 &&
724 msgs[1].flags & I2C_M_RD)
727 if (completion_done(&bus->cmd_complete) == false)
728 complete(&bus->cmd_complete);
732 /* MASTER transmit got a NACK before tx all bytes */
733 bus->cmd_err = -ENXIO;
734 if (bus->master_or_slave == I2C_MASTER)
735 complete(&bus->cmd_complete);
738 case I2C_BUS_ERR_IND:
740 bus->cmd_err = -EAGAIN;
741 if (bus->master_or_slave == I2C_MASTER)
742 complete(&bus->cmd_complete);
745 case I2C_WAKE_UP_IND:
752 bus->operation = I2C_NO_OPER;
753 #if IS_ENABLED(CONFIG_I2C_SLAVE)
755 bus->master_or_slave = I2C_SLAVE;
759 static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
761 if (bus->operation == I2C_WRITE_OPER)
762 return (bus->data->txf_sts_tx_bytes &
763 ioread8(bus->reg + NPCM_I2CTXF_STS));
764 if (bus->operation == I2C_READ_OPER)
765 return (bus->data->rxf_sts_rx_bytes &
766 ioread8(bus->reg + NPCM_I2CRXF_STS));
770 static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
775 * Fill the FIFO, while the FIFO is not full and there are more bytes
778 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
779 while (max_bytes-- && size_free_fifo) {
780 if (bus->wr_ind < bus->wr_size)
781 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
783 npcm_i2c_wr_byte(bus, 0xFF);
784 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
790 * configure the FIFO before using it. If nread is -1 RX FIFO will not be
791 * configured. same for nwrite
793 static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
799 npcm_i2c_select_bank(bus, I2C_BANK_1);
800 npcm_i2c_clear_tx_fifo(bus);
801 npcm_i2c_clear_rx_fifo(bus);
803 /* configure RX FIFO */
805 rxf_ctl = min_t(int, nread, bus->data->fifo_size);
807 /* set LAST bit. if LAST is set next FIFO packet is nacked */
808 if (nread <= bus->data->fifo_size)
809 rxf_ctl |= bus->data->rxf_ctl_last_pec;
812 * if we are about to read the first byte in blk rd mode,
813 * don't NACK it. If slave returns zero size HW can't NACK
814 * it immediately, it will read extra byte and then NACK.
816 if (bus->rd_ind == 0 && bus->read_block_use) {
817 /* set fifo to read one byte, no last: */
822 iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
825 /* configure TX FIFO */
827 if (nwrite > bus->data->fifo_size)
828 /* data to send is more then FIFO size. */
829 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CTXF_CTL);
831 iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
833 npcm_i2c_clear_tx_fifo(bus);
837 static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
841 while (bytes_in_fifo--) {
842 data = npcm_i2c_rd_byte(bus);
843 if (bus->rd_ind < bus->rd_size)
844 bus->rd_buf[bus->rd_ind++] = data;
848 static void npcm_i2c_master_abort(struct npcm_i2c *bus)
850 /* Only current master is allowed to issue a stop condition */
851 if (!npcm_i2c_is_master(bus))
854 npcm_i2c_eob_int(bus, true);
855 npcm_i2c_master_stop(bus);
856 npcm_i2c_clear_master_status(bus);
859 #if IS_ENABLED(CONFIG_I2C_SLAVE)
860 static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
864 if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
865 dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n");
867 slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]);
872 static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
876 /* Set the enable bit */
879 for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) {
880 if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
881 iowrite8(0, bus->reg + npcm_i2caddr[i]);
887 static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
890 * Fill the FIFO, while the FIFO is not full and there are more bytes
893 npcm_i2c_clear_fifo_int(bus);
894 npcm_i2c_clear_tx_fifo(bus);
895 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
896 while (max_bytes-- && bus->data->fifo_size != npcm_i2c_fifo_usage(bus)) {
897 if (bus->slv_wr_size <= 0)
899 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
900 npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
902 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
907 static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
914 while (bytes_in_fifo--) {
915 data = npcm_i2c_rd_byte(bus);
917 bus->slv_rd_ind = bus->slv_rd_ind & (bus->data->fifo_size - 1);
918 bus->slv_rd_buf[bus->slv_rd_ind] = data;
921 /* 1st byte is length in block protocol: */
922 if (bus->slv_rd_ind == 1 && bus->read_block_use)
923 bus->slv_rd_size = data + bus->PEC_use + 1;
927 static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
932 int ret = bus->slv_wr_ind;
934 /* fill a cyclic buffer */
935 for (i = 0; i < bus->data->fifo_size; i++) {
936 if (bus->slv_wr_size >= bus->data->fifo_size)
938 if (bus->state == I2C_SLAVE_MATCH) {
939 i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
940 bus->state = I2C_OPER_STARTED;
942 i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
944 ind = (bus->slv_wr_ind + bus->slv_wr_size) & (bus->data->fifo_size - 1);
945 bus->slv_wr_buf[ind] = value;
948 return bus->data->fifo_size - ret;
951 static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
955 for (i = 0; i < bus->slv_rd_ind; i++)
956 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
957 &bus->slv_rd_buf[i]);
959 * once we send bytes up, need to reset the counter of the wr buf
960 * got data from master (new offset in device), ignore wr fifo:
962 if (bus->slv_rd_ind) {
963 bus->slv_wr_size = 0;
968 bus->slv_rd_size = bus->adap.quirks->max_read_len;
970 npcm_i2c_clear_fifo_int(bus);
971 npcm_i2c_clear_rx_fifo(bus);
974 static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
977 bus->state = I2C_OPER_STARTED;
978 bus->operation = I2C_READ_OPER;
979 bus->slv_rd_size = nread;
982 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
983 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
984 npcm_i2c_clear_tx_fifo(bus);
985 npcm_i2c_clear_rx_fifo(bus);
988 static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
994 bus->operation = I2C_WRITE_OPER;
996 /* get the next buffer */
997 npcm_i2c_slave_get_wr_buf(bus);
998 npcm_i2c_write_fifo_slave(bus, nwrite);
1002 * npcm_i2c_slave_wr_buf_sync:
1003 * currently slave IF only supports single byte operations.
1004 * in order to utilize the npcm HW FIFO, the driver will ask for 16 bytes
1005 * at a time, pack them in buffer, and then transmit them all together
1006 * to the FIFO and onward to the bus.
1007 * NACK on read will be once reached to bus->adap->quirks->max_read_len.
1008 * sending a NACK wherever the backend requests for it is not supported.
1009 * the next two functions allow reading to local buffer before writing it all
1012 static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus)
1016 left_in_fifo = bus->data->txf_sts_tx_bytes &
1017 ioread8(bus->reg + NPCM_I2CTXF_STS);
1019 /* fifo already full: */
1020 if (left_in_fifo >= bus->data->fifo_size ||
1021 bus->slv_wr_size >= bus->data->fifo_size)
1024 /* update the wr fifo index back to the untransmitted bytes: */
1025 bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo;
1026 bus->slv_wr_size = bus->slv_wr_size + left_in_fifo;
1028 if (bus->slv_wr_ind < 0)
1029 bus->slv_wr_ind += bus->data->fifo_size;
1032 static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus)
1034 if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) {
1036 * Slave got an address match with direction bit 1 so it should
1037 * transmit data. Write till the master will NACK
1039 bus->operation = I2C_WRITE_OPER;
1040 npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len,
1044 * Slave got an address match with direction bit 0 so it should
1046 * this module does not support saying no to bytes.
1047 * it will always ACK.
1049 bus->operation = I2C_READ_OPER;
1050 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1051 bus->stop_ind = I2C_SLAVE_RCV_IND;
1052 npcm_i2c_slave_send_rd_buf(bus);
1053 npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len,
1058 static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus)
1061 irqreturn_t ret = IRQ_NONE;
1062 u8 i2cst = ioread8(bus->reg + NPCM_I2CST);
1064 /* Slave: A NACK has occurred */
1065 if (NPCM_I2CST_NEGACK & i2cst) {
1066 bus->stop_ind = I2C_NACK_IND;
1067 npcm_i2c_slave_wr_buf_sync(bus);
1069 /* clear the FIFO */
1070 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1071 bus->reg + NPCM_I2CFIF_CTS);
1073 /* In slave write, NACK is OK, otherwise it is a problem */
1074 bus->stop_ind = I2C_NO_STATUS_IND;
1075 bus->operation = I2C_NO_OPER;
1076 bus->own_slave_addr = 0xFF;
1079 * Slave has to wait for STOP to decide this is the end
1080 * of the transaction. tx is not yet considered as done
1082 iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST);
1087 /* Slave mode: a Bus Error (BER) has been identified */
1088 if (NPCM_I2CST_BER & i2cst) {
1090 * Check whether bus arbitration or Start or Stop during data
1091 * xfer bus arbitration problem should not result in recovery
1093 bus->stop_ind = I2C_BUS_ERR_IND;
1095 /* wait for bus busy before clear fifo */
1096 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1098 bus->state = I2C_IDLE;
1101 * in BER case we might get 2 interrupts: one for slave one for
1102 * master ( for a channel which is master\slave switching)
1104 if (completion_done(&bus->cmd_complete) == false) {
1105 bus->cmd_err = -EIO;
1106 complete(&bus->cmd_complete);
1108 bus->own_slave_addr = 0xFF;
1109 iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST);
1113 /* A Slave Stop Condition has been identified */
1114 if (NPCM_I2CST_SLVSTP & i2cst) {
1115 u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus);
1117 bus->stop_ind = I2C_SLAVE_DONE_IND;
1119 if (bus->operation == I2C_READ_OPER)
1120 npcm_i2c_read_fifo_slave(bus, bytes_in_fifo);
1122 /* if the buffer is empty nothing will be sent */
1123 npcm_i2c_slave_send_rd_buf(bus);
1125 /* Slave done transmitting or receiving */
1126 bus->stop_ind = I2C_NO_STATUS_IND;
1129 * Note, just because we got here, it doesn't mean we through
1130 * away the wr buffer.
1131 * we keep it until the next received offset.
1133 bus->operation = I2C_NO_OPER;
1134 bus->own_slave_addr = 0xFF;
1135 i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0);
1136 iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST);
1137 if (bus->fifo_use) {
1138 npcm_i2c_clear_fifo_int(bus);
1139 npcm_i2c_clear_rx_fifo(bus);
1140 npcm_i2c_clear_tx_fifo(bus);
1142 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1143 bus->reg + NPCM_I2CFIF_CTS);
1145 bus->state = I2C_IDLE;
1149 /* restart condition occurred and Rx-FIFO was not empty */
1150 if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR,
1151 ioread8(bus->reg + NPCM_I2CFIF_CTS))) {
1152 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1153 bus->master_or_slave = I2C_SLAVE;
1154 if (bus->operation == I2C_READ_OPER)
1155 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1156 bus->operation = I2C_WRITE_OPER;
1157 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1158 val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR |
1159 NPCM_I2CFIF_CTS_RXF_TXE;
1160 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
1161 npcm_i2c_slave_rd_wr(bus);
1165 /* A Slave Address Match has been identified */
1166 if (NPCM_I2CST_NMATCH & i2cst) {
1169 /* Address match automatically implies slave mode */
1170 bus->master_or_slave = I2C_SLAVE;
1171 npcm_i2c_clear_fifo_int(bus);
1172 npcm_i2c_clear_rx_fifo(bus);
1173 npcm_i2c_clear_tx_fifo(bus);
1174 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1175 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
1176 if (NPCM_I2CST_XMIT & i2cst) {
1177 bus->operation = I2C_WRITE_OPER;
1179 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED,
1181 bus->operation = I2C_READ_OPER;
1183 if (bus->own_slave_addr == 0xFF) {
1184 /* Check which type of address match */
1185 val = ioread8(bus->reg + NPCM_I2CCST);
1186 if (NPCM_I2CCST_MATCH & val) {
1188 enum i2c_addr eaddr;
1192 i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3);
1193 i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2);
1196 * the i2c module can response to 10 own SA.
1197 * check which one was addressed by the master.
1198 * respond to the first one.
1200 addr = ((i2ccst3 & 0x07) << 7) |
1203 eaddr = (enum i2c_addr)info;
1204 addr = npcm_i2c_get_slave_addr(bus, eaddr);
1206 bus->own_slave_addr = addr;
1207 if (bus->PEC_mask & BIT(info))
1208 bus->PEC_use = true;
1210 bus->PEC_use = false;
1212 if (NPCM_I2CCST_GCMATCH & val)
1213 bus->own_slave_addr = 0;
1214 if (NPCM_I2CCST_ARPMATCH & val)
1215 bus->own_slave_addr = 0x61;
1219 * Slave match can happen in two options:
1220 * 1. Start, SA, read (slave read without further ado)
1221 * 2. Start, SA, read, data, restart, SA, read, ...
1222 * (slave read in fragmented mode)
1223 * 3. Start, SA, write, data, restart, SA, read, ..
1224 * (regular write-read mode)
1226 if ((bus->state == I2C_OPER_STARTED &&
1227 bus->operation == I2C_READ_OPER &&
1228 bus->stop_ind == I2C_SLAVE_XMIT_IND) ||
1229 bus->stop_ind == I2C_SLAVE_RCV_IND) {
1230 /* slave tx after slave rx w/o STOP */
1231 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1235 if (NPCM_I2CST_XMIT & i2cst)
1236 bus->stop_ind = I2C_SLAVE_XMIT_IND;
1238 bus->stop_ind = I2C_SLAVE_RCV_IND;
1239 bus->state = I2C_SLAVE_MATCH;
1240 npcm_i2c_slave_rd_wr(bus);
1241 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1245 /* Slave SDA status is set - tx or rx */
1246 if ((NPCM_I2CST_SDAST & i2cst) ||
1248 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1249 npcm_i2c_slave_rd_wr(bus);
1250 iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST);
1255 * If irq is not one of the above, make sure EOB is disabled and all
1256 * status bits are cleared.
1258 if (ret == IRQ_NONE) {
1259 npcm_i2c_eob_int(bus, false);
1260 npcm_i2c_clear_master_status(bus);
1266 static int npcm_i2c_reg_slave(struct i2c_client *client)
1268 unsigned long lock_flags;
1269 struct npcm_i2c *bus = i2c_get_adapdata(client->adapter);
1271 bus->slave = client;
1276 if (client->flags & I2C_CLIENT_TEN)
1277 return -EAFNOSUPPORT;
1279 spin_lock_irqsave(&bus->lock, lock_flags);
1281 npcm_i2c_init_params(bus);
1282 bus->slv_rd_size = 0;
1283 bus->slv_wr_size = 0;
1284 bus->slv_rd_ind = 0;
1285 bus->slv_wr_ind = 0;
1286 if (client->flags & I2C_CLIENT_PEC)
1287 bus->PEC_use = true;
1289 dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num,
1290 client->addr, bus->PEC_use);
1292 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true);
1293 npcm_i2c_clear_fifo_int(bus);
1294 npcm_i2c_clear_rx_fifo(bus);
1295 npcm_i2c_clear_tx_fifo(bus);
1296 npcm_i2c_slave_int_enable(bus, true);
1298 spin_unlock_irqrestore(&bus->lock, lock_flags);
1302 static int npcm_i2c_unreg_slave(struct i2c_client *client)
1304 struct npcm_i2c *bus = client->adapter->algo_data;
1305 unsigned long lock_flags;
1307 spin_lock_irqsave(&bus->lock, lock_flags);
1309 spin_unlock_irqrestore(&bus->lock, lock_flags);
1312 npcm_i2c_slave_int_enable(bus, false);
1313 npcm_i2c_remove_slave_addr(bus, client->addr);
1315 spin_unlock_irqrestore(&bus->lock, lock_flags);
1318 #endif /* CONFIG_I2C_SLAVE */
1320 static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
1324 enum i2c_state_ind ind = I2C_MASTER_DONE_IND;
1326 fifo_bytes = npcm_i2c_fifo_usage(bus);
1327 rcount = bus->rd_size - bus->rd_ind;
1330 * In order not to change the RX_TRH during transaction (we found that
1331 * this might be problematic if it takes too much time to read the FIFO)
1332 * we read the data in the following way. If the number of bytes to
1333 * read == FIFO Size + C (where C < FIFO Size)then first read C bytes
1334 * and in the next int we read rest of the data.
1336 if (rcount < (2 * bus->data->fifo_size) && rcount > bus->data->fifo_size)
1337 fifo_bytes = rcount - bus->data->fifo_size;
1339 if (rcount <= fifo_bytes) {
1340 /* last bytes are about to be read - end of tx */
1341 bus->state = I2C_STOP_PENDING;
1342 bus->stop_ind = ind;
1343 npcm_i2c_eob_int(bus, true);
1344 /* Stop should be set before reading last byte. */
1345 npcm_i2c_master_stop(bus);
1346 npcm_i2c_read_fifo(bus, fifo_bytes);
1348 npcm_i2c_read_fifo(bus, fifo_bytes);
1349 rcount = bus->rd_size - bus->rd_ind;
1350 npcm_i2c_set_fifo(bus, rcount, -1);
1354 static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus)
1359 npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */
1361 /* Master write operation - last byte handling */
1362 if (bus->wr_ind == bus->wr_size) {
1363 if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0)
1365 * No more bytes to send (to add to the FIFO),
1366 * however the FIFO is not empty yet. It is
1367 * still in the middle of tx. Currently there's nothing
1368 * to do except for waiting to the end of the tx
1369 * We will get an int when the FIFO will get empty.
1373 if (bus->rd_size == 0) {
1374 /* all bytes have been written, in wr only operation */
1375 npcm_i2c_eob_int(bus, true);
1376 bus->state = I2C_STOP_PENDING;
1377 bus->stop_ind = I2C_MASTER_DONE_IND;
1378 npcm_i2c_master_stop(bus);
1379 /* Clear SDA Status bit (by writing dummy byte) */
1380 npcm_i2c_wr_byte(bus, 0xFF);
1383 /* last write-byte written on previous int - restart */
1384 npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1385 /* Generate repeated start upon next write to SDA */
1386 npcm_i2c_master_start(bus);
1389 * Receiving one byte only - stall after successful
1390 * completion of send address byte. If we NACK here, and
1391 * slave doesn't ACK the address, we might
1392 * unintentionally NACK the next multi-byte read.
1394 if (bus->rd_size == 1)
1395 npcm_i2c_stall_after_start(bus, true);
1397 /* Next int will occur on read */
1398 bus->operation = I2C_READ_OPER;
1399 /* send the slave address in read direction */
1400 npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1);
1403 /* write next byte not last byte and not slave address */
1404 if (!bus->fifo_use || bus->wr_size == 1) {
1405 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
1407 wcount = bus->wr_size - bus->wr_ind;
1408 npcm_i2c_set_fifo(bus, -1, wcount);
1410 npcm_i2c_write_to_fifo_master(bus, wcount);
1415 static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)
1417 u16 block_extra_bytes_size;
1420 /* added bytes to the packet: */
1421 block_extra_bytes_size = bus->read_block_use + bus->PEC_use;
1424 * Perform master read, distinguishing between last byte and the rest of
1425 * the bytes. The last byte should be read when the clock is stopped
1427 if (bus->rd_ind == 0) { /* first byte handling: */
1428 if (bus->read_block_use) {
1429 /* first byte in block protocol is the size: */
1430 data = npcm_i2c_rd_byte(bus);
1431 data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX);
1432 bus->rd_size = data + block_extra_bytes_size;
1433 bus->rd_buf[bus->rd_ind++] = data;
1435 /* clear RX FIFO interrupt status: */
1436 if (bus->fifo_use) {
1437 data = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1438 data = data | NPCM_I2CFIF_CTS_RXF_TXE;
1439 iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);
1442 npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);
1443 npcm_i2c_stall_after_start(bus, false);
1445 npcm_i2c_clear_tx_fifo(bus);
1446 npcm_i2c_master_fifo_read(bus);
1449 if (bus->rd_size == block_extra_bytes_size &&
1450 bus->read_block_use) {
1451 bus->state = I2C_STOP_PENDING;
1452 bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;
1453 bus->cmd_err = -EIO;
1454 npcm_i2c_eob_int(bus, true);
1455 npcm_i2c_master_stop(bus);
1456 npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));
1458 npcm_i2c_master_fifo_read(bus);
1463 static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus)
1465 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1467 bus->stop_ind = I2C_BUS_ERR_IND;
1468 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1471 /* A NACK has occurred */
1472 static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus)
1476 if (bus->nack_cnt < ULLONG_MAX)
1479 if (bus->fifo_use) {
1481 * if there are still untransmitted bytes in TX FIFO
1482 * reduce them from wr_ind
1484 if (bus->operation == I2C_WRITE_OPER)
1485 bus->wr_ind -= npcm_i2c_fifo_usage(bus);
1487 /* clear the FIFO */
1488 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1491 /* In master write operation, got unexpected NACK */
1492 bus->stop_ind = I2C_NACK_IND;
1493 /* Only current master is allowed to issue Stop Condition */
1494 if (npcm_i2c_is_master(bus)) {
1495 /* stopping in the middle */
1496 npcm_i2c_eob_int(bus, false);
1497 npcm_i2c_master_stop(bus);
1499 /* Clear SDA Status bit (by reading dummy byte) */
1500 npcm_i2c_rd_byte(bus);
1503 * The bus is released from stall only after the SW clears
1504 * NEGACK bit. Then a Stop condition is sent.
1506 npcm_i2c_clear_master_status(bus);
1507 readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val,
1508 !(val & NPCM_I2CCST_BUSY), 10, 200);
1509 /* Verify no status bits are still set after bus is released */
1510 npcm_i2c_clear_master_status(bus);
1512 bus->state = I2C_IDLE;
1515 * In Master mode, NACK should be cleared only after STOP.
1516 * In such case, the bus is released from stall only after the
1517 * software clears NACK bit. Then a Stop condition is sent.
1519 npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind);
1522 /* Master mode: a Bus Error has been identified */
1523 static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus)
1525 if (bus->ber_cnt < ULLONG_MAX)
1527 bus->stop_ind = I2C_BUS_ERR_IND;
1528 if (npcm_i2c_is_master(bus)) {
1529 npcm_i2c_master_abort(bus);
1531 npcm_i2c_clear_master_status(bus);
1533 /* Clear BB (BUS BUSY) bit */
1534 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1536 bus->cmd_err = -EAGAIN;
1537 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1539 bus->state = I2C_IDLE;
1542 /* EOB: a master End Of Busy (meaning STOP completed) */
1543 static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus)
1545 npcm_i2c_eob_int(bus, false);
1546 bus->state = I2C_IDLE;
1547 npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind);
1550 /* Address sent and requested stall occurred (Master mode) */
1551 static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus)
1553 if (npcm_i2c_is_quick(bus)) {
1554 bus->state = I2C_STOP_PENDING;
1555 bus->stop_ind = I2C_MASTER_DONE_IND;
1556 npcm_i2c_eob_int(bus, true);
1557 npcm_i2c_master_stop(bus);
1558 } else if ((bus->rd_size == 1) && !bus->read_block_use) {
1560 * Receiving one byte only - set NACK after ensuring
1561 * slave ACKed the address byte.
1566 /* Reset stall-after-address-byte */
1567 npcm_i2c_stall_after_start(bus, false);
1569 /* Clear stall only after setting STOP */
1570 iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST);
1573 /* SDA status is set - TX or RX, master */
1574 static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst)
1578 if (!npcm_i2c_is_master(bus))
1581 if (bus->state == I2C_IDLE) {
1582 bus->stop_ind = I2C_WAKE_UP_IND;
1584 if (npcm_i2c_is_quick(bus) || bus->read_block_use)
1586 * Need to stall after successful
1587 * completion of sending address byte
1589 npcm_i2c_stall_after_start(bus, true);
1591 npcm_i2c_stall_after_start(bus, false);
1594 * Receiving one byte only - stall after successful completion
1595 * of sending address byte If we NACK here, and slave doesn't
1596 * ACK the address, we might unintentionally NACK the next
1599 if (bus->wr_size == 0 && bus->rd_size == 1)
1600 npcm_i2c_stall_after_start(bus, true);
1602 /* Initiate I2C master tx */
1604 /* select bank 1 for FIFO regs */
1605 npcm_i2c_select_bank(bus, I2C_BANK_1);
1607 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1608 fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR;
1610 /* clear FIFO and relevant status bits. */
1611 fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO;
1612 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1615 fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE;
1616 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1619 * Configure the FIFO threshold:
1620 * according to the needed # of bytes to read.
1621 * Note: due to HW limitation can't config the rx fifo before it
1622 * got and ACK on the restart. LAST bit will not be reset unless
1623 * RX completed. It will stay set on the next tx.
1626 npcm_i2c_set_fifo(bus, -1, bus->wr_size);
1628 npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1630 bus->state = I2C_OPER_STARTED;
1632 if (npcm_i2c_is_quick(bus) || bus->wr_size)
1633 npcm_i2c_wr_byte(bus, bus->dest_addr);
1635 npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0));
1636 /* SDA interrupt, after start\restart */
1638 if (NPCM_I2CST_XMIT & i2cst) {
1639 bus->operation = I2C_WRITE_OPER;
1640 npcm_i2c_irq_master_handler_write(bus);
1642 bus->operation = I2C_READ_OPER;
1643 npcm_i2c_irq_master_handler_read(bus);
1648 static int npcm_i2c_int_master_handler(struct npcm_i2c *bus)
1653 i2cst = ioread8(bus->reg + NPCM_I2CST);
1655 if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) {
1656 npcm_i2c_irq_handle_nmatch(bus);
1659 /* A NACK has occurred */
1660 if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) {
1661 npcm_i2c_irq_handle_nack(bus);
1665 /* Master mode: a Bus Error has been identified */
1666 if (FIELD_GET(NPCM_I2CST_BER, i2cst)) {
1667 npcm_i2c_irq_handle_ber(bus);
1671 /* EOB: a master End Of Busy (meaning STOP completed) */
1672 if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE,
1673 ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&
1674 (FIELD_GET(NPCM_I2CCST3_EO_BUSY,
1675 ioread8(bus->reg + NPCM_I2CCST3)))) {
1676 npcm_i2c_irq_handle_eob(bus);
1680 /* Address sent and requested stall occurred (Master mode) */
1681 if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) {
1682 npcm_i2c_irq_handle_stall_after_start(bus);
1686 /* SDA status is set - TX or RX, master */
1687 if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) ||
1689 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1690 npcm_i2c_irq_handle_sda(bus, i2cst);
1697 /* recovery using TGCLK functionality of the module */
1698 static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap)
1703 int status = -ENOTRECOVERABLE;
1704 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1705 /* Allow 3 bytes (27 toggles) to be read from the slave: */
1708 if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) {
1709 dev_dbg(bus->dev, "bus%d-0x%x recovery skipped, bus not stuck",
1710 bus->num, bus->dest_addr);
1711 npcm_i2c_reset(bus);
1715 npcm_i2c_int_enable(bus, false);
1716 npcm_i2c_disable(bus);
1717 npcm_i2c_enable(bus);
1718 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1719 npcm_i2c_clear_tx_fifo(bus);
1720 npcm_i2c_clear_rx_fifo(bus);
1721 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1722 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1723 npcm_i2c_stall_after_start(bus, false);
1725 /* select bank 1 for FIFO regs */
1726 npcm_i2c_select_bank(bus, I2C_BANK_1);
1728 /* clear FIFO and relevant status bits. */
1729 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1730 fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
1731 fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
1732 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1733 npcm_i2c_set_fifo(bus, -1, 0);
1735 /* Repeat the following sequence until SDA is released */
1737 /* Issue a single SCL toggle */
1738 iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);
1739 usleep_range(20, 30);
1740 /* If SDA line is inactive (high), stop */
1741 if (npcm_i2c_get_SDA(_adap)) {
1745 } while (!done && iter--);
1747 /* If SDA line is released: send start-addr-stop, to re-sync. */
1748 if (npcm_i2c_get_SDA(_adap)) {
1749 /* Send an address byte in write direction: */
1750 npcm_i2c_wr_byte(bus, bus->dest_addr);
1751 npcm_i2c_master_start(bus);
1752 /* Wait until START condition is sent */
1753 status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val,
1755 /* If START condition was sent */
1756 if (npcm_i2c_is_master(bus) > 0) {
1757 usleep_range(20, 30);
1758 npcm_i2c_master_stop(bus);
1759 usleep_range(200, 500);
1762 npcm_i2c_reset(bus);
1763 npcm_i2c_int_enable(bus, true);
1765 if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1))
1768 status = -ENOTRECOVERABLE;
1770 if (bus->rec_fail_cnt < ULLONG_MAX)
1771 bus->rec_fail_cnt++;
1773 if (bus->rec_succ_cnt < ULLONG_MAX)
1774 bus->rec_succ_cnt++;
1779 /* recovery using bit banging functionality of the module */
1780 static void npcm_i2c_recovery_init(struct i2c_adapter *_adap)
1782 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1783 struct i2c_bus_recovery_info *rinfo = &bus->rinfo;
1785 rinfo->recover_bus = npcm_i2c_recovery_tgclk;
1788 * npcm i2c HW allows direct reading of SCL and SDA.
1789 * However, it does not support setting SCL and SDA directly.
1790 * The recovery function can toggle SCL when SDA is low (but not set)
1791 * Getter functions used internally, and can be used externally.
1793 rinfo->get_scl = npcm_i2c_get_SCL;
1794 rinfo->get_sda = npcm_i2c_get_SDA;
1795 _adap->bus_recovery_info = rinfo;
1798 /* SCLFRQ min/max field values */
1799 #define SCLFRQ_MIN 10
1800 #define SCLFRQ_MAX 511
1801 #define clk_coef(freq, mul) DIV_ROUND_UP((freq) * (mul), 1000000)
1804 * npcm_i2c_init_clk: init HW timing parameters.
1805 * NPCM7XX i2c module timing parameters are dependent on module core clk (APB)
1806 * and bus frequency.
1807 * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are symmetric.
1808 * 400kHz bus requires asymmetric HT and LT. A different equation is recommended
1809 * by the HW designer, given core clock range (equations in comments below).
1812 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
1823 src_clk_khz = bus->apb_clk / 1000;
1824 bus_freq_khz = bus_freq_hz / 1000;
1825 bus->bus_freq = bus_freq_hz;
1827 /* 100KHz and below: */
1828 if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
1829 sclfrq = src_clk_khz / (bus_freq_khz * 4);
1831 if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)
1834 if (src_clk_khz >= 40000)
1836 else if (src_clk_khz >= 12500)
1843 else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
1845 fast_mode = I2CCTL3_400K_MODE;
1847 if (src_clk_khz < 7500)
1848 /* 400KHZ cannot be supported for core clock < 7.5MHz */
1851 else if (src_clk_khz >= 50000) {
1858 /* Master or Slave with frequency > 25MHz */
1859 else if (src_clk_khz > 25000) {
1860 hldt = clk_coef(src_clk_khz, 300) + 7;
1861 k1 = clk_coef(src_clk_khz, 1600);
1862 k2 = clk_coef(src_clk_khz, 900);
1867 else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
1869 fast_mode = I2CCTL3_400K_MODE;
1871 /* 1MHZ cannot be supported for core clock < 24 MHz */
1872 if (src_clk_khz < 24000)
1875 k1 = clk_coef(src_clk_khz, 620);
1876 k2 = clk_coef(src_clk_khz, 380);
1878 /* Core clk > 40 MHz */
1879 if (src_clk_khz > 40000) {
1882 * SDA hold time: (HLDT-7) * T(CLK) >= 120
1883 * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7
1885 hldt = clk_coef(src_clk_khz, 120) + 7;
1892 /* Frequency larger than 1 MHz is not supported */
1896 if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1897 k1 = round_up(k1, 2);
1898 k2 = round_up(k2 + 1, 2);
1899 if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX ||
1900 k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX)
1904 /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */
1905 iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F),
1906 bus->reg + NPCM_I2CCTL2);
1908 /* bits [8:7] are in I2CCTL3 reg */
1909 iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3),
1910 bus->reg + NPCM_I2CCTL3);
1912 /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */
1913 npcm_i2c_select_bank(bus, I2C_BANK_0);
1915 if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1917 * Set SCL Low/High Time:
1918 * k1 = 2 * SCLLT7-0 -> Low Time = k1 / 2
1919 * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2
1921 iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT);
1922 iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT);
1924 iowrite8(dbnct, bus->reg + NPCM_I2CCTL5);
1927 iowrite8(hldt, bus->reg + NPCM_I2CCTL4);
1929 /* Return to Bank 1, and stay there by default: */
1930 npcm_i2c_select_bank(bus, I2C_BANK_1);
1935 static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode,
1941 /* Check whether module already enabled or frequency is out of bounds */
1942 if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) ||
1943 bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ)
1946 npcm_i2c_int_enable(bus, false);
1947 npcm_i2c_disable(bus);
1949 /* Configure FIFO mode : */
1950 if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) {
1951 bus->fifo_use = true;
1952 npcm_i2c_select_bank(bus, I2C_BANK_0);
1953 val = ioread8(bus->reg + NPCM_I2CFIF_CTL);
1954 val |= NPCM_I2CFIF_CTL_FIFO_EN;
1955 iowrite8(val, bus->reg + NPCM_I2CFIF_CTL);
1956 npcm_i2c_select_bank(bus, I2C_BANK_1);
1958 bus->fifo_use = false;
1961 /* Configure I2C module clock frequency */
1962 ret = npcm_i2c_init_clk(bus, bus_freq_hz);
1964 dev_err(bus->dev, "npcm_i2c_init_clk failed\n");
1968 /* Enable module (before configuring CTL1) */
1969 npcm_i2c_enable(bus);
1970 bus->state = I2C_IDLE;
1971 val = ioread8(bus->reg + NPCM_I2CCTL1);
1972 val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS;
1973 iowrite8(val, bus->reg + NPCM_I2CCTL1);
1975 npcm_i2c_reset(bus);
1977 /* Check HW is OK: SDA and SCL should be high at this point. */
1978 if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) {
1979 dev_err(bus->dev, "I2C%d init fail: lines are low\n", bus->num);
1980 dev_err(bus->dev, "SDA=%d SCL=%d\n", npcm_i2c_get_SDA(&bus->adap),
1981 npcm_i2c_get_SCL(&bus->adap));
1985 npcm_i2c_int_enable(bus, true);
1989 static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
1994 /* Initialize the internal data structures */
1995 bus->state = I2C_DISABLE;
1996 bus->master_or_slave = I2C_SLAVE;
1997 bus->int_time_stamp = 0;
1998 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2002 ret = device_property_read_u32(&pdev->dev, "clock-frequency",
2005 dev_info(&pdev->dev, "Could not read clock-frequency property");
2006 clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
2009 ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz);
2011 dev_err(&pdev->dev, "npcm_i2c_init_module failed\n");
2018 static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id)
2020 struct npcm_i2c *bus = dev_id;
2022 if (npcm_i2c_is_master(bus))
2023 bus->master_or_slave = I2C_MASTER;
2025 if (bus->master_or_slave == I2C_MASTER) {
2026 bus->int_time_stamp = jiffies;
2027 if (!npcm_i2c_int_master_handler(bus))
2030 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2032 bus->master_or_slave = I2C_SLAVE;
2033 if (npcm_i2c_int_slave_handler(bus))
2037 /* Clear status bits for spurious interrupts */
2038 npcm_i2c_clear_master_status(bus);
2043 static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
2044 u8 slave_addr, u16 nwrite, u16 nread,
2045 u8 *write_data, u8 *read_data,
2046 bool use_PEC, bool use_read_block)
2048 if (bus->state != I2C_IDLE) {
2049 bus->cmd_err = -EBUSY;
2052 bus->dest_addr = slave_addr << 1;
2053 bus->wr_buf = write_data;
2054 bus->wr_size = nwrite;
2056 bus->rd_buf = read_data;
2057 bus->rd_size = nread;
2061 /* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */
2063 bus->PEC_use = use_PEC;
2065 bus->read_block_use = use_read_block;
2066 if (nread && !nwrite)
2067 bus->operation = I2C_READ_OPER;
2069 bus->operation = I2C_WRITE_OPER;
2070 if (bus->fifo_use) {
2073 npcm_i2c_select_bank(bus, I2C_BANK_1);
2074 /* clear FIFO and relevant status bits. */
2075 i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
2076 i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
2077 i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
2078 iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);
2081 bus->state = I2C_IDLE;
2082 npcm_i2c_stall_after_start(bus, true);
2083 npcm_i2c_master_start(bus);
2087 static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
2090 struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap);
2091 struct i2c_msg *msg0, *msg1;
2092 unsigned long time_left, flags;
2094 u8 *write_data, *read_data;
2096 unsigned long timeout;
2097 bool read_block = false;
2098 bool read_PEC = false;
2100 unsigned long timeout_usec;
2102 if (bus->state == I2C_DISABLE) {
2103 dev_err(bus->dev, "I2C%d module is disabled", bus->num);
2108 slave_addr = msg0->addr;
2109 if (msg0->flags & I2C_M_RD) { /* read */
2112 read_data = msg0->buf;
2113 if (msg0->flags & I2C_M_RECV_LEN) {
2116 if (msg0->flags & I2C_CLIENT_PEC)
2121 } else { /* write */
2123 write_data = msg0->buf;
2128 read_data = msg1->buf;
2129 if (msg1->flags & I2C_M_RECV_LEN) {
2132 if (msg1->flags & I2C_CLIENT_PEC)
2142 * Adaptive TimeOut: estimated time in usec + 100% margin:
2143 * 2: double the timeout for clock stretching case
2144 * 9: bits per transaction (including the ack/nack)
2146 timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite);
2147 timeout = max_t(unsigned long, bus->adap.timeout, usecs_to_jiffies(timeout_usec));
2148 if (nwrite >= 32 * 1024 || nread >= 32 * 1024) {
2149 dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
2153 time_left = jiffies + timeout + 1;
2156 * we must clear slave address immediately when the bus is not
2157 * busy, so we spinlock it, but we don't keep the lock for the
2158 * entire while since it is too long.
2160 spin_lock_irqsave(&bus->lock, flags);
2161 bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
2162 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2163 if (!bus_busy && bus->slave)
2164 iowrite8((bus->slave->addr & 0x7F),
2165 bus->reg + NPCM_I2CADDR1);
2167 spin_unlock_irqrestore(&bus->lock, flags);
2169 } while (time_is_after_jiffies(time_left) && bus_busy);
2172 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
2173 npcm_i2c_reset(bus);
2174 i2c_recover_bus(adap);
2178 npcm_i2c_init_params(bus);
2179 bus->dest_addr = slave_addr;
2181 bus->msgs_num = num;
2183 bus->read_block_use = read_block;
2185 reinit_completion(&bus->cmd_complete);
2187 npcm_i2c_int_enable(bus, true);
2189 if (npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread,
2190 write_data, read_data, read_PEC,
2192 time_left = wait_for_completion_timeout(&bus->cmd_complete,
2195 if (time_left == 0) {
2196 if (bus->timeout_cnt < ULLONG_MAX)
2198 if (bus->master_or_slave == I2C_MASTER) {
2199 i2c_recover_bus(adap);
2200 bus->cmd_err = -EIO;
2201 bus->state = I2C_IDLE;
2206 /* if there was BER, check if need to recover the bus: */
2207 if (bus->cmd_err == -EAGAIN)
2208 bus->cmd_err = i2c_recover_bus(adap);
2211 * After any type of error, check if LAST bit is still set,
2212 * due to a HW issue.
2213 * It cannot be cleared without resetting the module.
2215 else if (bus->cmd_err &&
2216 (bus->data->rxf_ctl_last_pec & ioread8(bus->reg + NPCM_I2CRXF_CTL)))
2217 npcm_i2c_reset(bus);
2219 /* After any xfer, successful or not, stall and EOB must be disabled */
2220 npcm_i2c_stall_after_start(bus, false);
2221 npcm_i2c_eob_int(bus, false);
2223 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2224 /* reenable slave if it was enabled */
2226 iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN,
2227 bus->reg + NPCM_I2CADDR1);
2229 npcm_i2c_int_enable(bus, false);
2231 return bus->cmd_err;
2234 static u32 npcm_i2c_functionality(struct i2c_adapter *adap)
2236 return I2C_FUNC_I2C |
2237 I2C_FUNC_SMBUS_EMUL |
2238 I2C_FUNC_SMBUS_BLOCK_DATA |
2239 I2C_FUNC_SMBUS_PEC |
2243 static const struct i2c_adapter_quirks npcm_i2c_quirks = {
2244 .max_read_len = 32768,
2245 .max_write_len = 32768,
2246 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
2249 static const struct i2c_algorithm npcm_i2c_algo = {
2250 .master_xfer = npcm_i2c_master_xfer,
2251 .functionality = npcm_i2c_functionality,
2252 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2253 .reg_slave = npcm_i2c_reg_slave,
2254 .unreg_slave = npcm_i2c_unreg_slave,
2258 /* i2c debugfs directory: used to keep health monitor of i2c devices */
2259 static struct dentry *npcm_i2c_debugfs_dir;
2261 static void npcm_i2c_init_debugfs(struct platform_device *pdev,
2262 struct npcm_i2c *bus)
2266 if (!npcm_i2c_debugfs_dir)
2268 d = debugfs_create_dir(dev_name(&pdev->dev), npcm_i2c_debugfs_dir);
2269 if (IS_ERR_OR_NULL(d))
2271 debugfs_create_u64("ber_cnt", 0444, d, &bus->ber_cnt);
2272 debugfs_create_u64("nack_cnt", 0444, d, &bus->nack_cnt);
2273 debugfs_create_u64("rec_succ_cnt", 0444, d, &bus->rec_succ_cnt);
2274 debugfs_create_u64("rec_fail_cnt", 0444, d, &bus->rec_fail_cnt);
2275 debugfs_create_u64("timeout_cnt", 0444, d, &bus->timeout_cnt);
2276 debugfs_create_u64("tx_complete_cnt", 0444, d, &bus->tx_complete_cnt);
2281 static int npcm_i2c_probe_bus(struct platform_device *pdev)
2283 struct device_node *np = pdev->dev.of_node;
2284 static struct regmap *gcr_regmap;
2285 struct device *dev = &pdev->dev;
2286 struct i2c_adapter *adap;
2287 struct npcm_i2c *bus;
2288 struct clk *i2c_clk;
2292 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
2296 bus->dev = &pdev->dev;
2298 bus->data = of_device_get_match_data(dev);
2300 dev_err(dev, "OF data missing\n");
2304 bus->num = of_alias_get_id(pdev->dev.of_node, "i2c");
2305 /* core clk must be acquired to calculate module timing settings */
2306 i2c_clk = devm_clk_get(&pdev->dev, NULL);
2307 if (IS_ERR(i2c_clk))
2308 return PTR_ERR(i2c_clk);
2309 bus->apb_clk = clk_get_rate(i2c_clk);
2311 gcr_regmap = syscon_regmap_lookup_by_phandle(np, "nuvoton,sys-mgr");
2312 if (IS_ERR(gcr_regmap))
2313 gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
2315 if (IS_ERR(gcr_regmap))
2316 return PTR_ERR(gcr_regmap);
2317 regmap_write(gcr_regmap, NPCM_I2CSEGCTL, bus->data->segctl_init_val);
2319 bus->reg = devm_platform_ioremap_resource(pdev, 0);
2320 if (IS_ERR(bus->reg))
2321 return PTR_ERR(bus->reg);
2323 spin_lock_init(&bus->lock);
2324 init_completion(&bus->cmd_complete);
2327 adap->owner = THIS_MODULE;
2329 adap->timeout = msecs_to_jiffies(35);
2330 adap->algo = &npcm_i2c_algo;
2331 adap->quirks = &npcm_i2c_quirks;
2332 adap->algo_data = bus;
2333 adap->dev.parent = &pdev->dev;
2334 adap->dev.of_node = pdev->dev.of_node;
2335 adap->nr = pdev->id;
2337 irq = platform_get_irq(pdev, 0);
2341 ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0,
2342 dev_name(bus->dev), bus);
2346 ret = __npcm_i2c_init(bus, pdev);
2350 npcm_i2c_recovery_init(adap);
2352 i2c_set_adapdata(adap, bus);
2354 snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d",
2356 ret = i2c_add_numbered_adapter(&bus->adap);
2360 platform_set_drvdata(pdev, bus);
2361 npcm_i2c_init_debugfs(pdev, bus);
2365 static int npcm_i2c_remove_bus(struct platform_device *pdev)
2367 unsigned long lock_flags;
2368 struct npcm_i2c *bus = platform_get_drvdata(pdev);
2370 debugfs_remove_recursive(bus->debugfs);
2371 spin_lock_irqsave(&bus->lock, lock_flags);
2372 npcm_i2c_disable(bus);
2373 spin_unlock_irqrestore(&bus->lock, lock_flags);
2374 i2c_del_adapter(&bus->adap);
2378 static const struct of_device_id npcm_i2c_bus_of_table[] = {
2379 { .compatible = "nuvoton,npcm750-i2c", .data = &npxm7xx_i2c_data },
2380 { .compatible = "nuvoton,npcm845-i2c", .data = &npxm8xx_i2c_data },
2383 MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table);
2385 static struct platform_driver npcm_i2c_bus_driver = {
2386 .probe = npcm_i2c_probe_bus,
2387 .remove = npcm_i2c_remove_bus,
2389 .name = "nuvoton-i2c",
2390 .of_match_table = npcm_i2c_bus_of_table,
2394 static int __init npcm_i2c_init(void)
2396 npcm_i2c_debugfs_dir = debugfs_create_dir("npcm_i2c", NULL);
2397 return platform_driver_register(&npcm_i2c_bus_driver);
2399 module_init(npcm_i2c_init);
2401 static void __exit npcm_i2c_exit(void)
2403 platform_driver_unregister(&npcm_i2c_bus_driver);
2404 debugfs_remove_recursive(npcm_i2c_debugfs_dir);
2406 module_exit(npcm_i2c_exit);
2408 MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>");
2409 MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>");
2410 MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>");
2411 MODULE_DESCRIPTION("Nuvoton I2C Bus Driver");
2412 MODULE_LICENSE("GPL v2");