2 * Freescale MXS I2C bus driver
4 * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
6 * based on a (non-working) driver which was:
8 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * TODO: add dma-support if platform-support for it is available
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
19 #include <linux/slab.h>
20 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/i2c.h>
23 #include <linux/err.h>
24 #include <linux/interrupt.h>
25 #include <linux/completion.h>
26 #include <linux/platform_device.h>
27 #include <linux/jiffies.h>
29 #include <linux/pinctrl/consumer.h>
31 #include <linux/of_device.h>
32 #include <linux/of_i2c.h>
34 #include <mach/common.h>
36 #define DRIVER_NAME "mxs-i2c"
38 #define MXS_I2C_CTRL0 (0x00)
39 #define MXS_I2C_CTRL0_SET (0x04)
41 #define MXS_I2C_CTRL0_SFTRST 0x80000000
42 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
43 #define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
44 #define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
45 #define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
46 #define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
47 #define MXS_I2C_CTRL0_DIRECTION 0x00010000
48 #define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
50 #define MXS_I2C_CTRL1 (0x40)
51 #define MXS_I2C_CTRL1_SET (0x44)
52 #define MXS_I2C_CTRL1_CLR (0x48)
54 #define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
55 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
56 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
57 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
58 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
59 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
60 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
61 #define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
63 #define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
64 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
65 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
66 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
67 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
68 MXS_I2C_CTRL1_SLAVE_IRQ)
70 #define MXS_I2C_QUEUECTRL (0x60)
71 #define MXS_I2C_QUEUECTRL_SET (0x64)
72 #define MXS_I2C_QUEUECTRL_CLR (0x68)
74 #define MXS_I2C_QUEUECTRL_QUEUE_RUN 0x20
75 #define MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE 0x04
77 #define MXS_I2C_QUEUESTAT (0x70)
78 #define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000
79 #define MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK 0x0000001F
81 #define MXS_I2C_QUEUECMD (0x80)
83 #define MXS_I2C_QUEUEDATA (0x90)
85 #define MXS_I2C_DATA (0xa0)
88 #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
89 MXS_I2C_CTRL0_PRE_SEND_START | \
90 MXS_I2C_CTRL0_MASTER_MODE | \
91 MXS_I2C_CTRL0_DIRECTION | \
92 MXS_I2C_CTRL0_XFER_COUNT(1))
94 #define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
95 MXS_I2C_CTRL0_MASTER_MODE | \
96 MXS_I2C_CTRL0_DIRECTION)
98 #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
99 MXS_I2C_CTRL0_MASTER_MODE)
102 * struct mxs_i2c_dev - per device, private MXS-I2C data
104 * @dev: driver model device node
105 * @regs: IO registers pointer
106 * @cmd_complete: completion object for transaction wait
107 * @cmd_err: error code for last transaction
108 * @adapter: i2c subsystem adapter node
113 struct completion cmd_complete;
115 struct i2c_adapter adapter;
119 * TODO: check if calls to here are really needed. If not, we could get rid of
120 * mxs_reset_block and the mach-dependency. Needs an I2C analyzer, probably.
122 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
124 mxs_reset_block(i2c->regs);
125 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
126 writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
127 i2c->regs + MXS_I2C_QUEUECTRL_SET);
130 static void mxs_i2c_pioq_setup_read(struct mxs_i2c_dev *i2c, u8 addr, int len,
135 writel(MXS_CMD_I2C_SELECT, i2c->regs + MXS_I2C_QUEUECMD);
137 data = (addr << 1) | I2C_SMBUS_READ;
138 writel(data, i2c->regs + MXS_I2C_DATA);
140 data = MXS_CMD_I2C_READ | MXS_I2C_CTRL0_XFER_COUNT(len) | flags;
141 writel(data, i2c->regs + MXS_I2C_QUEUECMD);
144 static void mxs_i2c_pioq_setup_write(struct mxs_i2c_dev *i2c,
145 u8 addr, u8 *buf, int len, int flags)
150 data = MXS_CMD_I2C_WRITE | MXS_I2C_CTRL0_XFER_COUNT(len + 1) | flags;
151 writel(data, i2c->regs + MXS_I2C_QUEUECMD);
154 * We have to copy the slave address (u8) and buffer (arbitrary number
155 * of u8) into the data register (u32). To achieve that, the u8 are put
156 * into the MSBs of 'data' which is then shifted for the next u8. When
157 * appropriate, 'data' is written to MXS_I2C_DATA. So, the first u32
161 * 10987654|32109876|54321098|76543210
162 * --------+--------+--------+--------
163 * buffer+2|buffer+1|buffer+0|slave_addr
166 data = ((addr << 1) | I2C_SMBUS_WRITE) << 24;
168 for (i = 0; i < len; i++) {
170 data |= buf[i] << 24;
172 writel(data, i2c->regs + MXS_I2C_DATA);
175 /* Write out the remaining bytes if any */
176 shifts_left = 24 - (i & 3) * 8;
178 writel(data >> shifts_left, i2c->regs + MXS_I2C_DATA);
182 * TODO: should be replaceable with a waitqueue and RD_QUEUE_IRQ (setting the
183 * rd_threshold to 1). Couldn't get this to work, though.
185 static int mxs_i2c_wait_for_data(struct mxs_i2c_dev *i2c)
187 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
189 while (readl(i2c->regs + MXS_I2C_QUEUESTAT)
190 & MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY) {
191 if (time_after(jiffies, timeout))
199 static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len)
204 for (i = 0; i < len; i++) {
206 if (mxs_i2c_wait_for_data(i2c))
208 data = readl(i2c->regs + MXS_I2C_QUEUEDATA);
210 buf[i] = data & 0xff;
218 * Low level master read/write transaction.
220 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
223 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
227 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
228 msg->addr, msg->len, msg->flags, stop);
233 init_completion(&i2c->cmd_complete);
236 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
238 if (msg->flags & I2C_M_RD)
239 mxs_i2c_pioq_setup_read(i2c, msg->addr, msg->len, flags);
241 mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, msg->len,
244 writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
245 i2c->regs + MXS_I2C_QUEUECTRL_SET);
247 ret = wait_for_completion_timeout(&i2c->cmd_complete,
248 msecs_to_jiffies(1000));
252 if ((!i2c->cmd_err) && (msg->flags & I2C_M_RD)) {
253 ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len);
258 if (i2c->cmd_err == -ENXIO)
261 writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
262 i2c->regs + MXS_I2C_QUEUECTRL_CLR);
264 dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err);
269 dev_dbg(i2c->dev, "Timeout!\n");
274 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
280 for (i = 0; i < num; i++) {
281 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
289 static u32 mxs_i2c_func(struct i2c_adapter *adap)
291 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
294 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
296 struct mxs_i2c_dev *i2c = dev_id;
297 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
303 if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
304 i2c->cmd_err = -ENXIO;
305 else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
306 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
307 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
308 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
311 is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) &
312 MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0;
314 if (is_last_cmd || i2c->cmd_err)
315 complete(&i2c->cmd_complete);
317 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
322 static const struct i2c_algorithm mxs_i2c_algo = {
323 .master_xfer = mxs_i2c_xfer,
324 .functionality = mxs_i2c_func,
327 static int __devinit mxs_i2c_probe(struct platform_device *pdev)
329 struct device *dev = &pdev->dev;
330 struct mxs_i2c_dev *i2c;
331 struct i2c_adapter *adap;
332 struct pinctrl *pinctrl;
333 struct resource *res;
334 resource_size_t res_size;
337 pinctrl = devm_pinctrl_get_select_default(dev);
339 return PTR_ERR(pinctrl);
341 i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
345 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
349 res_size = resource_size(res);
350 if (!devm_request_mem_region(dev, res->start, res_size, res->name))
353 i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
357 irq = platform_get_irq(pdev, 0);
361 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
366 platform_set_drvdata(pdev, i2c);
368 /* Do reset to enforce correct startup after pinmuxing */
371 adap = &i2c->adapter;
372 strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
373 adap->owner = THIS_MODULE;
374 adap->algo = &mxs_i2c_algo;
375 adap->dev.parent = dev;
377 adap->dev.of_node = pdev->dev.of_node;
378 i2c_set_adapdata(adap, i2c);
379 err = i2c_add_numbered_adapter(adap);
381 dev_err(dev, "Failed to add adapter (%d)\n", err);
382 writel(MXS_I2C_CTRL0_SFTRST,
383 i2c->regs + MXS_I2C_CTRL0_SET);
387 of_i2c_register_devices(adap);
392 static int __devexit mxs_i2c_remove(struct platform_device *pdev)
394 struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
397 ret = i2c_del_adapter(&i2c->adapter);
401 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
403 platform_set_drvdata(pdev, NULL);
408 static const struct of_device_id mxs_i2c_dt_ids[] = {
409 { .compatible = "fsl,imx28-i2c", },
412 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
414 static struct platform_driver mxs_i2c_driver = {
417 .owner = THIS_MODULE,
418 .of_match_table = mxs_i2c_dt_ids,
420 .remove = __devexit_p(mxs_i2c_remove),
423 static int __init mxs_i2c_init(void)
425 return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
427 subsys_initcall(mxs_i2c_init);
429 static void __exit mxs_i2c_exit(void)
431 platform_driver_unregister(&mxs_i2c_driver);
433 module_exit(mxs_i2c_exit);
435 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
436 MODULE_DESCRIPTION("MXS I2C Bus Driver");
437 MODULE_LICENSE("GPL");
438 MODULE_ALIAS("platform:" DRIVER_NAME);