drivers/i2c/busses/i2c-mv64xxx.c

   1 /*
   2  * Driver for the i2c controller on the Marvell line of host bridges
   3  * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
   4  *
   5  * Author: Mark A. Greer <mgreer@mvista.com>
   6  *
   7  * 2005 (c) MontaVista, Software, Inc.  This file is licensed under
   8  * the terms of the GNU General Public License version 2.  This program
   9  * is licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/slab.h>
  14 #include <linux/module.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/i2c.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/mv643xx_i2c.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pinctrl/consumer.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/reset.h>
  23 #include <linux/io.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/clk.h>
  28 #include <linux/err.h>
  29 #include <linux/delay.h>
  30
  31 #define MV64XXX_I2C_ADDR_ADDR(val)                      ((val & 0x7f) << 1)
  32 #define MV64XXX_I2C_BAUD_DIV_N(val)                     (val & 0x7)
  33 #define MV64XXX_I2C_BAUD_DIV_M(val)                     ((val & 0xf) << 3)
  34
  35 #define MV64XXX_I2C_REG_CONTROL_ACK                     BIT(2)
  36 #define MV64XXX_I2C_REG_CONTROL_IFLG                    BIT(3)
  37 #define MV64XXX_I2C_REG_CONTROL_STOP                    BIT(4)
  38 #define MV64XXX_I2C_REG_CONTROL_START                   BIT(5)
  39 #define MV64XXX_I2C_REG_CONTROL_TWSIEN                  BIT(6)
  40 #define MV64XXX_I2C_REG_CONTROL_INTEN                   BIT(7)
  41
  42 /* Ctlr status values */
  43 #define MV64XXX_I2C_STATUS_BUS_ERR                      0x00
  44 #define MV64XXX_I2C_STATUS_MAST_START                   0x08
  45 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START            0x10
  46 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK             0x18
  47 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK          0x20
  48 #define MV64XXX_I2C_STATUS_MAST_WR_ACK                  0x28
  49 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK               0x30
  50 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB                0x38
  51 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK             0x40
  52 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK          0x48
  53 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK             0x50
  54 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK          0x58
  55 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK           0xd0
  56 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK        0xd8
  57 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK           0xe0
  58 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK        0xe8
  59 #define MV64XXX_I2C_STATUS_NO_STATUS                    0xf8
  60
  61 /* Register defines (I2C bridge) */
  62 #define MV64XXX_I2C_REG_TX_DATA_LO                      0xc0
  63 #define MV64XXX_I2C_REG_TX_DATA_HI                      0xc4
  64 #define MV64XXX_I2C_REG_RX_DATA_LO                      0xc8
  65 #define MV64XXX_I2C_REG_RX_DATA_HI                      0xcc
  66 #define MV64XXX_I2C_REG_BRIDGE_CONTROL                  0xd0
  67 #define MV64XXX_I2C_REG_BRIDGE_STATUS                   0xd4
  68 #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE               0xd8
  69 #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK                0xdC
  70 #define MV64XXX_I2C_REG_BRIDGE_TIMING                   0xe0
  71
  72 /* Bridge Control values */
  73 #define MV64XXX_I2C_BRIDGE_CONTROL_WR                   BIT(0)
  74 #define MV64XXX_I2C_BRIDGE_CONTROL_RD                   BIT(1)
  75 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT           2
  76 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT             BIT(12)
  77 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT        13
  78 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT        16
  79 #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE               BIT(19)
  80 #define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START       BIT(20)
  81
  82 /* Bridge Status values */
  83 #define MV64XXX_I2C_BRIDGE_STATUS_ERROR                 BIT(0)
  84
  85 /* Driver states */
  86 enum {
  87         MV64XXX_I2C_STATE_INVALID,
  88         MV64XXX_I2C_STATE_IDLE,
  89         MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
  90         MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
  91         MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
  92         MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
  93         MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
  94         MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
  95 };
  96
  97 /* Driver actions */
  98 enum {
  99         MV64XXX_I2C_ACTION_INVALID,
 100         MV64XXX_I2C_ACTION_CONTINUE,
 101         MV64XXX_I2C_ACTION_SEND_RESTART,
 102         MV64XXX_I2C_ACTION_SEND_ADDR_1,
 103         MV64XXX_I2C_ACTION_SEND_ADDR_2,
 104         MV64XXX_I2C_ACTION_SEND_DATA,
 105         MV64XXX_I2C_ACTION_RCV_DATA,
 106         MV64XXX_I2C_ACTION_RCV_DATA_STOP,
 107         MV64XXX_I2C_ACTION_SEND_STOP,
 108 };
 109
 110 struct mv64xxx_i2c_regs {
 111         u8      addr;
 112         u8      ext_addr;
 113         u8      data;
 114         u8      control;
 115         u8      status;
 116         u8      clock;
 117         u8      soft_reset;
 118 };
 119
 120 struct mv64xxx_i2c_data {
 121         struct i2c_msg          *msgs;
 122         int                     num_msgs;
 123         int                     irq;
 124         u32                     state;
 125         u32                     action;
 126         u32                     aborting;
 127         u32                     cntl_bits;
 128         void __iomem            *reg_base;
 129         struct mv64xxx_i2c_regs reg_offsets;
 130         u32                     addr1;
 131         u32                     addr2;
 132         u32                     bytes_left;
 133         u32                     byte_posn;
 134         u32                     send_stop;
 135         u32                     block;
 136         int                     rc;
 137         u32                     freq_m;
 138         u32                     freq_n;
 139         struct clk              *clk;
 140         struct clk              *reg_clk;
 141         wait_queue_head_t       waitq;
 142         spinlock_t              lock;
 143         struct i2c_msg          *msg;
 144         struct i2c_adapter      adapter;
 145         bool                    offload_enabled;
 146 /* 5us delay in order to avoid repeated start timing violation */
 147         bool                    errata_delay;
 148         struct reset_control    *rstc;
 149         bool                    irq_clear_inverted;
 150         /* Clk div is 2 to the power n, not 2 to the power n + 1 */
 151         bool                    clk_n_base_0;
 152         struct i2c_bus_recovery_info    rinfo;
 153         bool                    atomic;
 154 };
 155
 156 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
 157         .addr           = 0x00,
 158         .ext_addr       = 0x10,
 159         .data           = 0x04,
 160         .control        = 0x08,
 161         .status         = 0x0c,
 162         .clock          = 0x0c,
 163         .soft_reset     = 0x1c,
 164 };
 165
 166 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
 167         .addr           = 0x00,
 168         .ext_addr       = 0x04,
 169         .data           = 0x08,
 170         .control        = 0x0c,
 171         .status         = 0x10,
 172         .clock          = 0x14,
 173         .soft_reset     = 0x18,
 174 };
 175
 176 static void
 177 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
 178         struct i2c_msg *msg)
 179 {
 180         u32     dir = 0;
 181
 182         drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
 183                               MV64XXX_I2C_REG_CONTROL_TWSIEN;
 184
 185         if (!drv_data->atomic)
 186                 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_INTEN;
 187
 188         if (msg->flags & I2C_M_RD)
 189                 dir = 1;
 190
 191         if (msg->flags & I2C_M_TEN) {
 192                 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
 193                 drv_data->addr2 = (u32)msg->addr & 0xff;
 194         } else {
 195                 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
 196                 drv_data->addr2 = 0;
 197         }
 198 }
 199
 200 /*
 201  *****************************************************************************
 202  *
 203  *      Finite State Machine & Interrupt Routines
 204  *
 205  *****************************************************************************
 206  */
 207
 208 /* Reset hardware and initialize FSM */
 209 static void
 210 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
 211 {
 212         if (drv_data->offload_enabled) {
 213                 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
 214                 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
 215                 writel(0, drv_data->reg_base +
 216                         MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
 217                 writel(0, drv_data->reg_base +
 218                         MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
 219         }
 220
 221         writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
 222         writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
 223                 drv_data->reg_base + drv_data->reg_offsets.clock);
 224         writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
 225         writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
 226         writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
 227                 drv_data->reg_base + drv_data->reg_offsets.control);
 228
 229         if (drv_data->errata_delay)
 230                 udelay(5);
 231
 232         drv_data->state = MV64XXX_I2C_STATE_IDLE;
 233 }
 234
 235 static void
 236 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
 237 {
 238         /*
 239          * If state is idle, then this is likely the remnants of an old
 240          * operation that driver has given up on or the user has killed.
 241          * If so, issue the stop condition and go to idle.
 242          */
 243         if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
 244                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 245                 return;
 246         }
 247
 248         /* The status from the ctlr [mostly] tells us what to do next */
 249         switch (status) {
 250         /* Start condition interrupt */
 251         case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
 252         case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
 253                 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
 254                 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
 255                 break;
 256
 257         /* Performing a write */
 258         case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
 259                 if (drv_data->msg->flags & I2C_M_TEN) {
 260                         drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
 261                         drv_data->state =
 262                                 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
 263                         break;
 264                 }
 265                 fallthrough;
 266         case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
 267         case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
 268                 if ((drv_data->bytes_left == 0)
 269                                 || (drv_data->aborting
 270                                         && (drv_data->byte_posn != 0))) {
 271                         if (drv_data->send_stop || drv_data->aborting) {
 272                                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 273                                 drv_data->state = MV64XXX_I2C_STATE_IDLE;
 274                         } else {
 275                                 drv_data->action =
 276                                         MV64XXX_I2C_ACTION_SEND_RESTART;
 277                                 drv_data->state =
 278                                         MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
 279                         }
 280                 } else {
 281                         drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
 282                         drv_data->state =
 283                                 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
 284                         drv_data->bytes_left--;
 285                 }
 286                 break;
 287
 288         /* Performing a read */
 289         case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
 290                 if (drv_data->msg->flags & I2C_M_TEN) {
 291                         drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
 292                         drv_data->state =
 293                                 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
 294                         break;
 295                 }
 296                 fallthrough;
 297         case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
 298                 if (drv_data->bytes_left == 0) {
 299                         drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 300                         drv_data->state = MV64XXX_I2C_STATE_IDLE;
 301                         break;
 302                 }
 303                 fallthrough;
 304         case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
 305                 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
 306                         drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
 307                 else {
 308                         drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
 309                         drv_data->bytes_left--;
 310                 }
 311                 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
 312
 313                 if ((drv_data->bytes_left == 1) || drv_data->aborting)
 314                         drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
 315                 break;
 316
 317         case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
 318                 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
 319                 drv_data->state = MV64XXX_I2C_STATE_IDLE;
 320                 break;
 321
 322         case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
 323         case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
 324         case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
 325                 /* Doesn't seem to be a device at other end */
 326                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 327                 drv_data->state = MV64XXX_I2C_STATE_IDLE;
 328                 drv_data->rc = -ENXIO;
 329                 break;
 330
 331         default:
 332                 dev_err(&drv_data->adapter.dev,
 333                         "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
 334                         "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
 335                          drv_data->state, status, drv_data->msg->addr,
 336                          drv_data->msg->flags);
 337                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 338                 mv64xxx_i2c_hw_init(drv_data);
 339                 i2c_recover_bus(&drv_data->adapter);
 340                 drv_data->rc = -EAGAIN;
 341         }
 342 }
 343
 344 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
 345 {
 346         drv_data->msg = drv_data->msgs;
 347         drv_data->byte_posn = 0;
 348         drv_data->bytes_left = drv_data->msg->len;
 349         drv_data->aborting = 0;
 350         drv_data->rc = 0;
 351
 352         mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
 353         writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
 354                drv_data->reg_base + drv_data->reg_offsets.control);
 355 }
 356
 357 static void
 358 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
 359 {
 360         switch(drv_data->action) {
 361         case MV64XXX_I2C_ACTION_SEND_RESTART:
 362                 /* We should only get here if we have further messages */
 363                 BUG_ON(drv_data->num_msgs == 0);
 364
 365                 drv_data->msgs++;
 366                 drv_data->num_msgs--;
 367                 mv64xxx_i2c_send_start(drv_data);
 368
 369                 if (drv_data->errata_delay)
 370                         udelay(5);
 371
 372                 /*
 373                  * We're never at the start of the message here, and by this
 374                  * time it's already too late to do any protocol mangling.
 375                  * Thankfully, do not advertise support for that feature.
 376                  */
 377                 drv_data->send_stop = drv_data->num_msgs == 1;
 378                 break;
 379
 380         case MV64XXX_I2C_ACTION_CONTINUE:
 381                 writel(drv_data->cntl_bits,
 382                         drv_data->reg_base + drv_data->reg_offsets.control);
 383                 break;
 384
 385         case MV64XXX_I2C_ACTION_SEND_ADDR_1:
 386                 writel(drv_data->addr1,
 387                         drv_data->reg_base + drv_data->reg_offsets.data);
 388                 writel(drv_data->cntl_bits,
 389                         drv_data->reg_base + drv_data->reg_offsets.control);
 390                 break;
 391
 392         case MV64XXX_I2C_ACTION_SEND_ADDR_2:
 393                 writel(drv_data->addr2,
 394                         drv_data->reg_base + drv_data->reg_offsets.data);
 395                 writel(drv_data->cntl_bits,
 396                         drv_data->reg_base + drv_data->reg_offsets.control);
 397                 break;
 398
 399         case MV64XXX_I2C_ACTION_SEND_DATA:
 400                 writel(drv_data->msg->buf[drv_data->byte_posn++],
 401                         drv_data->reg_base + drv_data->reg_offsets.data);
 402                 writel(drv_data->cntl_bits,
 403                         drv_data->reg_base + drv_data->reg_offsets.control);
 404                 break;
 405
 406         case MV64XXX_I2C_ACTION_RCV_DATA:
 407                 drv_data->msg->buf[drv_data->byte_posn++] =
 408                         readl(drv_data->reg_base + drv_data->reg_offsets.data);
 409                 writel(drv_data->cntl_bits,
 410                         drv_data->reg_base + drv_data->reg_offsets.control);
 411                 break;
 412
 413         case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
 414                 drv_data->msg->buf[drv_data->byte_posn++] =
 415                         readl(drv_data->reg_base + drv_data->reg_offsets.data);
 416                 if (!drv_data->atomic)
 417                         drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
 418                 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
 419                         drv_data->reg_base + drv_data->reg_offsets.control);
 420                 drv_data->block = 0;
 421                 if (drv_data->errata_delay)
 422                         udelay(5);
 423
 424                 wake_up(&drv_data->waitq);
 425                 break;
 426
 427         case MV64XXX_I2C_ACTION_INVALID:
 428         default:
 429                 dev_err(&drv_data->adapter.dev,
 430                         "mv64xxx_i2c_do_action: Invalid action: %d\n",
 431                         drv_data->action);
 432                 drv_data->rc = -EIO;
 433                 fallthrough;
 434         case MV64XXX_I2C_ACTION_SEND_STOP:
 435                 if (!drv_data->atomic)
 436                         drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
 437                 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
 438                         drv_data->reg_base + drv_data->reg_offsets.control);
 439                 drv_data->block = 0;
 440                 wake_up(&drv_data->waitq);
 441                 break;
 442         }
 443 }
 444
 445 static void
 446 mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
 447                                  struct i2c_msg *msg)
 448 {
 449         u32 buf[2];
 450
 451         buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
 452         buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
 453
 454         memcpy(msg->buf, buf, msg->len);
 455 }
 456
 457 static int
 458 mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
 459 {
 460         u32 cause, status;
 461
 462         cause = readl(drv_data->reg_base +
 463                       MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
 464         if (!cause)
 465                 return IRQ_NONE;
 466
 467         status = readl(drv_data->reg_base +
 468                        MV64XXX_I2C_REG_BRIDGE_STATUS);
 469
 470         if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) {
 471                 drv_data->rc = -EIO;
 472                 goto out;
 473         }
 474
 475         drv_data->rc = 0;
 476
 477         /*
 478          * Transaction is a one message read transaction, read data
 479          * for this message.
 480          */
 481         if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
 482                 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
 483                 drv_data->msgs++;
 484                 drv_data->num_msgs--;
 485         }
 486         /*
 487          * Transaction is a two messages write/read transaction, read
 488          * data for the second (read) message.
 489          */
 490         else if (drv_data->num_msgs == 2 &&
 491                  !(drv_data->msgs[0].flags & I2C_M_RD) &&
 492                  drv_data->msgs[1].flags & I2C_M_RD) {
 493                 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
 494                 drv_data->msgs += 2;
 495                 drv_data->num_msgs -= 2;
 496         }
 497
 498 out:
 499         writel(0, drv_data->reg_base +  MV64XXX_I2C_REG_BRIDGE_CONTROL);
 500         writel(0, drv_data->reg_base +
 501                MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
 502         drv_data->block = 0;
 503
 504         wake_up(&drv_data->waitq);
 505
 506         return IRQ_HANDLED;
 507 }
 508
 509 static irqreturn_t
 510 mv64xxx_i2c_intr(int irq, void *dev_id)
 511 {
 512         struct mv64xxx_i2c_data *drv_data = dev_id;
 513         u32             status;
 514         irqreturn_t     rc = IRQ_NONE;
 515
 516         spin_lock(&drv_data->lock);
 517
 518         if (drv_data->offload_enabled)
 519                 rc = mv64xxx_i2c_intr_offload(drv_data);
 520
 521         while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
 522                                                 MV64XXX_I2C_REG_CONTROL_IFLG) {
 523                 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
 524                 mv64xxx_i2c_fsm(drv_data, status);
 525                 mv64xxx_i2c_do_action(drv_data);
 526
 527                 if (drv_data->irq_clear_inverted)
 528                         writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
 529                                drv_data->reg_base + drv_data->reg_offsets.control);
 530
 531                 rc = IRQ_HANDLED;
 532         }
 533         spin_unlock(&drv_data->lock);
 534
 535         return rc;
 536 }
 537
 538 /*
 539  *****************************************************************************
 540  *
 541  *      I2C Msg Execution Routines
 542  *
 543  *****************************************************************************
 544  */
 545 static void
 546 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
 547 {
 548         long            time_left;
 549         unsigned long   flags;
 550         char            abort = 0;
 551
 552         time_left = wait_event_timeout(drv_data->waitq,
 553                 !drv_data->block, drv_data->adapter.timeout);
 554
 555         spin_lock_irqsave(&drv_data->lock, flags);
 556         if (!time_left) { /* Timed out */
 557                 drv_data->rc = -ETIMEDOUT;
 558                 abort = 1;
 559         } else if (time_left < 0) { /* Interrupted/Error */
 560                 drv_data->rc = time_left; /* errno value */
 561                 abort = 1;
 562         }
 563
 564         if (abort && drv_data->block) {
 565                 drv_data->aborting = 1;
 566                 spin_unlock_irqrestore(&drv_data->lock, flags);
 567
 568                 time_left = wait_event_timeout(drv_data->waitq,
 569                         !drv_data->block, drv_data->adapter.timeout);
 570
 571                 if ((time_left <= 0) && drv_data->block) {
 572                         drv_data->state = MV64XXX_I2C_STATE_IDLE;
 573                         dev_err(&drv_data->adapter.dev,
 574                                 "mv64xxx: I2C bus locked, block: %d, "
 575                                 "time_left: %d\n", drv_data->block,
 576                                 (int)time_left);
 577                         mv64xxx_i2c_hw_init(drv_data);
 578                         i2c_recover_bus(&drv_data->adapter);
 579                 }
 580         } else
 581                 spin_unlock_irqrestore(&drv_data->lock, flags);
 582 }
 583
 584 static void mv64xxx_i2c_wait_polling(struct mv64xxx_i2c_data *drv_data)
 585 {
 586         ktime_t timeout = ktime_add_ms(ktime_get(), drv_data->adapter.timeout);
 587
 588         while (READ_ONCE(drv_data->block) &&
 589                ktime_compare(ktime_get(), timeout) < 0) {
 590                 udelay(5);
 591                 mv64xxx_i2c_intr(0, drv_data);
 592         }
 593 }
 594
 595 static int
 596 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
 597                                 int is_last)
 598 {
 599         unsigned long   flags;
 600
 601         spin_lock_irqsave(&drv_data->lock, flags);
 602
 603         drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
 604
 605         drv_data->send_stop = is_last;
 606         drv_data->block = 1;
 607         mv64xxx_i2c_send_start(drv_data);
 608         spin_unlock_irqrestore(&drv_data->lock, flags);
 609
 610         if (!drv_data->atomic)
 611                 mv64xxx_i2c_wait_for_completion(drv_data);
 612         else
 613                 mv64xxx_i2c_wait_polling(drv_data);
 614
 615         return drv_data->rc;
 616 }
 617
 618 static void
 619 mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
 620 {
 621         struct i2c_msg *msg = drv_data->msgs;
 622         u32 buf[2];
 623
 624         memcpy(buf, msg->buf, msg->len);
 625
 626         writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
 627         writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
 628 }
 629
 630 static int
 631 mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
 632 {
 633         struct i2c_msg *msgs = drv_data->msgs;
 634         int num = drv_data->num_msgs;
 635         unsigned long ctrl_reg;
 636         unsigned long flags;
 637
 638         spin_lock_irqsave(&drv_data->lock, flags);
 639
 640         /* Build transaction */
 641         ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
 642                 (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
 643
 644         if (msgs[0].flags & I2C_M_TEN)
 645                 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
 646
 647         /* Single write message transaction */
 648         if (num == 1 && !(msgs[0].flags & I2C_M_RD)) {
 649                 size_t len = msgs[0].len - 1;
 650
 651                 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
 652                         (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT);
 653                 mv64xxx_i2c_prepare_tx(drv_data);
 654         }
 655         /* Single read message transaction */
 656         else if (num == 1 && msgs[0].flags & I2C_M_RD) {
 657                 size_t len = msgs[0].len - 1;
 658
 659                 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
 660                         (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT);
 661         }
 662         /*
 663          * Transaction with one write and one read message. This is
 664          * guaranteed by the mv64xx_i2c_can_offload() checks.
 665          */
 666         else if (num == 2) {
 667                 size_t lentx = msgs[0].len - 1;
 668                 size_t lenrx = msgs[1].len - 1;
 669
 670                 ctrl_reg |=
 671                         MV64XXX_I2C_BRIDGE_CONTROL_RD |
 672                         MV64XXX_I2C_BRIDGE_CONTROL_WR |
 673                         (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) |
 674                         (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) |
 675                         MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START;
 676                 mv64xxx_i2c_prepare_tx(drv_data);
 677         }
 678
 679         /* Execute transaction */
 680         drv_data->block = 1;
 681         writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
 682         spin_unlock_irqrestore(&drv_data->lock, flags);
 683
 684         mv64xxx_i2c_wait_for_completion(drv_data);
 685
 686         return drv_data->rc;
 687 }
 688
 689 static bool
 690 mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg)
 691 {
 692         return msg->len <= 8 && msg->len >= 1;
 693 }
 694
 695 static bool
 696 mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
 697 {
 698         struct i2c_msg *msgs = drv_data->msgs;
 699         int num = drv_data->num_msgs;
 700
 701         if (!drv_data->offload_enabled)
 702                 return false;
 703
 704         /*
 705          * We can offload a transaction consisting of a single
 706          * message, as long as the message has a length between 1 and
 707          * 8 bytes.
 708          */
 709         if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs))
 710                 return true;
 711
 712         /*
 713          * We can offload a transaction consisting of two messages, if
 714          * the first is a write and a second is a read, and both have
 715          * a length between 1 and 8 bytes.
 716          */
 717         if (num == 2 &&
 718             mv64xxx_i2c_valid_offload_sz(msgs) &&
 719             mv64xxx_i2c_valid_offload_sz(msgs + 1) &&
 720             !(msgs[0].flags & I2C_M_RD) &&
 721             msgs[1].flags & I2C_M_RD)
 722                 return true;
 723
 724         return false;
 725 }
 726
 727 /*
 728  *****************************************************************************
 729  *
 730  *      I2C Core Support Routines (Interface to higher level I2C code)
 731  *
 732  *****************************************************************************
 733  */
 734 static u32
 735 mv64xxx_i2c_functionality(struct i2c_adapter *adap)
 736 {
 737         return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
 738 }
 739
 740 static int
 741 mv64xxx_i2c_xfer_core(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 742 {
 743         struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
 744         int rc, ret = num;
 745
 746         rc = pm_runtime_resume_and_get(&adap->dev);
 747         if (rc)
 748                 return rc;
 749
 750         BUG_ON(drv_data->msgs != NULL);
 751         drv_data->msgs = msgs;
 752         drv_data->num_msgs = num;
 753
 754         if (mv64xxx_i2c_can_offload(drv_data) && !drv_data->atomic)
 755                 rc = mv64xxx_i2c_offload_xfer(drv_data);
 756         else
 757                 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
 758
 759         if (rc < 0)
 760                 ret = rc;
 761
 762         drv_data->num_msgs = 0;
 763         drv_data->msgs = NULL;
 764
 765         pm_runtime_mark_last_busy(&adap->dev);
 766         pm_runtime_put_autosuspend(&adap->dev);
 767
 768         return ret;
 769 }
 770
 771 static int
 772 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 773 {
 774         struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
 775
 776         drv_data->atomic = 0;
 777         return mv64xxx_i2c_xfer_core(adap, msgs, num);
 778 }
 779
 780 static int mv64xxx_i2c_xfer_atomic(struct i2c_adapter *adap,
 781                                    struct i2c_msg msgs[], int num)
 782 {
 783         struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
 784
 785         drv_data->atomic = 1;
 786         return mv64xxx_i2c_xfer_core(adap, msgs, num);
 787 }
 788
 789 static const struct i2c_algorithm mv64xxx_i2c_algo = {
 790         .master_xfer = mv64xxx_i2c_xfer,
 791         .master_xfer_atomic = mv64xxx_i2c_xfer_atomic,
 792         .functionality = mv64xxx_i2c_functionality,
 793 };
 794
 795 /*
 796  *****************************************************************************
 797  *
 798  *      Driver Interface & Early Init Routines
 799  *
 800  *****************************************************************************
 801  */
 802 static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
 803         { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i},
 804         { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i},
 805         { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
 806         { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
 807         { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
 808         {}
 809 };
 810 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
 811
 812 #ifdef CONFIG_OF
 813 static int
 814 mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
 815                   const int tclk, const int n, const int m)
 816 {
 817         if (drv_data->clk_n_base_0)
 818                 return tclk / (10 * (m + 1) * (1 << n));
 819         else
 820                 return tclk / (10 * (m + 1) * (2 << n));
 821 }
 822
 823 static bool
 824 mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
 825                           const u32 req_freq, const u32 tclk)
 826 {
 827         int freq, delta, best_delta = INT_MAX;
 828         int m, n;
 829
 830         for (n = 0; n <= 7; n++)
 831                 for (m = 0; m <= 15; m++) {
 832                         freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
 833                         delta = req_freq - freq;
 834                         if (delta >= 0 && delta < best_delta) {
 835                                 drv_data->freq_m = m;
 836                                 drv_data->freq_n = n;
 837                                 best_delta = delta;
 838                         }
 839                         if (best_delta == 0)
 840                                 return true;
 841                 }
 842         if (best_delta == INT_MAX)
 843                 return false;
 844         return true;
 845 }
 846
 847 static int
 848 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
 849                   struct device *dev)
 850 {
 851         const struct of_device_id *device;
 852         struct device_node *np = dev->of_node;
 853         u32 bus_freq, tclk;
 854         int rc = 0;
 855
 856         /* CLK is mandatory when using DT to describe the i2c bus. We
 857          * need to know tclk in order to calculate bus clock
 858          * factors.
 859          */
 860         if (!drv_data->clk) {
 861                 rc = -ENODEV;
 862                 goto out;
 863         }
 864         tclk = clk_get_rate(drv_data->clk);
 865
 866         if (of_property_read_u32(np, "clock-frequency", &bus_freq))
 867                 bus_freq = I2C_MAX_STANDARD_MODE_FREQ; /* 100kHz by default */
 868
 869         if (of_device_is_compatible(np, "allwinner,sun4i-a10-i2c") ||
 870             of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
 871                 drv_data->clk_n_base_0 = true;
 872
 873         if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
 874                 rc = -EINVAL;
 875                 goto out;
 876         }
 877
 878         drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
 879         if (IS_ERR(drv_data->rstc)) {
 880                 rc = PTR_ERR(drv_data->rstc);
 881                 goto out;
 882         }
 883
 884         /* Its not yet defined how timeouts will be specified in device tree.
 885          * So hard code the value to 1 second.
 886          */
 887         drv_data->adapter.timeout = HZ;
 888
 889         device = of_match_device(mv64xxx_i2c_of_match_table, dev);
 890         if (!device)
 891                 return -ENODEV;
 892
 893         memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
 894
 895         /*
 896          * For controllers embedded in new SoCs activate the
 897          * Transaction Generator support and the errata fix.
 898          */
 899         if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
 900                 drv_data->offload_enabled = true;
 901                 /* The delay is only needed in standard mode (100kHz) */
 902                 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
 903                         drv_data->errata_delay = true;
 904         }
 905
 906         if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
 907                 drv_data->offload_enabled = false;
 908                 /* The delay is only needed in standard mode (100kHz) */
 909                 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
 910                         drv_data->errata_delay = true;
 911         }
 912
 913         if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
 914                 drv_data->irq_clear_inverted = true;
 915
 916 out:
 917         return rc;
 918 }
 919 #else /* CONFIG_OF */
 920 static int
 921 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
 922                   struct device *dev)
 923 {
 924         return -ENODEV;
 925 }
 926 #endif /* CONFIG_OF */
 927
 928 static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data,
 929                                           struct device *dev)
 930 {
 931         struct i2c_bus_recovery_info *rinfo = &drv_data->rinfo;
 932
 933         rinfo->pinctrl = devm_pinctrl_get(dev);
 934         if (IS_ERR(rinfo->pinctrl)) {
 935                 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER)
 936                         return -EPROBE_DEFER;
 937                 dev_info(dev, "can't get pinctrl, bus recovery not supported\n");
 938                 return PTR_ERR(rinfo->pinctrl);
 939         } else if (!rinfo->pinctrl) {
 940                 return -ENODEV;
 941         }
 942
 943         drv_data->adapter.bus_recovery_info = rinfo;
 944         return 0;
 945 }
 946
 947 static int
 948 mv64xxx_i2c_runtime_suspend(struct device *dev)
 949 {
 950         struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
 951
 952         reset_control_assert(drv_data->rstc);
 953         clk_disable_unprepare(drv_data->reg_clk);
 954         clk_disable_unprepare(drv_data->clk);
 955
 956         return 0;
 957 }
 958
 959 static int
 960 mv64xxx_i2c_runtime_resume(struct device *dev)
 961 {
 962         struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
 963
 964         clk_prepare_enable(drv_data->clk);
 965         clk_prepare_enable(drv_data->reg_clk);
 966         reset_control_reset(drv_data->rstc);
 967
 968         mv64xxx_i2c_hw_init(drv_data);
 969
 970         return 0;
 971 }
 972
 973 static int
 974 mv64xxx_i2c_probe(struct platform_device *pd)
 975 {
 976         struct mv64xxx_i2c_data         *drv_data;
 977         struct mv64xxx_i2c_pdata        *pdata = dev_get_platdata(&pd->dev);
 978         int     rc;
 979
 980         if ((!pdata && !pd->dev.of_node))
 981                 return -ENODEV;
 982
 983         drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
 984                                 GFP_KERNEL);
 985         if (!drv_data)
 986                 return -ENOMEM;
 987
 988         drv_data->reg_base = devm_platform_ioremap_resource(pd, 0);
 989         if (IS_ERR(drv_data->reg_base))
 990                 return PTR_ERR(drv_data->reg_base);
 991
 992         strscpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
 993                 sizeof(drv_data->adapter.name));
 994
 995         init_waitqueue_head(&drv_data->waitq);
 996         spin_lock_init(&drv_data->lock);
 997
 998         /* Not all platforms have clocks */
 999         drv_data->clk = devm_clk_get(&pd->dev, NULL);
1000         if (IS_ERR(drv_data->clk)) {
1001                 if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
1002                         return -EPROBE_DEFER;
1003                 drv_data->clk = NULL;
1004         }
1005
1006         drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
1007         if (IS_ERR(drv_data->reg_clk)) {
1008                 if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
1009                         return -EPROBE_DEFER;
1010                 drv_data->reg_clk = NULL;
1011         }
1012
1013         drv_data->irq = platform_get_irq(pd, 0);
1014         if (drv_data->irq < 0)
1015                 return drv_data->irq;
1016
1017         if (pdata) {
1018                 drv_data->freq_m = pdata->freq_m;
1019                 drv_data->freq_n = pdata->freq_n;
1020                 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
1021                 drv_data->offload_enabled = false;
1022                 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
1023         } else if (pd->dev.of_node) {
1024                 rc = mv64xxx_of_config(drv_data, &pd->dev);
1025                 if (rc)
1026                         return rc;
1027         }
1028
1029         rc = mv64xxx_i2c_init_recovery_info(drv_data, &pd->dev);
1030         if (rc == -EPROBE_DEFER)
1031                 return rc;
1032
1033         drv_data->adapter.dev.parent = &pd->dev;
1034         drv_data->adapter.algo = &mv64xxx_i2c_algo;
1035         drv_data->adapter.owner = THIS_MODULE;
1036         drv_data->adapter.class = I2C_CLASS_DEPRECATED;
1037         drv_data->adapter.nr = pd->id;
1038         drv_data->adapter.dev.of_node = pd->dev.of_node;
1039         platform_set_drvdata(pd, drv_data);
1040         i2c_set_adapdata(&drv_data->adapter, drv_data);
1041
1042         pm_runtime_set_autosuspend_delay(&pd->dev, MSEC_PER_SEC);
1043         pm_runtime_use_autosuspend(&pd->dev);
1044         pm_runtime_enable(&pd->dev);
1045         if (!pm_runtime_enabled(&pd->dev)) {
1046                 rc = mv64xxx_i2c_runtime_resume(&pd->dev);
1047                 if (rc)
1048                         goto exit_disable_pm;
1049         }
1050
1051         rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
1052                          MV64XXX_I2C_CTLR_NAME, drv_data);
1053         if (rc) {
1054                 dev_err(&drv_data->adapter.dev,
1055                         "mv64xxx: Can't register intr handler irq%d: %d\n",
1056                         drv_data->irq, rc);
1057                 goto exit_disable_pm;
1058         } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
1059                 dev_err(&drv_data->adapter.dev,
1060                         "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
1061                 goto exit_free_irq;
1062         }
1063
1064         return 0;
1065
1066 exit_free_irq:
1067         free_irq(drv_data->irq, drv_data);
1068 exit_disable_pm:
1069         pm_runtime_disable(&pd->dev);
1070         if (!pm_runtime_status_suspended(&pd->dev))
1071                 mv64xxx_i2c_runtime_suspend(&pd->dev);
1072
1073         return rc;
1074 }
1075
1076 static int
1077 mv64xxx_i2c_remove(struct platform_device *pd)
1078 {
1079         struct mv64xxx_i2c_data         *drv_data = platform_get_drvdata(pd);
1080
1081         i2c_del_adapter(&drv_data->adapter);
1082         free_irq(drv_data->irq, drv_data);
1083         pm_runtime_disable(&pd->dev);
1084         if (!pm_runtime_status_suspended(&pd->dev))
1085                 mv64xxx_i2c_runtime_suspend(&pd->dev);
1086
1087         return 0;
1088 }
1089
1090 static const struct dev_pm_ops mv64xxx_i2c_pm_ops = {
1091         SET_RUNTIME_PM_OPS(mv64xxx_i2c_runtime_suspend,
1092                            mv64xxx_i2c_runtime_resume, NULL)
1093         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1094                                       pm_runtime_force_resume)
1095 };
1096
1097 static struct platform_driver mv64xxx_i2c_driver = {
1098         .probe  = mv64xxx_i2c_probe,
1099         .remove = mv64xxx_i2c_remove,
1100         .driver = {
1101                 .name   = MV64XXX_I2C_CTLR_NAME,
1102                 .pm     = &mv64xxx_i2c_pm_ops,
1103                 .of_match_table = mv64xxx_i2c_of_match_table,
1104         },
1105 };
1106
1107 module_platform_driver(mv64xxx_i2c_driver);
1108
1109 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
1110 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
1111 MODULE_LICENSE("GPL");