drivers/i2c/busses/i2c-mt65xx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Xudong Chen <xudong.chen@mediatek.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/completion.h>
   9 #include <linux/delay.h>
  10 #include <linux/device.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/err.h>
  13 #include <linux/errno.h>
  14 #include <linux/i2c.h>
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/iopoll.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/module.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/scatterlist.h>
  27 #include <linux/sched.h>
  28 #include <linux/slab.h>
  29
  30 #define I2C_RS_TRANSFER                 (1 << 4)
  31 #define I2C_ARB_LOST                    (1 << 3)
  32 #define I2C_HS_NACKERR                  (1 << 2)
  33 #define I2C_ACKERR                      (1 << 1)
  34 #define I2C_TRANSAC_COMP                (1 << 0)
  35 #define I2C_TRANSAC_START               (1 << 0)
  36 #define I2C_RS_MUL_CNFG                 (1 << 15)
  37 #define I2C_RS_MUL_TRIG                 (1 << 14)
  38 #define I2C_DCM_DISABLE                 0x0000
  39 #define I2C_IO_CONFIG_OPEN_DRAIN        0x0003
  40 #define I2C_IO_CONFIG_PUSH_PULL         0x0000
  41 #define I2C_SOFT_RST                    0x0001
  42 #define I2C_HANDSHAKE_RST               0x0020
  43 #define I2C_FIFO_ADDR_CLR               0x0001
  44 #define I2C_DELAY_LEN                   0x0002
  45 #define I2C_ST_START_CON                0x8001
  46 #define I2C_FS_START_CON                0x1800
  47 #define I2C_TIME_CLR_VALUE              0x0000
  48 #define I2C_TIME_DEFAULT_VALUE          0x0003
  49 #define I2C_WRRD_TRANAC_VALUE           0x0002
  50 #define I2C_RD_TRANAC_VALUE             0x0001
  51 #define I2C_SCL_MIS_COMP_VALUE          0x0000
  52 #define I2C_CHN_CLR_FLAG                0x0000
  53 #define I2C_RELIABILITY         0x0010
  54 #define I2C_DMAACK_ENABLE               0x0008
  55
  56 #define I2C_DMA_CON_TX                  0x0000
  57 #define I2C_DMA_CON_RX                  0x0001
  58 #define I2C_DMA_ASYNC_MODE              0x0004
  59 #define I2C_DMA_SKIP_CONFIG             0x0010
  60 #define I2C_DMA_DIR_CHANGE              0x0200
  61 #define I2C_DMA_START_EN                0x0001
  62 #define I2C_DMA_INT_FLAG_NONE           0x0000
  63 #define I2C_DMA_CLR_FLAG                0x0000
  64 #define I2C_DMA_WARM_RST                0x0001
  65 #define I2C_DMA_HARD_RST                0x0002
  66 #define I2C_DMA_HANDSHAKE_RST           0x0004
  67
  68 #define MAX_SAMPLE_CNT_DIV              8
  69 #define MAX_STEP_CNT_DIV                64
  70 #define MAX_CLOCK_DIV_8BITS             256
  71 #define MAX_CLOCK_DIV_5BITS             32
  72 #define MAX_HS_STEP_CNT_DIV             8
  73 #define I2C_STANDARD_MODE_BUFFER        (1000 / 3)
  74 #define I2C_FAST_MODE_BUFFER            (300 / 3)
  75 #define I2C_FAST_MODE_PLUS_BUFFER       (20 / 3)
  76
  77 #define I2C_CONTROL_RS                  (0x1 << 1)
  78 #define I2C_CONTROL_DMA_EN              (0x1 << 2)
  79 #define I2C_CONTROL_CLK_EXT_EN          (0x1 << 3)
  80 #define I2C_CONTROL_DIR_CHANGE          (0x1 << 4)
  81 #define I2C_CONTROL_ACKERR_DET_EN       (0x1 << 5)
  82 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
  83 #define I2C_CONTROL_DMAACK_EN           (0x1 << 8)
  84 #define I2C_CONTROL_ASYNC_MODE          (0x1 << 9)
  85 #define I2C_CONTROL_WRAPPER             (0x1 << 0)
  86
  87 #define I2C_DRV_NAME            "i2c-mt65xx"
  88
  89 /**
  90  * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C
  91  *
  92  * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus
  93  * @I2C_MT65XX_CLK_DMA:  DMA clock for i2c via DMA
  94  * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC
  95  * @I2C_MT65XX_CLK_ARB:  Arbitrator clock for i2c
  96  * @I2C_MT65XX_CLK_MAX:  Number of supported clocks
  97  */
  98 enum i2c_mt65xx_clks {
  99         I2C_MT65XX_CLK_MAIN = 0,
 100         I2C_MT65XX_CLK_DMA,
 101         I2C_MT65XX_CLK_PMIC,
 102         I2C_MT65XX_CLK_ARB,
 103         I2C_MT65XX_CLK_MAX
 104 };
 105
 106 static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = {
 107         "main", "dma", "pmic", "arb"
 108 };
 109
 110 enum DMA_REGS_OFFSET {
 111         OFFSET_INT_FLAG = 0x0,
 112         OFFSET_INT_EN = 0x04,
 113         OFFSET_EN = 0x08,
 114         OFFSET_RST = 0x0c,
 115         OFFSET_CON = 0x18,
 116         OFFSET_TX_MEM_ADDR = 0x1c,
 117         OFFSET_RX_MEM_ADDR = 0x20,
 118         OFFSET_TX_LEN = 0x24,
 119         OFFSET_RX_LEN = 0x28,
 120         OFFSET_TX_4G_MODE = 0x54,
 121         OFFSET_RX_4G_MODE = 0x58,
 122 };
 123
 124 enum i2c_trans_st_rs {
 125         I2C_TRANS_STOP = 0,
 126         I2C_TRANS_REPEATED_START,
 127 };
 128
 129 enum mtk_trans_op {
 130         I2C_MASTER_WR = 1,
 131         I2C_MASTER_RD,
 132         I2C_MASTER_WRRD,
 133 };
 134
 135 enum I2C_REGS_OFFSET {
 136         OFFSET_DATA_PORT,
 137         OFFSET_SLAVE_ADDR,
 138         OFFSET_INTR_MASK,
 139         OFFSET_INTR_STAT,
 140         OFFSET_CONTROL,
 141         OFFSET_TRANSFER_LEN,
 142         OFFSET_TRANSAC_LEN,
 143         OFFSET_DELAY_LEN,
 144         OFFSET_TIMING,
 145         OFFSET_START,
 146         OFFSET_EXT_CONF,
 147         OFFSET_FIFO_STAT,
 148         OFFSET_FIFO_THRESH,
 149         OFFSET_FIFO_ADDR_CLR,
 150         OFFSET_IO_CONFIG,
 151         OFFSET_RSV_DEBUG,
 152         OFFSET_HS,
 153         OFFSET_SOFTRESET,
 154         OFFSET_DCM_EN,
 155         OFFSET_MULTI_DMA,
 156         OFFSET_PATH_DIR,
 157         OFFSET_DEBUGSTAT,
 158         OFFSET_DEBUGCTRL,
 159         OFFSET_TRANSFER_LEN_AUX,
 160         OFFSET_CLOCK_DIV,
 161         OFFSET_LTIMING,
 162         OFFSET_SCL_HIGH_LOW_RATIO,
 163         OFFSET_HS_SCL_HIGH_LOW_RATIO,
 164         OFFSET_SCL_MIS_COMP_POINT,
 165         OFFSET_STA_STO_AC_TIMING,
 166         OFFSET_HS_STA_STO_AC_TIMING,
 167         OFFSET_SDA_TIMING,
 168 };
 169
 170 static const u16 mt_i2c_regs_v1[] = {
 171         [OFFSET_DATA_PORT] = 0x0,
 172         [OFFSET_SLAVE_ADDR] = 0x4,
 173         [OFFSET_INTR_MASK] = 0x8,
 174         [OFFSET_INTR_STAT] = 0xc,
 175         [OFFSET_CONTROL] = 0x10,
 176         [OFFSET_TRANSFER_LEN] = 0x14,
 177         [OFFSET_TRANSAC_LEN] = 0x18,
 178         [OFFSET_DELAY_LEN] = 0x1c,
 179         [OFFSET_TIMING] = 0x20,
 180         [OFFSET_START] = 0x24,
 181         [OFFSET_EXT_CONF] = 0x28,
 182         [OFFSET_FIFO_STAT] = 0x30,
 183         [OFFSET_FIFO_THRESH] = 0x34,
 184         [OFFSET_FIFO_ADDR_CLR] = 0x38,
 185         [OFFSET_IO_CONFIG] = 0x40,
 186         [OFFSET_RSV_DEBUG] = 0x44,
 187         [OFFSET_HS] = 0x48,
 188         [OFFSET_SOFTRESET] = 0x50,
 189         [OFFSET_DCM_EN] = 0x54,
 190         [OFFSET_PATH_DIR] = 0x60,
 191         [OFFSET_DEBUGSTAT] = 0x64,
 192         [OFFSET_DEBUGCTRL] = 0x68,
 193         [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
 194         [OFFSET_CLOCK_DIV] = 0x70,
 195         [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74,
 196         [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78,
 197         [OFFSET_SCL_MIS_COMP_POINT] = 0x7C,
 198         [OFFSET_STA_STO_AC_TIMING] = 0x80,
 199         [OFFSET_HS_STA_STO_AC_TIMING] = 0x84,
 200         [OFFSET_SDA_TIMING] = 0x88,
 201 };
 202
 203 static const u16 mt_i2c_regs_v2[] = {
 204         [OFFSET_DATA_PORT] = 0x0,
 205         [OFFSET_SLAVE_ADDR] = 0x4,
 206         [OFFSET_INTR_MASK] = 0x8,
 207         [OFFSET_INTR_STAT] = 0xc,
 208         [OFFSET_CONTROL] = 0x10,
 209         [OFFSET_TRANSFER_LEN] = 0x14,
 210         [OFFSET_TRANSAC_LEN] = 0x18,
 211         [OFFSET_DELAY_LEN] = 0x1c,
 212         [OFFSET_TIMING] = 0x20,
 213         [OFFSET_START] = 0x24,
 214         [OFFSET_EXT_CONF] = 0x28,
 215         [OFFSET_LTIMING] = 0x2c,
 216         [OFFSET_HS] = 0x30,
 217         [OFFSET_IO_CONFIG] = 0x34,
 218         [OFFSET_FIFO_ADDR_CLR] = 0x38,
 219         [OFFSET_SDA_TIMING] = 0x3c,
 220         [OFFSET_TRANSFER_LEN_AUX] = 0x44,
 221         [OFFSET_CLOCK_DIV] = 0x48,
 222         [OFFSET_SOFTRESET] = 0x50,
 223         [OFFSET_MULTI_DMA] = 0x8c,
 224         [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
 225         [OFFSET_DEBUGSTAT] = 0xe4,
 226         [OFFSET_DEBUGCTRL] = 0xe8,
 227         [OFFSET_FIFO_STAT] = 0xf4,
 228         [OFFSET_FIFO_THRESH] = 0xf8,
 229         [OFFSET_DCM_EN] = 0xf88,
 230 };
 231
 232 static const u16 mt_i2c_regs_v3[] = {
 233         [OFFSET_DATA_PORT] = 0x0,
 234         [OFFSET_INTR_MASK] = 0x8,
 235         [OFFSET_INTR_STAT] = 0xc,
 236         [OFFSET_CONTROL] = 0x10,
 237         [OFFSET_TRANSFER_LEN] = 0x14,
 238         [OFFSET_TRANSAC_LEN] = 0x18,
 239         [OFFSET_DELAY_LEN] = 0x1c,
 240         [OFFSET_TIMING] = 0x20,
 241         [OFFSET_START] = 0x24,
 242         [OFFSET_EXT_CONF] = 0x28,
 243         [OFFSET_LTIMING] = 0x2c,
 244         [OFFSET_HS] = 0x30,
 245         [OFFSET_IO_CONFIG] = 0x34,
 246         [OFFSET_FIFO_ADDR_CLR] = 0x38,
 247         [OFFSET_SDA_TIMING] = 0x3c,
 248         [OFFSET_TRANSFER_LEN_AUX] = 0x44,
 249         [OFFSET_CLOCK_DIV] = 0x48,
 250         [OFFSET_SOFTRESET] = 0x50,
 251         [OFFSET_MULTI_DMA] = 0x8c,
 252         [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
 253         [OFFSET_SLAVE_ADDR] = 0x94,
 254         [OFFSET_DEBUGSTAT] = 0xe4,
 255         [OFFSET_DEBUGCTRL] = 0xe8,
 256         [OFFSET_FIFO_STAT] = 0xf4,
 257         [OFFSET_FIFO_THRESH] = 0xf8,
 258         [OFFSET_DCM_EN] = 0xf88,
 259 };
 260
 261 struct mtk_i2c_compatible {
 262         const struct i2c_adapter_quirks *quirks;
 263         const u16 *regs;
 264         unsigned char pmic_i2c: 1;
 265         unsigned char dcm: 1;
 266         unsigned char auto_restart: 1;
 267         unsigned char aux_len_reg: 1;
 268         unsigned char timing_adjust: 1;
 269         unsigned char dma_sync: 1;
 270         unsigned char ltiming_adjust: 1;
 271         unsigned char apdma_sync: 1;
 272         unsigned char max_dma_support;
 273 };
 274
 275 struct mtk_i2c_ac_timing {
 276         u16 htiming;
 277         u16 ltiming;
 278         u16 hs;
 279         u16 ext;
 280         u16 inter_clk_div;
 281         u16 scl_hl_ratio;
 282         u16 hs_scl_hl_ratio;
 283         u16 sta_stop;
 284         u16 hs_sta_stop;
 285         u16 sda_timing;
 286 };
 287
 288 struct mtk_i2c {
 289         struct i2c_adapter adap;        /* i2c host adapter */
 290         struct device *dev;
 291         struct completion msg_complete;
 292         struct i2c_timings timing_info;
 293
 294         /* set in i2c probe */
 295         void __iomem *base;             /* i2c base addr */
 296         void __iomem *pdmabase;         /* dma base address*/
 297         struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */
 298         bool have_pmic;                 /* can use i2c pins from PMIC */
 299         bool use_push_pull;             /* IO config push-pull mode */
 300
 301         u16 irq_stat;                   /* interrupt status */
 302         unsigned int clk_src_div;
 303         unsigned int speed_hz;          /* The speed in transfer */
 304         enum mtk_trans_op op;
 305         u16 timing_reg;
 306         u16 high_speed_reg;
 307         u16 ltiming_reg;
 308         unsigned char auto_restart;
 309         bool ignore_restart_irq;
 310         struct mtk_i2c_ac_timing ac_timing;
 311         const struct mtk_i2c_compatible *dev_comp;
 312 };
 313
 314 /**
 315  * struct i2c_spec_values:
 316  * @min_low_ns: min LOW period of the SCL clock
 317  * @min_su_sta_ns: min set-up time for a repeated START condition
 318  * @max_hd_dat_ns: max data hold time
 319  * @min_su_dat_ns: min data set-up time
 320  */
 321 struct i2c_spec_values {
 322         unsigned int min_low_ns;
 323         unsigned int min_su_sta_ns;
 324         unsigned int max_hd_dat_ns;
 325         unsigned int min_su_dat_ns;
 326 };
 327
 328 static const struct i2c_spec_values standard_mode_spec = {
 329         .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
 330         .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
 331         .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
 332         .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER,
 333 };
 334
 335 static const struct i2c_spec_values fast_mode_spec = {
 336         .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER,
 337         .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER,
 338         .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
 339         .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER,
 340 };
 341
 342 static const struct i2c_spec_values fast_mode_plus_spec = {
 343         .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER,
 344         .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER,
 345         .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
 346         .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER,
 347 };
 348
 349 static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
 350         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 351         .max_num_msgs = 1,
 352         .max_write_len = 255,
 353         .max_read_len = 255,
 354         .max_comb_1st_msg_len = 255,
 355         .max_comb_2nd_msg_len = 31,
 356 };
 357
 358 static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
 359         .max_num_msgs = 255,
 360 };
 361
 362 static const struct i2c_adapter_quirks mt8183_i2c_quirks = {
 363         .flags = I2C_AQ_NO_ZERO_LEN,
 364 };
 365
 366 static const struct mtk_i2c_compatible mt2712_compat = {
 367         .regs = mt_i2c_regs_v1,
 368         .pmic_i2c = 0,
 369         .dcm = 1,
 370         .auto_restart = 1,
 371         .aux_len_reg = 1,
 372         .timing_adjust = 1,
 373         .dma_sync = 0,
 374         .ltiming_adjust = 0,
 375         .apdma_sync = 0,
 376         .max_dma_support = 33,
 377 };
 378
 379 static const struct mtk_i2c_compatible mt6577_compat = {
 380         .quirks = &mt6577_i2c_quirks,
 381         .regs = mt_i2c_regs_v1,
 382         .pmic_i2c = 0,
 383         .dcm = 1,
 384         .auto_restart = 0,
 385         .aux_len_reg = 0,
 386         .timing_adjust = 0,
 387         .dma_sync = 0,
 388         .ltiming_adjust = 0,
 389         .apdma_sync = 0,
 390         .max_dma_support = 32,
 391 };
 392
 393 static const struct mtk_i2c_compatible mt6589_compat = {
 394         .quirks = &mt6577_i2c_quirks,
 395         .regs = mt_i2c_regs_v1,
 396         .pmic_i2c = 1,
 397         .dcm = 0,
 398         .auto_restart = 0,
 399         .aux_len_reg = 0,
 400         .timing_adjust = 0,
 401         .dma_sync = 0,
 402         .ltiming_adjust = 0,
 403         .apdma_sync = 0,
 404         .max_dma_support = 32,
 405 };
 406
 407 static const struct mtk_i2c_compatible mt7622_compat = {
 408         .quirks = &mt7622_i2c_quirks,
 409         .regs = mt_i2c_regs_v1,
 410         .pmic_i2c = 0,
 411         .dcm = 1,
 412         .auto_restart = 1,
 413         .aux_len_reg = 1,
 414         .timing_adjust = 0,
 415         .dma_sync = 0,
 416         .ltiming_adjust = 0,
 417         .apdma_sync = 0,
 418         .max_dma_support = 32,
 419 };
 420
 421 static const struct mtk_i2c_compatible mt8168_compat = {
 422         .regs = mt_i2c_regs_v1,
 423         .pmic_i2c = 0,
 424         .dcm = 1,
 425         .auto_restart = 1,
 426         .aux_len_reg = 1,
 427         .timing_adjust = 1,
 428         .dma_sync = 1,
 429         .ltiming_adjust = 0,
 430         .apdma_sync = 0,
 431         .max_dma_support = 33,
 432 };
 433
 434 static const struct mtk_i2c_compatible mt8173_compat = {
 435         .regs = mt_i2c_regs_v1,
 436         .pmic_i2c = 0,
 437         .dcm = 1,
 438         .auto_restart = 1,
 439         .aux_len_reg = 1,
 440         .timing_adjust = 0,
 441         .dma_sync = 0,
 442         .ltiming_adjust = 0,
 443         .apdma_sync = 0,
 444         .max_dma_support = 33,
 445 };
 446
 447 static const struct mtk_i2c_compatible mt8183_compat = {
 448         .quirks = &mt8183_i2c_quirks,
 449         .regs = mt_i2c_regs_v2,
 450         .pmic_i2c = 0,
 451         .dcm = 0,
 452         .auto_restart = 1,
 453         .aux_len_reg = 1,
 454         .timing_adjust = 1,
 455         .dma_sync = 1,
 456         .ltiming_adjust = 1,
 457         .apdma_sync = 0,
 458         .max_dma_support = 33,
 459 };
 460
 461 static const struct mtk_i2c_compatible mt8186_compat = {
 462         .regs = mt_i2c_regs_v2,
 463         .pmic_i2c = 0,
 464         .dcm = 0,
 465         .auto_restart = 1,
 466         .aux_len_reg = 1,
 467         .timing_adjust = 1,
 468         .dma_sync = 0,
 469         .ltiming_adjust = 1,
 470         .apdma_sync = 0,
 471         .max_dma_support = 36,
 472 };
 473
 474 static const struct mtk_i2c_compatible mt8188_compat = {
 475         .regs = mt_i2c_regs_v3,
 476         .pmic_i2c = 0,
 477         .dcm = 0,
 478         .auto_restart = 1,
 479         .aux_len_reg = 1,
 480         .timing_adjust = 1,
 481         .dma_sync = 0,
 482         .ltiming_adjust = 1,
 483         .apdma_sync = 1,
 484         .max_dma_support = 36,
 485 };
 486
 487 static const struct mtk_i2c_compatible mt8192_compat = {
 488         .quirks = &mt8183_i2c_quirks,
 489         .regs = mt_i2c_regs_v2,
 490         .pmic_i2c = 0,
 491         .dcm = 0,
 492         .auto_restart = 1,
 493         .aux_len_reg = 1,
 494         .timing_adjust = 1,
 495         .dma_sync = 1,
 496         .ltiming_adjust = 1,
 497         .apdma_sync = 1,
 498         .max_dma_support = 36,
 499 };
 500
 501 static const struct of_device_id mtk_i2c_of_match[] = {
 502         { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
 503         { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
 504         { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
 505         { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
 506         { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
 507         { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
 508         { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
 509         { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
 510         { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat },
 511         { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
 512         {}
 513 };
 514 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
 515
 516 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
 517 {
 518         return readw(i2c->base + i2c->dev_comp->regs[reg]);
 519 }
 520
 521 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
 522                            enum I2C_REGS_OFFSET reg)
 523 {
 524         writew(val, i2c->base + i2c->dev_comp->regs[reg]);
 525 }
 526
 527 static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
 528 {
 529         u16 control_reg;
 530         u16 intr_stat_reg;
 531         u16 ext_conf_val;
 532
 533         mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START);
 534         intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
 535         mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT);
 536
 537         if (i2c->dev_comp->apdma_sync) {
 538                 writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
 539                 udelay(10);
 540                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
 541                 udelay(10);
 542                 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST,
 543                        i2c->pdmabase + OFFSET_RST);
 544                 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST,
 545                                OFFSET_SOFTRESET);
 546                 udelay(10);
 547                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
 548                 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
 549         } else {
 550                 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
 551                 udelay(50);
 552                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
 553                 mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
 554         }
 555
 556         /* Set ioconfig */
 557         if (i2c->use_push_pull)
 558                 mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
 559         else
 560                 mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
 561
 562         if (i2c->dev_comp->dcm)
 563                 mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
 564
 565         mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
 566         mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
 567         if (i2c->dev_comp->ltiming_adjust)
 568                 mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
 569
 570         if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ)
 571                 ext_conf_val = I2C_ST_START_CON;
 572         else
 573                 ext_conf_val = I2C_FS_START_CON;
 574
 575         if (i2c->dev_comp->timing_adjust) {
 576                 ext_conf_val = i2c->ac_timing.ext;
 577                 mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div,
 578                                OFFSET_CLOCK_DIV);
 579                 mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE,
 580                                OFFSET_SCL_MIS_COMP_POINT);
 581                 mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing,
 582                                OFFSET_SDA_TIMING);
 583
 584                 if (i2c->dev_comp->ltiming_adjust) {
 585                         mtk_i2c_writew(i2c, i2c->ac_timing.htiming,
 586                                        OFFSET_TIMING);
 587                         mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS);
 588                         mtk_i2c_writew(i2c, i2c->ac_timing.ltiming,
 589                                        OFFSET_LTIMING);
 590                 } else {
 591                         mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio,
 592                                        OFFSET_SCL_HIGH_LOW_RATIO);
 593                         mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio,
 594                                        OFFSET_HS_SCL_HIGH_LOW_RATIO);
 595                         mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop,
 596                                        OFFSET_STA_STO_AC_TIMING);
 597                         mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop,
 598                                        OFFSET_HS_STA_STO_AC_TIMING);
 599                 }
 600         }
 601         mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF);
 602
 603         /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
 604         if (i2c->have_pmic)
 605                 mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
 606
 607         control_reg = I2C_CONTROL_ACKERR_DET_EN |
 608                       I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
 609         if (i2c->dev_comp->dma_sync)
 610                 control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
 611
 612         mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
 613         mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
 614 }
 615
 616 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed)
 617 {
 618         if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
 619                 return &standard_mode_spec;
 620         else if (speed <= I2C_MAX_FAST_MODE_FREQ)
 621                 return &fast_mode_spec;
 622         else
 623                 return &fast_mode_plus_spec;
 624 }
 625
 626 static int mtk_i2c_max_step_cnt(unsigned int target_speed)
 627 {
 628         if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ)
 629                 return MAX_HS_STEP_CNT_DIV;
 630         else
 631                 return MAX_STEP_CNT_DIV;
 632 }
 633
 634 static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c,
 635                                       unsigned int sample_cnt)
 636 {
 637         int clk_div_restri = 0;
 638
 639         if (i2c->dev_comp->ltiming_adjust == 0)
 640                 return 0;
 641
 642         if (sample_cnt == 1) {
 643                 if (i2c->ac_timing.inter_clk_div == 0)
 644                         clk_div_restri = 0;
 645                 else
 646                         clk_div_restri = 1;
 647         } else {
 648                 if (i2c->ac_timing.inter_clk_div == 0)
 649                         clk_div_restri = -1;
 650                 else if (i2c->ac_timing.inter_clk_div == 1)
 651                         clk_div_restri = 0;
 652                 else
 653                         clk_div_restri = 1;
 654         }
 655
 656         return clk_div_restri;
 657 }
 658
 659 /*
 660  * Check and Calculate i2c ac-timing
 661  *
 662  * Hardware design:
 663  * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
 664  * xxx_cnt_div =  spec->min_xxx_ns / sample_ns
 665  *
 666  * Sample_ns is rounded down for xxx_cnt_div would be greater
 667  * than the smallest spec.
 668  * The sda_timing is chosen as the middle value between
 669  * the largest and smallest.
 670  */
 671 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,
 672                                    unsigned int clk_src,
 673                                    unsigned int check_speed,
 674                                    unsigned int step_cnt,
 675                                    unsigned int sample_cnt)
 676 {
 677         const struct i2c_spec_values *spec;
 678         unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
 679         unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f;
 680         unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1),
 681                                          clk_src);
 682
 683         if (!i2c->dev_comp->timing_adjust)
 684                 return 0;
 685
 686         if (i2c->dev_comp->ltiming_adjust)
 687                 max_sta_cnt = 0x100;
 688
 689         spec = mtk_i2c_get_spec(check_speed);
 690
 691         if (i2c->dev_comp->ltiming_adjust)
 692                 clk_ns = 1000000000 / clk_src;
 693         else
 694                 clk_ns = sample_ns / 2;
 695
 696         su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns +
 697                                   i2c->timing_info.scl_int_delay_ns, clk_ns);
 698         if (su_sta_cnt > max_sta_cnt)
 699                 return -1;
 700
 701         low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
 702         max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
 703         if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) {
 704                 if (low_cnt > step_cnt) {
 705                         high_cnt = 2 * step_cnt - low_cnt;
 706                 } else {
 707                         high_cnt = step_cnt;
 708                         low_cnt = step_cnt;
 709                 }
 710         } else {
 711                 return -2;
 712         }
 713
 714         sda_max = spec->max_hd_dat_ns / sample_ns;
 715         if (sda_max > low_cnt)
 716                 sda_max = 0;
 717
 718         sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
 719         if (sda_min < low_cnt)
 720                 sda_min = 0;
 721
 722         if (sda_min > sda_max)
 723                 return -3;
 724
 725         if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
 726                 if (i2c->dev_comp->ltiming_adjust) {
 727                         i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE |
 728                                 (sample_cnt << 12) | (high_cnt << 8);
 729                         i2c->ac_timing.ltiming &= ~GENMASK(15, 9);
 730                         i2c->ac_timing.ltiming |= (sample_cnt << 12) |
 731                                 (low_cnt << 9);
 732                         i2c->ac_timing.ext &= ~GENMASK(7, 1);
 733                         i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0);
 734                 } else {
 735                         i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) |
 736                                 (high_cnt << 6) | low_cnt;
 737                         i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) |
 738                                 su_sta_cnt;
 739                 }
 740                 i2c->ac_timing.sda_timing &= ~GENMASK(11, 6);
 741                 i2c->ac_timing.sda_timing |= (1 << 12) |
 742                         ((sda_max + sda_min) / 2) << 6;
 743         } else {
 744                 if (i2c->dev_comp->ltiming_adjust) {
 745                         i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt);
 746                         i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt);
 747                         i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0);
 748                 } else {
 749                         i2c->ac_timing.scl_hl_ratio = (1 << 12) |
 750                                 (high_cnt << 6) | low_cnt;
 751                         i2c->ac_timing.sta_stop = (su_sta_cnt << 8) |
 752                                 su_sta_cnt;
 753                 }
 754
 755                 i2c->ac_timing.sda_timing = (1 << 12) |
 756                         (sda_max + sda_min) / 2;
 757         }
 758
 759         return 0;
 760 }
 761
 762 /*
 763  * Calculate i2c port speed
 764  *
 765  * Hardware design:
 766  * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
 767  * clock_div: fixed in hardware, but may be various in different SoCs
 768  *
 769  * The calculation want to pick the highest bus frequency that is still
 770  * less than or equal to i2c->speed_hz. The calculation try to get
 771  * sample_cnt and step_cn
 772  */
 773 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
 774                                    unsigned int target_speed,
 775                                    unsigned int *timing_step_cnt,
 776                                    unsigned int *timing_sample_cnt)
 777 {
 778         unsigned int step_cnt;
 779         unsigned int sample_cnt;
 780         unsigned int max_step_cnt;
 781         unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
 782         unsigned int base_step_cnt;
 783         unsigned int opt_div;
 784         unsigned int best_mul;
 785         unsigned int cnt_mul;
 786         int ret = -EINVAL;
 787         int clk_div_restri = 0;
 788
 789         if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ)
 790                 target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ;
 791
 792         max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
 793         base_step_cnt = max_step_cnt;
 794         /* Find the best combination */
 795         opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
 796         best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
 797
 798         /* Search for the best pair (sample_cnt, step_cnt) with
 799          * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
 800          * 0 < step_cnt < max_step_cnt
 801          * sample_cnt * step_cnt >= opt_div
 802          * optimizing for sample_cnt * step_cnt being minimal
 803          */
 804         for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
 805                 clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt);
 806                 step_cnt = DIV_ROUND_UP(opt_div + clk_div_restri, sample_cnt);
 807                 cnt_mul = step_cnt * sample_cnt;
 808                 if (step_cnt > max_step_cnt)
 809                         continue;
 810
 811                 if (cnt_mul < best_mul) {
 812                         ret = mtk_i2c_check_ac_timing(i2c, clk_src,
 813                                 target_speed, step_cnt - 1, sample_cnt - 1);
 814                         if (ret)
 815                                 continue;
 816
 817                         best_mul = cnt_mul;
 818                         base_sample_cnt = sample_cnt;
 819                         base_step_cnt = step_cnt;
 820                         if (best_mul == (opt_div + clk_div_restri))
 821                                 break;
 822                 }
 823         }
 824
 825         if (ret)
 826                 return -EINVAL;
 827
 828         sample_cnt = base_sample_cnt;
 829         step_cnt = base_step_cnt;
 830
 831         if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) >
 832                 target_speed) {
 833                 /* In this case, hardware can't support such
 834                  * low i2c_bus_freq
 835                  */
 836                 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
 837                 return -EINVAL;
 838         }
 839
 840         *timing_step_cnt = step_cnt - 1;
 841         *timing_sample_cnt = sample_cnt - 1;
 842
 843         return 0;
 844 }
 845
 846 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
 847 {
 848         unsigned int clk_src;
 849         unsigned int step_cnt;
 850         unsigned int sample_cnt;
 851         unsigned int l_step_cnt;
 852         unsigned int l_sample_cnt;
 853         unsigned int target_speed;
 854         unsigned int clk_div;
 855         unsigned int max_clk_div;
 856         int ret;
 857
 858         target_speed = i2c->speed_hz;
 859         parent_clk /= i2c->clk_src_div;
 860
 861         if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust)
 862                 max_clk_div = MAX_CLOCK_DIV_5BITS;
 863         else if (i2c->dev_comp->timing_adjust)
 864                 max_clk_div = MAX_CLOCK_DIV_8BITS;
 865         else
 866                 max_clk_div = 1;
 867
 868         for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
 869                 clk_src = parent_clk / clk_div;
 870                 i2c->ac_timing.inter_clk_div = clk_div - 1;
 871
 872                 if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
 873                         /* Set master code speed register */
 874                         ret = mtk_i2c_calculate_speed(i2c, clk_src,
 875                                                       I2C_MAX_FAST_MODE_FREQ,
 876                                                       &l_step_cnt,
 877                                                       &l_sample_cnt);
 878                         if (ret < 0)
 879                                 continue;
 880
 881                         i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
 882
 883                         /* Set the high speed mode register */
 884                         ret = mtk_i2c_calculate_speed(i2c, clk_src,
 885                                                       target_speed, &step_cnt,
 886                                                       &sample_cnt);
 887                         if (ret < 0)
 888                                 continue;
 889
 890                         i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
 891                                         (sample_cnt << 12) | (step_cnt << 8);
 892
 893                         if (i2c->dev_comp->ltiming_adjust)
 894                                 i2c->ltiming_reg =
 895                                         (l_sample_cnt << 6) | l_step_cnt |
 896                                         (sample_cnt << 12) | (step_cnt << 9);
 897                 } else {
 898                         ret = mtk_i2c_calculate_speed(i2c, clk_src,
 899                                                       target_speed, &l_step_cnt,
 900                                                       &l_sample_cnt);
 901                         if (ret < 0)
 902                                 continue;
 903
 904                         i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
 905
 906                         /* Disable the high speed transaction */
 907                         i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
 908
 909                         if (i2c->dev_comp->ltiming_adjust)
 910                                 i2c->ltiming_reg =
 911                                         (l_sample_cnt << 6) | l_step_cnt;
 912                 }
 913
 914                 break;
 915         }
 916
 917
 918         return 0;
 919 }
 920
 921 static void i2c_dump_register(struct mtk_i2c *i2c)
 922 {
 923         dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n",
 924                 mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR),
 925                 mtk_i2c_readw(i2c, OFFSET_INTR_MASK));
 926         dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n",
 927                 mtk_i2c_readw(i2c, OFFSET_INTR_STAT),
 928                 mtk_i2c_readw(i2c, OFFSET_CONTROL));
 929         dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n",
 930                 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN),
 931                 mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN));
 932         dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n",
 933                 mtk_i2c_readw(i2c, OFFSET_DELAY_LEN),
 934                 mtk_i2c_readw(i2c, OFFSET_TIMING));
 935         dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n",
 936                 mtk_i2c_readw(i2c, OFFSET_START),
 937                 mtk_i2c_readw(i2c, OFFSET_EXT_CONF));
 938         dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n",
 939                 mtk_i2c_readw(i2c, OFFSET_HS),
 940                 mtk_i2c_readw(i2c, OFFSET_IO_CONFIG));
 941         dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n",
 942                 mtk_i2c_readw(i2c, OFFSET_DCM_EN),
 943                 mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX));
 944         dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n",
 945                 mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV),
 946                 mtk_i2c_readw(i2c, OFFSET_FIFO_STAT));
 947         dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n",
 948                 mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL),
 949                 mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT));
 950         if (i2c->dev_comp->regs == mt_i2c_regs_v2) {
 951                 dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n",
 952                         mtk_i2c_readw(i2c, OFFSET_LTIMING),
 953                         mtk_i2c_readw(i2c, OFFSET_MULTI_DMA));
 954         }
 955         dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n",
 956                 readl(i2c->pdmabase + OFFSET_INT_FLAG),
 957                 readl(i2c->pdmabase + OFFSET_INT_EN));
 958         dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n",
 959                 readl(i2c->pdmabase + OFFSET_EN),
 960                 readl(i2c->pdmabase + OFFSET_CON));
 961         dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n",
 962                 readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR),
 963                 readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR));
 964         dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n",
 965                 readl(i2c->pdmabase + OFFSET_TX_LEN),
 966                 readl(i2c->pdmabase + OFFSET_RX_LEN));
 967         dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x",
 968                 readl(i2c->pdmabase + OFFSET_TX_4G_MODE),
 969                 readl(i2c->pdmabase + OFFSET_RX_4G_MODE));
 970 }
 971
 972 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
 973                                int num, int left_num)
 974 {
 975         u16 addr_reg;
 976         u16 start_reg;
 977         u16 control_reg;
 978         u16 restart_flag = 0;
 979         u16 dma_sync = 0;
 980         u32 reg_4g_mode;
 981         u32 reg_dma_reset;
 982         u8 *dma_rd_buf = NULL;
 983         u8 *dma_wr_buf = NULL;
 984         dma_addr_t rpaddr = 0;
 985         dma_addr_t wpaddr = 0;
 986         int ret;
 987
 988         i2c->irq_stat = 0;
 989
 990         if (i2c->auto_restart)
 991                 restart_flag = I2C_RS_TRANSFER;
 992
 993         reinit_completion(&i2c->msg_complete);
 994
 995         if (i2c->dev_comp->apdma_sync &&
 996             i2c->op != I2C_MASTER_WRRD && num > 1) {
 997                 mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL);
 998                 writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST,
 999                        i2c->pdmabase + OFFSET_RST);
1000
1001                 ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST,
1002                                          reg_dma_reset,
1003                                          !(reg_dma_reset & I2C_DMA_WARM_RST),
1004                                          0, 100);
1005                 if (ret) {
1006                         dev_err(i2c->dev, "DMA warm reset timeout\n");
1007                         return -ETIMEDOUT;
1008                 }
1009
1010                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
1011                 mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET);
1012                 mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
1013                 mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE,
1014                                OFFSET_DEBUGCTRL);
1015         }
1016
1017         control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
1018                         ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
1019         if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
1020                 control_reg |= I2C_CONTROL_RS;
1021
1022         if (i2c->op == I2C_MASTER_WRRD)
1023                 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
1024
1025         mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
1026
1027         addr_reg = i2c_8bit_addr_from_msg(msgs);
1028         mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
1029
1030         /* Clear interrupt status */
1031         mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1032                             I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
1033
1034         mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
1035
1036         /* Enable interrupt */
1037         mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1038                             I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
1039
1040         /* Set transfer and transaction len */
1041         if (i2c->op == I2C_MASTER_WRRD) {
1042                 if (i2c->dev_comp->aux_len_reg) {
1043                         mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
1044                         mtk_i2c_writew(i2c, (msgs + 1)->len,
1045                                             OFFSET_TRANSFER_LEN_AUX);
1046                 } else {
1047                         mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
1048                                             OFFSET_TRANSFER_LEN);
1049                 }
1050                 mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
1051         } else {
1052                 mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
1053                 mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
1054         }
1055
1056         if (i2c->dev_comp->apdma_sync) {
1057                 dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
1058                 if (i2c->op == I2C_MASTER_WRRD)
1059                         dma_sync |= I2C_DMA_DIR_CHANGE;
1060         }
1061
1062         /* Prepare buffer data to start transfer */
1063         if (i2c->op == I2C_MASTER_RD) {
1064                 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
1065                 writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
1066
1067                 dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
1068                 if (!dma_rd_buf)
1069                         return -ENOMEM;
1070
1071                 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
1072                                         msgs->len, DMA_FROM_DEVICE);
1073                 if (dma_mapping_error(i2c->dev, rpaddr)) {
1074                         i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false);
1075
1076                         return -ENOMEM;
1077                 }
1078
1079                 if (i2c->dev_comp->max_dma_support > 32) {
1080                         reg_4g_mode = upper_32_bits(rpaddr);
1081                         writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
1082                 }
1083
1084                 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
1085                 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
1086         } else if (i2c->op == I2C_MASTER_WR) {
1087                 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
1088                 writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
1089
1090                 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
1091                 if (!dma_wr_buf)
1092                         return -ENOMEM;
1093
1094                 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
1095                                         msgs->len, DMA_TO_DEVICE);
1096                 if (dma_mapping_error(i2c->dev, wpaddr)) {
1097                         i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
1098
1099                         return -ENOMEM;
1100                 }
1101
1102                 if (i2c->dev_comp->max_dma_support > 32) {
1103                         reg_4g_mode = upper_32_bits(wpaddr);
1104                         writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
1105                 }
1106
1107                 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
1108                 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
1109         } else {
1110                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
1111                 writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
1112
1113                 dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
1114                 if (!dma_wr_buf)
1115                         return -ENOMEM;
1116
1117                 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
1118                                         msgs->len, DMA_TO_DEVICE);
1119                 if (dma_mapping_error(i2c->dev, wpaddr)) {
1120                         i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
1121
1122                         return -ENOMEM;
1123                 }
1124
1125                 dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1);
1126                 if (!dma_rd_buf) {
1127                         dma_unmap_single(i2c->dev, wpaddr,
1128                                          msgs->len, DMA_TO_DEVICE);
1129
1130                         i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
1131
1132                         return -ENOMEM;
1133                 }
1134
1135                 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
1136                                         (msgs + 1)->len,
1137                                         DMA_FROM_DEVICE);
1138                 if (dma_mapping_error(i2c->dev, rpaddr)) {
1139                         dma_unmap_single(i2c->dev, wpaddr,
1140                                          msgs->len, DMA_TO_DEVICE);
1141
1142                         i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
1143                         i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false);
1144
1145                         return -ENOMEM;
1146                 }
1147
1148                 if (i2c->dev_comp->max_dma_support > 32) {
1149                         reg_4g_mode = upper_32_bits(wpaddr);
1150                         writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
1151
1152                         reg_4g_mode = upper_32_bits(rpaddr);
1153                         writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
1154                 }
1155
1156                 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
1157                 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
1158                 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
1159                 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
1160         }
1161
1162         writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
1163
1164         if (!i2c->auto_restart) {
1165                 start_reg = I2C_TRANSAC_START;
1166         } else {
1167                 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
1168                 if (left_num >= 1)
1169                         start_reg |= I2C_RS_MUL_CNFG;
1170         }
1171         mtk_i2c_writew(i2c, start_reg, OFFSET_START);
1172
1173         ret = wait_for_completion_timeout(&i2c->msg_complete,
1174                                           i2c->adap.timeout);
1175
1176         /* Clear interrupt mask */
1177         mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1178                             I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
1179
1180         if (i2c->op == I2C_MASTER_WR) {
1181                 dma_unmap_single(i2c->dev, wpaddr,
1182                                  msgs->len, DMA_TO_DEVICE);
1183
1184                 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
1185         } else if (i2c->op == I2C_MASTER_RD) {
1186                 dma_unmap_single(i2c->dev, rpaddr,
1187                                  msgs->len, DMA_FROM_DEVICE);
1188
1189                 i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true);
1190         } else {
1191                 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
1192                                  DMA_TO_DEVICE);
1193                 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
1194                                  DMA_FROM_DEVICE);
1195
1196                 i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
1197                 i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true);
1198         }
1199
1200         if (ret == 0) {
1201                 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
1202                 i2c_dump_register(i2c);
1203                 mtk_i2c_init_hw(i2c);
1204                 return -ETIMEDOUT;
1205         }
1206
1207         if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
1208                 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
1209                 mtk_i2c_init_hw(i2c);
1210                 return -ENXIO;
1211         }
1212
1213         return 0;
1214 }
1215
1216 static int mtk_i2c_transfer(struct i2c_adapter *adap,
1217                             struct i2c_msg msgs[], int num)
1218 {
1219         int ret;
1220         int left_num = num;
1221         struct mtk_i2c *i2c = i2c_get_adapdata(adap);
1222
1223         ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1224         if (ret)
1225                 return ret;
1226
1227         i2c->auto_restart = i2c->dev_comp->auto_restart;
1228
1229         /* checking if we can skip restart and optimize using WRRD mode */
1230         if (i2c->auto_restart && num == 2) {
1231                 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
1232                     msgs[0].addr == msgs[1].addr) {
1233                         i2c->auto_restart = 0;
1234                 }
1235         }
1236
1237         if (i2c->auto_restart && num >= 2 &&
1238                 i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
1239                 /* ignore the first restart irq after the master code,
1240                  * otherwise the first transfer will be discarded.
1241                  */
1242                 i2c->ignore_restart_irq = true;
1243         else
1244                 i2c->ignore_restart_irq = false;
1245
1246         while (left_num--) {
1247                 if (!msgs->buf) {
1248                         dev_dbg(i2c->dev, "data buffer is NULL.\n");
1249                         ret = -EINVAL;
1250                         goto err_exit;
1251                 }
1252
1253                 if (msgs->flags & I2C_M_RD)
1254                         i2c->op = I2C_MASTER_RD;
1255                 else
1256                         i2c->op = I2C_MASTER_WR;
1257
1258                 if (!i2c->auto_restart) {
1259                         if (num > 1) {
1260                                 /* combined two messages into one transaction */
1261                                 i2c->op = I2C_MASTER_WRRD;
1262                                 left_num--;
1263                         }
1264                 }
1265
1266                 /* always use DMA mode. */
1267                 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
1268                 if (ret < 0)
1269                         goto err_exit;
1270
1271                 msgs++;
1272         }
1273         /* the return value is number of executed messages */
1274         ret = num;
1275
1276 err_exit:
1277         clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1278         return ret;
1279 }
1280
1281 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
1282 {
1283         struct mtk_i2c *i2c = dev_id;
1284         u16 restart_flag = 0;
1285         u16 intr_stat;
1286
1287         if (i2c->auto_restart)
1288                 restart_flag = I2C_RS_TRANSFER;
1289
1290         intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
1291         mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
1292
1293         /*
1294          * when occurs ack error, i2c controller generate two interrupts
1295          * first is the ack error interrupt, then the complete interrupt
1296          * i2c->irq_stat need keep the two interrupt value.
1297          */
1298         i2c->irq_stat |= intr_stat;
1299
1300         if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
1301                 i2c->ignore_restart_irq = false;
1302                 i2c->irq_stat = 0;
1303                 mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
1304                                     I2C_TRANSAC_START, OFFSET_START);
1305         } else {
1306                 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
1307                         complete(&i2c->msg_complete);
1308         }
1309
1310         return IRQ_HANDLED;
1311 }
1312
1313 static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
1314 {
1315         if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN))
1316                 return I2C_FUNC_I2C |
1317                         (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1318         else
1319                 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1320 }
1321
1322 static const struct i2c_algorithm mtk_i2c_algorithm = {
1323         .master_xfer = mtk_i2c_transfer,
1324         .functionality = mtk_i2c_functionality,
1325 };
1326
1327 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
1328 {
1329         int ret;
1330
1331         ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
1332         if (ret < 0)
1333                 i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ;
1334
1335         ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
1336         if (ret < 0)
1337                 return ret;
1338
1339         if (i2c->clk_src_div == 0)
1340                 return -EINVAL;
1341
1342         i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
1343         i2c->use_push_pull =
1344                 of_property_read_bool(np, "mediatek,use-push-pull");
1345
1346         i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true);
1347
1348         return 0;
1349 }
1350
1351 static int mtk_i2c_probe(struct platform_device *pdev)
1352 {
1353         int ret = 0;
1354         struct mtk_i2c *i2c;
1355         struct resource *res;
1356         int i, irq, speed_clk;
1357
1358         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
1359         if (!i2c)
1360                 return -ENOMEM;
1361
1362         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1363         i2c->base = devm_ioremap_resource(&pdev->dev, res);
1364         if (IS_ERR(i2c->base))
1365                 return PTR_ERR(i2c->base);
1366
1367         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1368         i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
1369         if (IS_ERR(i2c->pdmabase))
1370                 return PTR_ERR(i2c->pdmabase);
1371
1372         irq = platform_get_irq(pdev, 0);
1373         if (irq < 0)
1374                 return irq;
1375
1376         init_completion(&i2c->msg_complete);
1377
1378         i2c->dev_comp = of_device_get_match_data(&pdev->dev);
1379         i2c->adap.dev.of_node = pdev->dev.of_node;
1380         i2c->dev = &pdev->dev;
1381         i2c->adap.dev.parent = &pdev->dev;
1382         i2c->adap.owner = THIS_MODULE;
1383         i2c->adap.algo = &mtk_i2c_algorithm;
1384         i2c->adap.quirks = i2c->dev_comp->quirks;
1385         i2c->adap.timeout = 2 * HZ;
1386         i2c->adap.retries = 1;
1387         i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus");
1388         if (IS_ERR(i2c->adap.bus_regulator)) {
1389                 if (PTR_ERR(i2c->adap.bus_regulator) == -ENODEV)
1390                         i2c->adap.bus_regulator = NULL;
1391                 else
1392                         return PTR_ERR(i2c->adap.bus_regulator);
1393         }
1394
1395         ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
1396         if (ret)
1397                 return -EINVAL;
1398
1399         if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
1400                 return -EINVAL;
1401
1402         /* Fill in clk-bulk IDs */
1403         for (i = 0; i < I2C_MT65XX_CLK_MAX; i++)
1404                 i2c->clocks[i].id = i2c_mt65xx_clk_ids[i];
1405
1406         /* Get clocks one by one, some may be optional */
1407         i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main");
1408         if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) {
1409                 dev_err(&pdev->dev, "cannot get main clock\n");
1410                 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk);
1411         }
1412
1413         i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma");
1414         if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) {
1415                 dev_err(&pdev->dev, "cannot get dma clock\n");
1416                 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk);
1417         }
1418
1419         i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb");
1420         if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
1421                 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
1422
1423         if (i2c->have_pmic) {
1424                 i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
1425                 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
1426                         dev_err(&pdev->dev, "cannot get pmic clock\n");
1427                         return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
1428                 }
1429                 speed_clk = I2C_MT65XX_CLK_PMIC;
1430         } else {
1431                 i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL;
1432                 speed_clk = I2C_MT65XX_CLK_MAIN;
1433         }
1434
1435         strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
1436
1437         ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk));
1438         if (ret) {
1439                 dev_err(&pdev->dev, "Failed to set the speed.\n");
1440                 return -EINVAL;
1441         }
1442
1443         if (i2c->dev_comp->max_dma_support > 32) {
1444                 ret = dma_set_mask(&pdev->dev,
1445                                 DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
1446                 if (ret) {
1447                         dev_err(&pdev->dev, "dma_set_mask return error.\n");
1448                         return ret;
1449                 }
1450         }
1451
1452         ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1453         if (ret) {
1454                 dev_err(&pdev->dev, "clock enable failed!\n");
1455                 return ret;
1456         }
1457         mtk_i2c_init_hw(i2c);
1458         clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1459
1460         ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
1461                                IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
1462                                dev_name(&pdev->dev), i2c);
1463         if (ret < 0) {
1464                 dev_err(&pdev->dev,
1465                         "Request I2C IRQ %d fail\n", irq);
1466                 goto err_bulk_unprepare;
1467         }
1468
1469         i2c_set_adapdata(&i2c->adap, i2c);
1470         ret = i2c_add_adapter(&i2c->adap);
1471         if (ret)
1472                 goto err_bulk_unprepare;
1473
1474         platform_set_drvdata(pdev, i2c);
1475
1476         return 0;
1477
1478 err_bulk_unprepare:
1479         clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
1480
1481         return ret;
1482 }
1483
1484 static int mtk_i2c_remove(struct platform_device *pdev)
1485 {
1486         struct mtk_i2c *i2c = platform_get_drvdata(pdev);
1487
1488         i2c_del_adapter(&i2c->adap);
1489
1490         clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
1491
1492         return 0;
1493 }
1494
1495 #ifdef CONFIG_PM_SLEEP
1496 static int mtk_i2c_suspend_noirq(struct device *dev)
1497 {
1498         struct mtk_i2c *i2c = dev_get_drvdata(dev);
1499
1500         i2c_mark_adapter_suspended(&i2c->adap);
1501         clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
1502
1503         return 0;
1504 }
1505
1506 static int mtk_i2c_resume_noirq(struct device *dev)
1507 {
1508         int ret;
1509         struct mtk_i2c *i2c = dev_get_drvdata(dev);
1510
1511         ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1512         if (ret) {
1513                 dev_err(dev, "clock enable failed!\n");
1514                 return ret;
1515         }
1516
1517         mtk_i2c_init_hw(i2c);
1518
1519         clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1520
1521         i2c_mark_adapter_resumed(&i2c->adap);
1522
1523         return 0;
1524 }
1525 #endif
1526
1527 static const struct dev_pm_ops mtk_i2c_pm = {
1528         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq,
1529                                       mtk_i2c_resume_noirq)
1530 };
1531
1532 static struct platform_driver mtk_i2c_driver = {
1533         .probe = mtk_i2c_probe,
1534         .remove = mtk_i2c_remove,
1535         .driver = {
1536                 .name = I2C_DRV_NAME,
1537                 .pm = &mtk_i2c_pm,
1538                 .of_match_table = of_match_ptr(mtk_i2c_of_match),
1539         },
1540 };
1541
1542 module_platform_driver(mtk_i2c_driver);
1543
1544 MODULE_LICENSE("GPL v2");
1545 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
1546 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");