drivers/i2c/busses/i2c-mpc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * This is a combined i2c adapter and algorithm driver for the
   4  * MPC107/Tsi107 PowerPC northbridge and processors that include
   5  * the same I2C unit (8240, 8245, 85xx).
   6  *
   7  * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk
   8  * Copyright (C) 2021 Allied Telesis Labs
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/sched/signal.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_irq.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/property.h>
  18 #include <linux/slab.h>
  19
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/fsl_devices.h>
  24 #include <linux/i2c.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27
  28 #include <asm/mpc52xx.h>
  29 #include <asm/mpc85xx.h>
  30 #include <sysdev/fsl_soc.h>
  31
  32 #define DRV_NAME "mpc-i2c"
  33
  34 #define MPC_I2C_CLOCK_LEGACY   0
  35 #define MPC_I2C_CLOCK_PRESERVE (~0U)
  36
  37 #define MPC_I2C_FDR   0x04
  38 #define MPC_I2C_CR    0x08
  39 #define MPC_I2C_SR    0x0c
  40 #define MPC_I2C_DR    0x10
  41 #define MPC_I2C_DFSRR 0x14
  42
  43 #define CCR_MEN  0x80
  44 #define CCR_MIEN 0x40
  45 #define CCR_MSTA 0x20
  46 #define CCR_MTX  0x10
  47 #define CCR_TXAK 0x08
  48 #define CCR_RSTA 0x04
  49 #define CCR_RSVD 0x02
  50
  51 #define CSR_MCF  0x80
  52 #define CSR_MAAS 0x40
  53 #define CSR_MBB  0x20
  54 #define CSR_MAL  0x10
  55 #define CSR_SRW  0x04
  56 #define CSR_MIF  0x02
  57 #define CSR_RXAK 0x01
  58
  59 enum mpc_i2c_action {
  60         MPC_I2C_ACTION_START = 1,
  61         MPC_I2C_ACTION_RESTART,
  62         MPC_I2C_ACTION_READ_BEGIN,
  63         MPC_I2C_ACTION_READ_BYTE,
  64         MPC_I2C_ACTION_WRITE,
  65         MPC_I2C_ACTION_STOP,
  66
  67         __MPC_I2C_ACTION_CNT
  68 };
  69
  70 static const char * const action_str[] = {
  71         "invalid",
  72         "start",
  73         "restart",
  74         "read begin",
  75         "read",
  76         "write",
  77         "stop",
  78 };
  79
  80 static_assert(ARRAY_SIZE(action_str) == __MPC_I2C_ACTION_CNT);
  81
  82 struct mpc_i2c {
  83         struct device *dev;
  84         void __iomem *base;
  85         u32 interrupt;
  86         wait_queue_head_t waitq;
  87         spinlock_t lock;
  88         struct i2c_adapter adap;
  89         int irq;
  90         u32 real_clk;
  91         u8 fdr, dfsrr;
  92         struct clk *clk_per;
  93         u32 cntl_bits;
  94         enum mpc_i2c_action action;
  95         struct i2c_msg *msgs;
  96         int num_msgs;
  97         int curr_msg;
  98         u32 byte_posn;
  99         u32 block;
 100         int rc;
 101         int expect_rxack;
 102         bool has_errata_A004447;
 103 };
 104
 105 struct mpc_i2c_divider {
 106         u16 divider;
 107         u16 fdr;        /* including dfsrr */
 108 };
 109
 110 struct mpc_i2c_data {
 111         void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
 112 };
 113
 114 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
 115 {
 116         writeb(x, i2c->base + MPC_I2C_CR);
 117 }
 118
 119 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
 120  * the bus, because it wants to send ACK.
 121  * Following sequence of enabling/disabling and sending start/stop generates
 122  * the 9 pulses, each with a START then ending with STOP, so it's all OK.
 123  */
 124 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
 125 {
 126         int k;
 127         unsigned long flags;
 128
 129         for (k = 9; k; k--) {
 130                 writeccr(i2c, 0);
 131                 writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */
 132                 writeccr(i2c, CCR_MEN | CCR_MSTA); /* START */
 133                 readb(i2c->base + MPC_I2C_DR); /* init xfer */
 134                 udelay(15); /* let it hit the bus */
 135                 local_irq_save(flags); /* should not be delayed further */
 136                 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSTA); /* delay SDA */
 137                 readb(i2c->base + MPC_I2C_DR);
 138                 if (k != 1)
 139                         udelay(5);
 140                 local_irq_restore(flags);
 141         }
 142         writeccr(i2c, CCR_MEN); /* Initiate STOP */
 143         readb(i2c->base + MPC_I2C_DR);
 144         udelay(15); /* Let STOP propagate */
 145         writeccr(i2c, 0);
 146 }
 147
 148 static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
 149 {
 150         void __iomem *addr = i2c->base + MPC_I2C_SR;
 151         u8 val;
 152
 153         return readb_poll_timeout(addr, val, val & mask, 0, 100);
 154 }
 155
 156 /*
 157  * Workaround for Erratum A004447. From the P2040CE Rev Q
 158  *
 159  * 1.  Set up the frequency divider and sampling rate.
 160  * 2.  I2CCR - a0h
 161  * 3.  Poll for I2CSR[MBB] to get set.
 162  * 4.  If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
 163  *     step 5. If MAL is not set, then go to step 13.
 164  * 5.  I2CCR - 00h
 165  * 6.  I2CCR - 22h
 166  * 7.  I2CCR - a2h
 167  * 8.  Poll for I2CSR[MBB] to get set.
 168  * 9.  Issue read to I2CDR.
 169  * 10. Poll for I2CSR[MIF] to be set.
 170  * 11. I2CCR - 82h
 171  * 12. Workaround complete. Skip the next steps.
 172  * 13. Issue read to I2CDR.
 173  * 14. Poll for I2CSR[MIF] to be set.
 174  * 15. I2CCR - 80h
 175  */
 176 static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
 177 {
 178         int ret;
 179         u32 val;
 180
 181         writeccr(i2c, CCR_MEN | CCR_MSTA);
 182         ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
 183         if (ret) {
 184                 dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
 185                 return;
 186         }
 187
 188         val = readb(i2c->base + MPC_I2C_SR);
 189
 190         if (val & CSR_MAL) {
 191                 writeccr(i2c, 0x00);
 192                 writeccr(i2c, CCR_MSTA | CCR_RSVD);
 193                 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
 194                 ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
 195                 if (ret) {
 196                         dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
 197                         return;
 198                 }
 199                 val = readb(i2c->base + MPC_I2C_DR);
 200                 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
 201                 if (ret) {
 202                         dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
 203                         return;
 204                 }
 205                 writeccr(i2c, CCR_MEN | CCR_RSVD);
 206         } else {
 207                 val = readb(i2c->base + MPC_I2C_DR);
 208                 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
 209                 if (ret) {
 210                         dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
 211                         return;
 212                 }
 213                 writeccr(i2c, CCR_MEN);
 214         }
 215 }
 216
 217 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
 218 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
 219         {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
 220         {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
 221         {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
 222         {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
 223         {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
 224         {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
 225         {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
 226         {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
 227         {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
 228         {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
 229         {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
 230         {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
 231         {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
 232         {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
 233         {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
 234         {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
 235         {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
 236         {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
 237 };
 238
 239 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
 240                                           u32 *real_clk)
 241 {
 242         struct fwnode_handle *fwnode = of_fwnode_handle(node);
 243         const struct mpc_i2c_divider *div = NULL;
 244         unsigned int pvr = mfspr(SPRN_PVR);
 245         u32 divider;
 246         int i;
 247
 248         if (clock == MPC_I2C_CLOCK_LEGACY) {
 249                 /* see below - default fdr = 0x3f -> div = 2048 */
 250                 *real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / 2048;
 251                 return -EINVAL;
 252         }
 253
 254         /* Determine divider value */
 255         divider = mpc5xxx_fwnode_get_bus_frequency(fwnode) / clock;
 256
 257         /*
 258          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 259          * is equal to or lower than the requested speed.
 260          */
 261         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
 262                 div = &mpc_i2c_dividers_52xx[i];
 263                 /* Old MPC5200 rev A CPUs do not support the high bits */
 264                 if (div->fdr & 0xc0 && pvr == 0x80822011)
 265                         continue;
 266                 if (div->divider >= divider)
 267                         break;
 268         }
 269
 270         *real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / div->divider;
 271         return (int)div->fdr;
 272 }
 273
 274 static void mpc_i2c_setup_52xx(struct device_node *node,
 275                                          struct mpc_i2c *i2c,
 276                                          u32 clock)
 277 {
 278         int ret, fdr;
 279
 280         if (clock == MPC_I2C_CLOCK_PRESERVE) {
 281                 dev_dbg(i2c->dev, "using fdr %d\n",
 282                         readb(i2c->base + MPC_I2C_FDR));
 283                 return;
 284         }
 285
 286         ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk);
 287         fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
 288
 289         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 290
 291         if (ret >= 0)
 292                 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
 293                          fdr);
 294 }
 295 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
 296 static void mpc_i2c_setup_52xx(struct device_node *node,
 297                                          struct mpc_i2c *i2c,
 298                                          u32 clock)
 299 {
 300 }
 301 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
 302
 303 #ifdef CONFIG_PPC_MPC512x
 304 static void mpc_i2c_setup_512x(struct device_node *node,
 305                                          struct mpc_i2c *i2c,
 306                                          u32 clock)
 307 {
 308         struct device_node *node_ctrl;
 309         void __iomem *ctrl;
 310         u32 idx;
 311
 312         /* Enable I2C interrupts for mpc5121 */
 313         node_ctrl = of_find_compatible_node(NULL, NULL,
 314                                             "fsl,mpc5121-i2c-ctrl");
 315         if (node_ctrl) {
 316                 ctrl = of_iomap(node_ctrl, 0);
 317                 if (ctrl) {
 318                         u64 addr;
 319                         /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
 320                         of_property_read_reg(node, 0, &addr, NULL);
 321                         idx = (addr & 0xff) / 0x20;
 322                         setbits32(ctrl, 1 << (24 + idx * 2));
 323                         iounmap(ctrl);
 324                 }
 325                 of_node_put(node_ctrl);
 326         }
 327
 328         /* The clock setup for the 52xx works also fine for the 512x */
 329         mpc_i2c_setup_52xx(node, i2c, clock);
 330 }
 331 #else /* CONFIG_PPC_MPC512x */
 332 static void mpc_i2c_setup_512x(struct device_node *node,
 333                                          struct mpc_i2c *i2c,
 334                                          u32 clock)
 335 {
 336 }
 337 #endif /* CONFIG_PPC_MPC512x */
 338
 339 #ifdef CONFIG_FSL_SOC
 340 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
 341         {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
 342         {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
 343         {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
 344         {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
 345         {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
 346         {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
 347         {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
 348         {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
 349         {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
 350         {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
 351         {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
 352         {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
 353         {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
 354         {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
 355         {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
 356         {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
 357         {49152, 0x011e}, {61440, 0x011f}
 358 };
 359
 360 static u32 mpc_i2c_get_sec_cfg_8xxx(void)
 361 {
 362         struct device_node *node;
 363         u32 __iomem *reg;
 364         u32 val = 0;
 365
 366         node = of_find_node_by_name(NULL, "global-utilities");
 367         if (node) {
 368                 const u32 *prop = of_get_property(node, "reg", NULL);
 369                 if (prop) {
 370                         /*
 371                          * Map and check POR Device Status Register 2
 372                          * (PORDEVSR2) at 0xE0014. Note than while MPC8533
 373                          * and MPC8544 indicate SEC frequency ratio
 374                          * configuration as bit 26 in PORDEVSR2, other MPC8xxx
 375                          * parts may store it differently or may not have it
 376                          * at all.
 377                          */
 378                         reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
 379                         if (!reg)
 380                                 printk(KERN_ERR
 381                                        "Error: couldn't map PORDEVSR2\n");
 382                         else
 383                                 val = in_be32(reg) & 0x00000020; /* sec-cfg */
 384                         iounmap(reg);
 385                 }
 386         }
 387         of_node_put(node);
 388
 389         return val;
 390 }
 391
 392 static u32 mpc_i2c_get_prescaler_8xxx(void)
 393 {
 394         /*
 395          * According to the AN2919 all MPC824x have prescaler 1, while MPC83xx
 396          * may have prescaler 1, 2, or 3, depending on the power-on
 397          * configuration.
 398          */
 399         u32 prescaler = 1;
 400
 401         /* mpc85xx */
 402         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
 403                 || pvr_version_is(PVR_VER_E500MC)
 404                 || pvr_version_is(PVR_VER_E5500)
 405                 || pvr_version_is(PVR_VER_E6500)) {
 406                 unsigned int svr = mfspr(SPRN_SVR);
 407
 408                 if ((SVR_SOC_VER(svr) == SVR_8540)
 409                         || (SVR_SOC_VER(svr) == SVR_8541)
 410                         || (SVR_SOC_VER(svr) == SVR_8560)
 411                         || (SVR_SOC_VER(svr) == SVR_8555)
 412                         || (SVR_SOC_VER(svr) == SVR_8610))
 413                         /* the above 85xx SoCs have prescaler 1 */
 414                         prescaler = 1;
 415                 else if ((SVR_SOC_VER(svr) == SVR_8533)
 416                         || (SVR_SOC_VER(svr) == SVR_8544))
 417                         /* the above 85xx SoCs have prescaler 3 or 2 */
 418                         prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
 419                 else
 420                         /* all the other 85xx have prescaler 2 */
 421                         prescaler = 2;
 422         }
 423
 424         return prescaler;
 425 }
 426
 427 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
 428                                           u32 *real_clk)
 429 {
 430         const struct mpc_i2c_divider *div = NULL;
 431         u32 prescaler = mpc_i2c_get_prescaler_8xxx();
 432         u32 divider;
 433         int i;
 434
 435         if (clock == MPC_I2C_CLOCK_LEGACY) {
 436                 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
 437                 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
 438                 return -EINVAL;
 439         }
 440
 441         divider = fsl_get_sys_freq() / clock / prescaler;
 442
 443         pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
 444                  fsl_get_sys_freq(), clock, divider);
 445
 446         /*
 447          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 448          * is equal to or lower than the requested speed.
 449          */
 450         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
 451                 div = &mpc_i2c_dividers_8xxx[i];
 452                 if (div->divider >= divider)
 453                         break;
 454         }
 455
 456         *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
 457         return (int)div->fdr;
 458 }
 459
 460 static void mpc_i2c_setup_8xxx(struct device_node *node,
 461                                          struct mpc_i2c *i2c,
 462                                          u32 clock)
 463 {
 464         int ret, fdr;
 465
 466         if (clock == MPC_I2C_CLOCK_PRESERVE) {
 467                 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
 468                         readb(i2c->base + MPC_I2C_DFSRR),
 469                         readb(i2c->base + MPC_I2C_FDR));
 470                 return;
 471         }
 472
 473         ret = mpc_i2c_get_fdr_8xxx(node, clock, &i2c->real_clk);
 474         fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
 475
 476         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 477         writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
 478
 479         if (ret >= 0)
 480                 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
 481                          i2c->real_clk, fdr >> 8, fdr & 0xff);
 482 }
 483
 484 #else /* !CONFIG_FSL_SOC */
 485 static void mpc_i2c_setup_8xxx(struct device_node *node,
 486                                          struct mpc_i2c *i2c,
 487                                          u32 clock)
 488 {
 489 }
 490 #endif /* CONFIG_FSL_SOC */
 491
 492 static void mpc_i2c_finish(struct mpc_i2c *i2c, int rc)
 493 {
 494         i2c->rc = rc;
 495         i2c->block = 0;
 496         i2c->cntl_bits = CCR_MEN;
 497         writeccr(i2c, i2c->cntl_bits);
 498         wake_up(&i2c->waitq);
 499 }
 500
 501 static void mpc_i2c_do_action(struct mpc_i2c *i2c)
 502 {
 503         struct i2c_msg *msg = NULL;
 504         int dir = 0;
 505         int recv_len = 0;
 506         u8 byte;
 507
 508         dev_dbg(i2c->dev, "action = %s\n", action_str[i2c->action]);
 509
 510         i2c->cntl_bits &= ~(CCR_RSTA | CCR_MTX | CCR_TXAK);
 511
 512         if (i2c->action != MPC_I2C_ACTION_STOP) {
 513                 msg = &i2c->msgs[i2c->curr_msg];
 514                 if (msg->flags & I2C_M_RD)
 515                         dir = 1;
 516                 if (msg->flags & I2C_M_RECV_LEN)
 517                         recv_len = 1;
 518         }
 519
 520         switch (i2c->action) {
 521         case MPC_I2C_ACTION_RESTART:
 522                 i2c->cntl_bits |= CCR_RSTA;
 523                 fallthrough;
 524
 525         case MPC_I2C_ACTION_START:
 526                 i2c->cntl_bits |= CCR_MSTA | CCR_MTX;
 527                 writeccr(i2c, i2c->cntl_bits);
 528                 writeb((msg->addr << 1) | dir, i2c->base + MPC_I2C_DR);
 529                 i2c->expect_rxack = 1;
 530                 i2c->action = dir ? MPC_I2C_ACTION_READ_BEGIN : MPC_I2C_ACTION_WRITE;
 531                 break;
 532
 533         case MPC_I2C_ACTION_READ_BEGIN:
 534                 if (msg->len) {
 535                         if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
 536                                 i2c->cntl_bits |= CCR_TXAK;
 537
 538                         writeccr(i2c, i2c->cntl_bits);
 539                         /* Dummy read */
 540                         readb(i2c->base + MPC_I2C_DR);
 541                 }
 542                 i2c->action = MPC_I2C_ACTION_READ_BYTE;
 543                 break;
 544
 545         case MPC_I2C_ACTION_READ_BYTE:
 546                 if (i2c->byte_posn || !recv_len) {
 547                         /* Generate Tx ACK on next to last byte */
 548                         if (i2c->byte_posn == msg->len - 2)
 549                                 i2c->cntl_bits |= CCR_TXAK;
 550                         /* Do not generate stop on last byte */
 551                         if (i2c->byte_posn == msg->len - 1)
 552                                 i2c->cntl_bits |= CCR_MTX;
 553
 554                         writeccr(i2c, i2c->cntl_bits);
 555                 }
 556
 557                 byte = readb(i2c->base + MPC_I2C_DR);
 558
 559                 if (i2c->byte_posn == 0 && recv_len) {
 560                         if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) {
 561                                 mpc_i2c_finish(i2c, -EPROTO);
 562                                 return;
 563                         }
 564                         msg->len += byte;
 565                         /*
 566                          * For block reads, generate Tx ACK here if data length
 567                          * is 1 byte (total length is 2 bytes).
 568                          */
 569                         if (msg->len == 2) {
 570                                 i2c->cntl_bits |= CCR_TXAK;
 571                                 writeccr(i2c, i2c->cntl_bits);
 572                         }
 573                 }
 574
 575                 dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action], byte);
 576                 msg->buf[i2c->byte_posn++] = byte;
 577                 break;
 578
 579         case MPC_I2C_ACTION_WRITE:
 580                 dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action],
 581                         msg->buf[i2c->byte_posn]);
 582                 writeb(msg->buf[i2c->byte_posn++], i2c->base + MPC_I2C_DR);
 583                 i2c->expect_rxack = 1;
 584                 break;
 585
 586         case MPC_I2C_ACTION_STOP:
 587                 mpc_i2c_finish(i2c, 0);
 588                 break;
 589
 590         default:
 591                 WARN(1, "Unexpected action %d\n", i2c->action);
 592                 break;
 593         }
 594
 595         if (msg && msg->len == i2c->byte_posn) {
 596                 i2c->curr_msg++;
 597                 i2c->byte_posn = 0;
 598
 599                 if (i2c->curr_msg == i2c->num_msgs) {
 600                         i2c->action = MPC_I2C_ACTION_STOP;
 601                         /*
 602                          * We don't get another interrupt on read so
 603                          * finish the transfer now
 604                          */
 605                         if (dir)
 606                                 mpc_i2c_finish(i2c, 0);
 607                 } else {
 608                         i2c->action = MPC_I2C_ACTION_RESTART;
 609                 }
 610         }
 611 }
 612
 613 static void mpc_i2c_do_intr(struct mpc_i2c *i2c, u8 status)
 614 {
 615         spin_lock(&i2c->lock);
 616
 617         if (!(status & CSR_MCF)) {
 618                 dev_dbg(i2c->dev, "unfinished\n");
 619                 mpc_i2c_finish(i2c, -EIO);
 620                 goto out;
 621         }
 622
 623         if (status & CSR_MAL) {
 624                 dev_dbg(i2c->dev, "arbitration lost\n");
 625                 mpc_i2c_finish(i2c, -EAGAIN);
 626                 goto out;
 627         }
 628
 629         if (i2c->expect_rxack && (status & CSR_RXAK)) {
 630                 dev_dbg(i2c->dev, "no Rx ACK\n");
 631                 mpc_i2c_finish(i2c, -ENXIO);
 632                 goto out;
 633         }
 634         i2c->expect_rxack = 0;
 635
 636         mpc_i2c_do_action(i2c);
 637
 638 out:
 639         spin_unlock(&i2c->lock);
 640 }
 641
 642 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
 643 {
 644         struct mpc_i2c *i2c = dev_id;
 645         u8 status;
 646
 647         status = readb(i2c->base + MPC_I2C_SR);
 648         if (status & CSR_MIF) {
 649                 /* Wait up to 100us for transfer to properly complete */
 650                 readb_poll_timeout_atomic(i2c->base + MPC_I2C_SR, status, status & CSR_MCF, 0, 100);
 651                 writeb(0, i2c->base + MPC_I2C_SR);
 652                 mpc_i2c_do_intr(i2c, status);
 653                 return IRQ_HANDLED;
 654         }
 655         return IRQ_NONE;
 656 }
 657
 658 static int mpc_i2c_wait_for_completion(struct mpc_i2c *i2c)
 659 {
 660         long time_left;
 661
 662         time_left = wait_event_timeout(i2c->waitq, !i2c->block, i2c->adap.timeout);
 663         if (!time_left)
 664                 return -ETIMEDOUT;
 665         if (time_left < 0)
 666                 return time_left;
 667
 668         return 0;
 669 }
 670
 671 static int mpc_i2c_execute_msg(struct mpc_i2c *i2c)
 672 {
 673         unsigned long orig_jiffies;
 674         unsigned long flags;
 675         int ret;
 676
 677         spin_lock_irqsave(&i2c->lock, flags);
 678
 679         i2c->curr_msg = 0;
 680         i2c->rc = 0;
 681         i2c->byte_posn = 0;
 682         i2c->block = 1;
 683         i2c->action = MPC_I2C_ACTION_START;
 684
 685         i2c->cntl_bits = CCR_MEN | CCR_MIEN;
 686         writeb(0, i2c->base + MPC_I2C_SR);
 687         writeccr(i2c, i2c->cntl_bits);
 688
 689         mpc_i2c_do_action(i2c);
 690
 691         spin_unlock_irqrestore(&i2c->lock, flags);
 692
 693         ret = mpc_i2c_wait_for_completion(i2c);
 694         if (ret)
 695                 i2c->rc = ret;
 696
 697         if (i2c->rc == -EIO || i2c->rc == -EAGAIN || i2c->rc == -ETIMEDOUT)
 698                 i2c_recover_bus(&i2c->adap);
 699
 700         orig_jiffies = jiffies;
 701         /* Wait until STOP is seen, allow up to 1 s */
 702         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
 703                 if (time_after(jiffies, orig_jiffies + HZ)) {
 704                         u8 status = readb(i2c->base + MPC_I2C_SR);
 705
 706                         dev_dbg(i2c->dev, "timeout\n");
 707                         if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
 708                                 writeb(status & ~CSR_MAL,
 709                                        i2c->base + MPC_I2C_SR);
 710                                 i2c_recover_bus(&i2c->adap);
 711                         }
 712                         return -EIO;
 713                 }
 714                 cond_resched();
 715         }
 716
 717         return i2c->rc;
 718 }
 719
 720 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 721 {
 722         int rc, ret = num;
 723         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
 724         int i;
 725
 726         dev_dbg(i2c->dev, "num = %d\n", num);
 727         for (i = 0; i < num; i++)
 728                 dev_dbg(i2c->dev, "  addr = %02x, flags = %02x, len = %d, %*ph\n",
 729                         msgs[i].addr, msgs[i].flags, msgs[i].len,
 730                         msgs[i].flags & I2C_M_RD ? 0 : msgs[i].len,
 731                         msgs[i].buf);
 732
 733         WARN_ON(i2c->msgs != NULL);
 734         i2c->msgs = msgs;
 735         i2c->num_msgs = num;
 736
 737         rc = mpc_i2c_execute_msg(i2c);
 738         if (rc < 0)
 739                 ret = rc;
 740
 741         i2c->num_msgs = 0;
 742         i2c->msgs = NULL;
 743
 744         return ret;
 745 }
 746
 747 static u32 mpc_functionality(struct i2c_adapter *adap)
 748 {
 749         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
 750           | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
 751 }
 752
 753 static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
 754 {
 755         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
 756
 757         if (i2c->has_errata_A004447)
 758                 mpc_i2c_fixup_A004447(i2c);
 759         else
 760                 mpc_i2c_fixup(i2c);
 761
 762         return 0;
 763 }
 764
 765 static const struct i2c_algorithm mpc_algo = {
 766         .master_xfer = mpc_xfer,
 767         .functionality = mpc_functionality,
 768 };
 769
 770 static struct i2c_adapter mpc_ops = {
 771         .owner = THIS_MODULE,
 772         .algo = &mpc_algo,
 773 };
 774
 775 static struct i2c_bus_recovery_info fsl_i2c_recovery_info = {
 776         .recover_bus = fsl_i2c_bus_recovery,
 777 };
 778
 779 static int fsl_i2c_probe(struct platform_device *op)
 780 {
 781         const struct mpc_i2c_data *data;
 782         struct mpc_i2c *i2c;
 783         struct clk *clk;
 784         int result;
 785         u32 clock;
 786         int err;
 787
 788         i2c = devm_kzalloc(&op->dev, sizeof(*i2c), GFP_KERNEL);
 789         if (!i2c)
 790                 return -ENOMEM;
 791
 792         i2c->dev = &op->dev; /* for debug and error output */
 793
 794         init_waitqueue_head(&i2c->waitq);
 795         spin_lock_init(&i2c->lock);
 796
 797         i2c->base = devm_platform_ioremap_resource(op, 0);
 798         if (IS_ERR(i2c->base))
 799                 return PTR_ERR(i2c->base);
 800
 801         i2c->irq = platform_get_irq(op, 0);
 802         if (i2c->irq < 0)
 803                 return i2c->irq;
 804
 805         result = devm_request_irq(&op->dev, i2c->irq, mpc_i2c_isr,
 806                         IRQF_SHARED, "i2c-mpc", i2c);
 807         if (result < 0) {
 808                 dev_err(i2c->dev, "failed to attach interrupt\n");
 809                 return result;
 810         }
 811
 812         /*
 813          * enable clock for the I2C peripheral (non fatal),
 814          * keep a reference upon successful allocation
 815          */
 816         clk = devm_clk_get_optional(&op->dev, NULL);
 817         if (IS_ERR(clk))
 818                 return PTR_ERR(clk);
 819
 820         err = clk_prepare_enable(clk);
 821         if (err) {
 822                 dev_err(&op->dev, "failed to enable clock\n");
 823                 return err;
 824         }
 825
 826         i2c->clk_per = clk;
 827
 828         if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) {
 829                 clock = MPC_I2C_CLOCK_PRESERVE;
 830         } else {
 831                 result = of_property_read_u32(op->dev.of_node,
 832                                               "clock-frequency", &clock);
 833                 if (result)
 834                         clock = MPC_I2C_CLOCK_LEGACY;
 835         }
 836
 837         data = device_get_match_data(&op->dev);
 838         if (data) {
 839                 data->setup(op->dev.of_node, i2c, clock);
 840         } else {
 841                 /* Backwards compatibility */
 842                 if (of_property_read_bool(op->dev.of_node, "dfsrr"))
 843                         mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock);
 844         }
 845
 846         /*
 847          * "fsl,timeout" has been marked as deprecated and, to maintain
 848          * backward compatibility, we will only look for it if
 849          * "i2c-scl-clk-low-timeout-us" is not present.
 850          */
 851         result = of_property_read_u32(op->dev.of_node,
 852                                       "i2c-scl-clk-low-timeout-us",
 853                                       &mpc_ops.timeout);
 854         if (result == -EINVAL)
 855                 result = of_property_read_u32(op->dev.of_node,
 856                                               "fsl,timeout", &mpc_ops.timeout);
 857
 858         if (!result) {
 859                 mpc_ops.timeout *= HZ / 1000000;
 860                 if (mpc_ops.timeout < 5)
 861                         mpc_ops.timeout = 5;
 862         } else {
 863                 mpc_ops.timeout = HZ;
 864         }
 865
 866         dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
 867
 868         if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
 869                 i2c->has_errata_A004447 = true;
 870
 871         i2c->adap = mpc_ops;
 872         scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
 873                   "MPC adapter (%s)", of_node_full_name(op->dev.of_node));
 874         i2c->adap.dev.parent = &op->dev;
 875         i2c->adap.nr = op->id;
 876         i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
 877         i2c->adap.bus_recovery_info = &fsl_i2c_recovery_info;
 878         platform_set_drvdata(op, i2c);
 879         i2c_set_adapdata(&i2c->adap, i2c);
 880
 881         result = i2c_add_numbered_adapter(&i2c->adap);
 882         if (result)
 883                 goto fail_add;
 884
 885         return 0;
 886
 887  fail_add:
 888         clk_disable_unprepare(i2c->clk_per);
 889
 890         return result;
 891 };
 892
 893 static void fsl_i2c_remove(struct platform_device *op)
 894 {
 895         struct mpc_i2c *i2c = platform_get_drvdata(op);
 896
 897         i2c_del_adapter(&i2c->adap);
 898
 899         clk_disable_unprepare(i2c->clk_per);
 900 };
 901
 902 static int __maybe_unused mpc_i2c_suspend(struct device *dev)
 903 {
 904         struct mpc_i2c *i2c = dev_get_drvdata(dev);
 905
 906         i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
 907         i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
 908
 909         return 0;
 910 }
 911
 912 static int __maybe_unused mpc_i2c_resume(struct device *dev)
 913 {
 914         struct mpc_i2c *i2c = dev_get_drvdata(dev);
 915
 916         writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
 917         writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
 918
 919         return 0;
 920 }
 921 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
 922
 923 static const struct mpc_i2c_data mpc_i2c_data_512x = {
 924         .setup = mpc_i2c_setup_512x,
 925 };
 926
 927 static const struct mpc_i2c_data mpc_i2c_data_52xx = {
 928         .setup = mpc_i2c_setup_52xx,
 929 };
 930
 931 static const struct mpc_i2c_data mpc_i2c_data_8313 = {
 932         .setup = mpc_i2c_setup_8xxx,
 933 };
 934
 935 static const struct mpc_i2c_data mpc_i2c_data_8543 = {
 936         .setup = mpc_i2c_setup_8xxx,
 937 };
 938
 939 static const struct mpc_i2c_data mpc_i2c_data_8544 = {
 940         .setup = mpc_i2c_setup_8xxx,
 941 };
 942
 943 static const struct of_device_id mpc_i2c_of_match[] = {
 944         {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
 945         {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
 946         {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
 947         {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
 948         {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
 949         {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
 950         {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
 951         /* Backward compatibility */
 952         {.compatible = "fsl-i2c", },
 953         {},
 954 };
 955 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
 956
 957 /* Structure for a device driver */
 958 static struct platform_driver mpc_i2c_driver = {
 959         .probe          = fsl_i2c_probe,
 960         .remove_new     = fsl_i2c_remove,
 961         .driver = {
 962                 .name = DRV_NAME,
 963                 .of_match_table = mpc_i2c_of_match,
 964                 .pm = &mpc_i2c_pm_ops,
 965         },
 966 };
 967
 968 module_platform_driver(mpc_i2c_driver);
 969
 970 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
 971 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
 972                    "MPC824x/83xx/85xx/86xx/512x/52xx processors");
 973 MODULE_LICENSE("GPL");