i2c: remove DEFINE_PCI_DEVICE_TABLE macro
[platform/adaptation/renesas_rcar/renesas_kernel.git] / drivers / i2c / busses / i2c-ismt.c
1 /*
2  * This file is provided under a dual BSD/GPLv2 license.  When using or
3  * redistributing this file, you may do so under either license.
4  *
5  * Copyright(c) 2012 Intel Corporation. All rights reserved.
6  *
7  * GPL LICENSE SUMMARY
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of version 2 of the GNU General Public License as
11  * published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16  * General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21  * The full GNU General Public License is included in this distribution
22  * in the file called LICENSE.GPL.
23  *
24  * BSD LICENSE
25  *
26  * Redistribution and use in source and binary forms, with or without
27  * modification, are permitted provided that the following conditions
28  * are met:
29  *
30  *   * Redistributions of source code must retain the above copyright
31  *     notice, this list of conditions and the following disclaimer.
32  *   * Redistributions in binary form must reproduce the above copyright
33  *     notice, this list of conditions and the following disclaimer in
34  *     the documentation and/or other materials provided with the
35  *     distribution.
36  *   * Neither the name of Intel Corporation nor the names of its
37  *     contributors may be used to endorse or promote products derived
38  *     from this software without specific prior written permission.
39  *
40  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
43  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
44  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
45  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51  */
52
53 /*
54  *  Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
55  *  S12xx Product Family.
56  *
57  *  Features supported by this driver:
58  *  Hardware PEC                     yes
59  *  Block buffer                     yes
60  *  Block process call transaction   no
61  *  Slave mode                       no
62  */
63
64 #include <linux/module.h>
65 #include <linux/pci.h>
66 #include <linux/kernel.h>
67 #include <linux/stddef.h>
68 #include <linux/completion.h>
69 #include <linux/dma-mapping.h>
70 #include <linux/i2c.h>
71 #include <linux/acpi.h>
72 #include <linux/interrupt.h>
73
74 #include <asm-generic/io-64-nonatomic-lo-hi.h>
75
76 /* PCI Address Constants */
77 #define SMBBAR          0
78
79 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
80 #define PCI_DEVICE_ID_INTEL_S1200_SMT0  0x0c59
81 #define PCI_DEVICE_ID_INTEL_S1200_SMT1  0x0c5a
82 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT  0x1f15
83
84 #define ISMT_DESC_ENTRIES       32      /* number of descriptor entries */
85 #define ISMT_MAX_RETRIES        3       /* number of SMBus retries to attempt */
86
87 /* Hardware Descriptor Constants - Control Field */
88 #define ISMT_DESC_CWRL  0x01    /* Command/Write Length */
89 #define ISMT_DESC_BLK   0X04    /* Perform Block Transaction */
90 #define ISMT_DESC_FAIR  0x08    /* Set fairness flag upon successful arbit. */
91 #define ISMT_DESC_PEC   0x10    /* Packet Error Code */
92 #define ISMT_DESC_I2C   0x20    /* I2C Enable */
93 #define ISMT_DESC_INT   0x40    /* Interrupt */
94 #define ISMT_DESC_SOE   0x80    /* Stop On Error */
95
96 /* Hardware Descriptor Constants - Status Field */
97 #define ISMT_DESC_SCS   0x01    /* Success */
98 #define ISMT_DESC_DLTO  0x04    /* Data Low Time Out */
99 #define ISMT_DESC_NAK   0x08    /* NAK Received */
100 #define ISMT_DESC_CRC   0x10    /* CRC Error */
101 #define ISMT_DESC_CLTO  0x20    /* Clock Low Time Out */
102 #define ISMT_DESC_COL   0x40    /* Collisions */
103 #define ISMT_DESC_LPR   0x80    /* Large Packet Received */
104
105 /* Macros */
106 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
107
108 /* iSMT General Register address offsets (SMBBAR + <addr>) */
109 #define ISMT_GR_GCTRL           0x000   /* General Control */
110 #define ISMT_GR_SMTICL          0x008   /* SMT Interrupt Cause Location */
111 #define ISMT_GR_ERRINTMSK       0x010   /* Error Interrupt Mask */
112 #define ISMT_GR_ERRAERMSK       0x014   /* Error AER Mask */
113 #define ISMT_GR_ERRSTS          0x018   /* Error Status */
114 #define ISMT_GR_ERRINFO         0x01c   /* Error Information */
115
116 /* iSMT Master Registers */
117 #define ISMT_MSTR_MDBA          0x100   /* Master Descriptor Base Address */
118 #define ISMT_MSTR_MCTRL         0x108   /* Master Control */
119 #define ISMT_MSTR_MSTS          0x10c   /* Master Status */
120 #define ISMT_MSTR_MDS           0x110   /* Master Descriptor Size */
121 #define ISMT_MSTR_RPOLICY       0x114   /* Retry Policy */
122
123 /* iSMT Miscellaneous Registers */
124 #define ISMT_SPGT       0x300   /* SMBus PHY Global Timing */
125
126 /* General Control Register (GCTRL) bit definitions */
127 #define ISMT_GCTRL_TRST 0x04    /* Target Reset */
128 #define ISMT_GCTRL_KILL 0x08    /* Kill */
129 #define ISMT_GCTRL_SRST 0x40    /* Soft Reset */
130
131 /* Master Control Register (MCTRL) bit definitions */
132 #define ISMT_MCTRL_SS   0x01            /* Start/Stop */
133 #define ISMT_MCTRL_MEIE 0x10            /* Master Error Interrupt Enable */
134 #define ISMT_MCTRL_FMHP 0x00ff0000      /* Firmware Master Head Ptr (FMHP) */
135
136 /* Master Status Register (MSTS) bit definitions */
137 #define ISMT_MSTS_HMTP  0xff0000        /* HW Master Tail Pointer (HMTP) */
138 #define ISMT_MSTS_MIS   0x20            /* Master Interrupt Status (MIS) */
139 #define ISMT_MSTS_MEIS  0x10            /* Master Error Int Status (MEIS) */
140 #define ISMT_MSTS_IP    0x01            /* In Progress */
141
142 /* Master Descriptor Size (MDS) bit definitions */
143 #define ISMT_MDS_MASK   0xff    /* Master Descriptor Size mask (MDS) */
144
145 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
146 #define ISMT_SPGT_SPD_MASK      0xc0000000      /* SMBus Speed mask */
147 #define ISMT_SPGT_SPD_80K       0x00            /* 80 kHz */
148 #define ISMT_SPGT_SPD_100K      (0x1 << 30)     /* 100 kHz */
149 #define ISMT_SPGT_SPD_400K      (0x2 << 30)     /* 400 kHz */
150 #define ISMT_SPGT_SPD_1M        (0x3 << 30)     /* 1 MHz */
151
152
153 /* MSI Control Register (MSICTL) bit definitions */
154 #define ISMT_MSICTL_MSIE        0x01    /* MSI Enable */
155
156 /* iSMT Hardware Descriptor */
157 struct ismt_desc {
158         u8 tgtaddr_rw;  /* target address & r/w bit */
159         u8 wr_len_cmd;  /* write length in bytes or a command */
160         u8 rd_len;      /* read length */
161         u8 control;     /* control bits */
162         u8 status;      /* status bits */
163         u8 retry;       /* collision retry and retry count */
164         u8 rxbytes;     /* received bytes */
165         u8 txbytes;     /* transmitted bytes */
166         u32 dptr_low;   /* lower 32 bit of the data pointer */
167         u32 dptr_high;  /* upper 32 bit of the data pointer */
168 } __packed;
169
170 struct ismt_priv {
171         struct i2c_adapter adapter;
172         void *smba;                             /* PCI BAR */
173         struct pci_dev *pci_dev;
174         struct ismt_desc *hw;                   /* descriptor virt base addr */
175         dma_addr_t io_rng_dma;                  /* descriptor HW base addr */
176         u8 head;                                /* ring buffer head pointer */
177         struct completion cmp;                  /* interrupt completion */
178         u8 dma_buffer[I2C_SMBUS_BLOCK_MAX + 1]; /* temp R/W data buffer */
179         bool using_msi;                         /* type of interrupt flag */
180 };
181
182 /**
183  * ismt_ids - PCI device IDs supported by this driver
184  */
185 static const struct pci_device_id ismt_ids[] = {
186         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
187         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
188         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
189         { 0, }
190 };
191
192 MODULE_DEVICE_TABLE(pci, ismt_ids);
193
194 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
195 static unsigned int bus_speed;
196 module_param(bus_speed, uint, S_IRUGO);
197 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
198
199 /**
200  * __ismt_desc_dump() - dump the contents of a specific descriptor
201  */
202 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
203 {
204
205         dev_dbg(dev, "Descriptor struct:  %p\n", desc);
206         dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
207         dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
208         dev_dbg(dev, "\trd_len=    0x%02X\n", desc->rd_len);
209         dev_dbg(dev, "\tcontrol=   0x%02X\n", desc->control);
210         dev_dbg(dev, "\tstatus=    0x%02X\n", desc->status);
211         dev_dbg(dev, "\tretry=     0x%02X\n", desc->retry);
212         dev_dbg(dev, "\trxbytes=   0x%02X\n", desc->rxbytes);
213         dev_dbg(dev, "\ttxbytes=   0x%02X\n", desc->txbytes);
214         dev_dbg(dev, "\tdptr_low=  0x%08X\n", desc->dptr_low);
215         dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
216 }
217 /**
218  * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
219  * @priv: iSMT private data
220  */
221 static void ismt_desc_dump(struct ismt_priv *priv)
222 {
223         struct device *dev = &priv->pci_dev->dev;
224         struct ismt_desc *desc = &priv->hw[priv->head];
225
226         dev_dbg(dev, "Dump of the descriptor struct:  0x%X\n", priv->head);
227         __ismt_desc_dump(dev, desc);
228 }
229
230 /**
231  * ismt_gen_reg_dump() - dump the iSMT General Registers
232  * @priv: iSMT private data
233  */
234 static void ismt_gen_reg_dump(struct ismt_priv *priv)
235 {
236         struct device *dev = &priv->pci_dev->dev;
237
238         dev_dbg(dev, "Dump of the iSMT General Registers\n");
239         dev_dbg(dev, "  GCTRL.... : (0x%p)=0x%X\n",
240                 priv->smba + ISMT_GR_GCTRL,
241                 readl(priv->smba + ISMT_GR_GCTRL));
242         dev_dbg(dev, "  SMTICL... : (0x%p)=0x%016llX\n",
243                 priv->smba + ISMT_GR_SMTICL,
244                 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
245         dev_dbg(dev, "  ERRINTMSK : (0x%p)=0x%X\n",
246                 priv->smba + ISMT_GR_ERRINTMSK,
247                 readl(priv->smba + ISMT_GR_ERRINTMSK));
248         dev_dbg(dev, "  ERRAERMSK : (0x%p)=0x%X\n",
249                 priv->smba + ISMT_GR_ERRAERMSK,
250                 readl(priv->smba + ISMT_GR_ERRAERMSK));
251         dev_dbg(dev, "  ERRSTS... : (0x%p)=0x%X\n",
252                 priv->smba + ISMT_GR_ERRSTS,
253                 readl(priv->smba + ISMT_GR_ERRSTS));
254         dev_dbg(dev, "  ERRINFO.. : (0x%p)=0x%X\n",
255                 priv->smba + ISMT_GR_ERRINFO,
256                 readl(priv->smba + ISMT_GR_ERRINFO));
257 }
258
259 /**
260  * ismt_mstr_reg_dump() - dump the iSMT Master Registers
261  * @priv: iSMT private data
262  */
263 static void ismt_mstr_reg_dump(struct ismt_priv *priv)
264 {
265         struct device *dev = &priv->pci_dev->dev;
266
267         dev_dbg(dev, "Dump of the iSMT Master Registers\n");
268         dev_dbg(dev, "  MDBA..... : (0x%p)=0x%016llX\n",
269                 priv->smba + ISMT_MSTR_MDBA,
270                 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
271         dev_dbg(dev, "  MCTRL.... : (0x%p)=0x%X\n",
272                 priv->smba + ISMT_MSTR_MCTRL,
273                 readl(priv->smba + ISMT_MSTR_MCTRL));
274         dev_dbg(dev, "  MSTS..... : (0x%p)=0x%X\n",
275                 priv->smba + ISMT_MSTR_MSTS,
276                 readl(priv->smba + ISMT_MSTR_MSTS));
277         dev_dbg(dev, "  MDS...... : (0x%p)=0x%X\n",
278                 priv->smba + ISMT_MSTR_MDS,
279                 readl(priv->smba + ISMT_MSTR_MDS));
280         dev_dbg(dev, "  RPOLICY.. : (0x%p)=0x%X\n",
281                 priv->smba + ISMT_MSTR_RPOLICY,
282                 readl(priv->smba + ISMT_MSTR_RPOLICY));
283         dev_dbg(dev, "  SPGT..... : (0x%p)=0x%X\n",
284                 priv->smba + ISMT_SPGT,
285                 readl(priv->smba + ISMT_SPGT));
286 }
287
288 /**
289  * ismt_submit_desc() - add a descriptor to the ring
290  * @priv: iSMT private data
291  */
292 static void ismt_submit_desc(struct ismt_priv *priv)
293 {
294         uint fmhp;
295         uint val;
296
297         ismt_desc_dump(priv);
298         ismt_gen_reg_dump(priv);
299         ismt_mstr_reg_dump(priv);
300
301         /* Set the FMHP (Firmware Master Head Pointer)*/
302         fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
303         val = readl(priv->smba + ISMT_MSTR_MCTRL);
304         writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
305                priv->smba + ISMT_MSTR_MCTRL);
306
307         /* Set the start bit */
308         val = readl(priv->smba + ISMT_MSTR_MCTRL);
309         writel(val | ISMT_MCTRL_SS,
310                priv->smba + ISMT_MSTR_MCTRL);
311 }
312
313 /**
314  * ismt_process_desc() - handle the completion of the descriptor
315  * @desc: the iSMT hardware descriptor
316  * @data: data buffer from the upper layer
317  * @priv: ismt_priv struct holding our dma buffer
318  * @size: SMBus transaction type
319  * @read_write: flag to indicate if this is a read or write
320  */
321 static int ismt_process_desc(const struct ismt_desc *desc,
322                              union i2c_smbus_data *data,
323                              struct ismt_priv *priv, int size,
324                              char read_write)
325 {
326         u8 *dma_buffer = priv->dma_buffer;
327
328         dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
329         __ismt_desc_dump(&priv->pci_dev->dev, desc);
330
331         if (desc->status & ISMT_DESC_SCS) {
332                 if (read_write == I2C_SMBUS_WRITE &&
333                     size != I2C_SMBUS_PROC_CALL)
334                         return 0;
335
336                 switch (size) {
337                 case I2C_SMBUS_BYTE:
338                 case I2C_SMBUS_BYTE_DATA:
339                         data->byte = dma_buffer[0];
340                         break;
341                 case I2C_SMBUS_WORD_DATA:
342                 case I2C_SMBUS_PROC_CALL:
343                         data->word = dma_buffer[0] | (dma_buffer[1] << 8);
344                         break;
345                 case I2C_SMBUS_BLOCK_DATA:
346                 case I2C_SMBUS_I2C_BLOCK_DATA:
347                         memcpy(&data->block[1], dma_buffer, desc->rxbytes);
348                         data->block[0] = desc->rxbytes;
349                         break;
350                 }
351                 return 0;
352         }
353
354         if (likely(desc->status & ISMT_DESC_NAK))
355                 return -ENXIO;
356
357         if (desc->status & ISMT_DESC_CRC)
358                 return -EBADMSG;
359
360         if (desc->status & ISMT_DESC_COL)
361                 return -EAGAIN;
362
363         if (desc->status & ISMT_DESC_LPR)
364                 return -EPROTO;
365
366         if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
367                 return -ETIMEDOUT;
368
369         return -EIO;
370 }
371
372 /**
373  * ismt_access() - process an SMBus command
374  * @adap: the i2c host adapter
375  * @addr: address of the i2c/SMBus target
376  * @flags: command options
377  * @read_write: read from or write to device
378  * @command: the i2c/SMBus command to issue
379  * @size: SMBus transaction type
380  * @data: read/write data buffer
381  */
382 static int ismt_access(struct i2c_adapter *adap, u16 addr,
383                        unsigned short flags, char read_write, u8 command,
384                        int size, union i2c_smbus_data *data)
385 {
386         int ret;
387         dma_addr_t dma_addr = 0; /* address of the data buffer */
388         u8 dma_size = 0;
389         enum dma_data_direction dma_direction = 0;
390         struct ismt_desc *desc;
391         struct ismt_priv *priv = i2c_get_adapdata(adap);
392         struct device *dev = &priv->pci_dev->dev;
393
394         desc = &priv->hw[priv->head];
395
396         /* Initialize the DMA buffer */
397         memset(priv->dma_buffer, 0, sizeof(priv->dma_buffer));
398
399         /* Initialize the descriptor */
400         memset(desc, 0, sizeof(struct ismt_desc));
401         desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
402
403         /* Initialize common control bits */
404         if (likely(priv->using_msi))
405                 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
406         else
407                 desc->control = ISMT_DESC_FAIR;
408
409         if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
410             && (size != I2C_SMBUS_I2C_BLOCK_DATA))
411                 desc->control |= ISMT_DESC_PEC;
412
413         switch (size) {
414         case I2C_SMBUS_QUICK:
415                 dev_dbg(dev, "I2C_SMBUS_QUICK\n");
416                 break;
417
418         case I2C_SMBUS_BYTE:
419                 if (read_write == I2C_SMBUS_WRITE) {
420                         /*
421                          * Send Byte
422                          * The command field contains the write data
423                          */
424                         dev_dbg(dev, "I2C_SMBUS_BYTE:  WRITE\n");
425                         desc->control |= ISMT_DESC_CWRL;
426                         desc->wr_len_cmd = command;
427                 } else {
428                         /* Receive Byte */
429                         dev_dbg(dev, "I2C_SMBUS_BYTE:  READ\n");
430                         dma_size = 1;
431                         dma_direction = DMA_FROM_DEVICE;
432                         desc->rd_len = 1;
433                 }
434                 break;
435
436         case I2C_SMBUS_BYTE_DATA:
437                 if (read_write == I2C_SMBUS_WRITE) {
438                         /*
439                          * Write Byte
440                          * Command plus 1 data byte
441                          */
442                         dev_dbg(dev, "I2C_SMBUS_BYTE_DATA:  WRITE\n");
443                         desc->wr_len_cmd = 2;
444                         dma_size = 2;
445                         dma_direction = DMA_TO_DEVICE;
446                         priv->dma_buffer[0] = command;
447                         priv->dma_buffer[1] = data->byte;
448                 } else {
449                         /* Read Byte */
450                         dev_dbg(dev, "I2C_SMBUS_BYTE_DATA:  READ\n");
451                         desc->control |= ISMT_DESC_CWRL;
452                         desc->wr_len_cmd = command;
453                         desc->rd_len = 1;
454                         dma_size = 1;
455                         dma_direction = DMA_FROM_DEVICE;
456                 }
457                 break;
458
459         case I2C_SMBUS_WORD_DATA:
460                 if (read_write == I2C_SMBUS_WRITE) {
461                         /* Write Word */
462                         dev_dbg(dev, "I2C_SMBUS_WORD_DATA:  WRITE\n");
463                         desc->wr_len_cmd = 3;
464                         dma_size = 3;
465                         dma_direction = DMA_TO_DEVICE;
466                         priv->dma_buffer[0] = command;
467                         priv->dma_buffer[1] = data->word & 0xff;
468                         priv->dma_buffer[2] = data->word >> 8;
469                 } else {
470                         /* Read Word */
471                         dev_dbg(dev, "I2C_SMBUS_WORD_DATA:  READ\n");
472                         desc->wr_len_cmd = command;
473                         desc->control |= ISMT_DESC_CWRL;
474                         desc->rd_len = 2;
475                         dma_size = 2;
476                         dma_direction = DMA_FROM_DEVICE;
477                 }
478                 break;
479
480         case I2C_SMBUS_PROC_CALL:
481                 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
482                 desc->wr_len_cmd = 3;
483                 desc->rd_len = 2;
484                 dma_size = 3;
485                 dma_direction = DMA_BIDIRECTIONAL;
486                 priv->dma_buffer[0] = command;
487                 priv->dma_buffer[1] = data->word & 0xff;
488                 priv->dma_buffer[2] = data->word >> 8;
489                 break;
490
491         case I2C_SMBUS_BLOCK_DATA:
492                 if (read_write == I2C_SMBUS_WRITE) {
493                         /* Block Write */
494                         dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA:  WRITE\n");
495                         dma_size = data->block[0] + 1;
496                         dma_direction = DMA_TO_DEVICE;
497                         desc->wr_len_cmd = dma_size;
498                         desc->control |= ISMT_DESC_BLK;
499                         priv->dma_buffer[0] = command;
500                         memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1);
501                 } else {
502                         /* Block Read */
503                         dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA:  READ\n");
504                         dma_size = I2C_SMBUS_BLOCK_MAX;
505                         dma_direction = DMA_FROM_DEVICE;
506                         desc->rd_len = dma_size;
507                         desc->wr_len_cmd = command;
508                         desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
509                 }
510                 break;
511
512         case I2C_SMBUS_I2C_BLOCK_DATA:
513                 /* Make sure the length is valid */
514                 if (data->block[0] < 1)
515                         data->block[0] = 1;
516
517                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
518                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
519
520                 if (read_write == I2C_SMBUS_WRITE) {
521                         /* i2c Block Write */
522                         dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA:  WRITE\n");
523                         dma_size = data->block[0] + 1;
524                         dma_direction = DMA_TO_DEVICE;
525                         desc->wr_len_cmd = dma_size;
526                         desc->control |= ISMT_DESC_I2C;
527                         priv->dma_buffer[0] = command;
528                         memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1);
529                 } else {
530                         /* i2c Block Read */
531                         dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA:  READ\n");
532                         dma_size = data->block[0];
533                         dma_direction = DMA_FROM_DEVICE;
534                         desc->rd_len = dma_size;
535                         desc->wr_len_cmd = command;
536                         desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL);
537                         /*
538                          * Per the "Table 15-15. I2C Commands",
539                          * in the External Design Specification (EDS),
540                          * (Document Number: 508084, Revision: 2.0),
541                          * the _rw bit must be 0
542                          */
543                         desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0);
544                 }
545                 break;
546
547         default:
548                 dev_err(dev, "Unsupported transaction %d\n",
549                         size);
550                 return -EOPNOTSUPP;
551         }
552
553         /* map the data buffer */
554         if (dma_size != 0) {
555                 dev_dbg(dev, " dev=%p\n", dev);
556                 dev_dbg(dev, " data=%p\n", data);
557                 dev_dbg(dev, " dma_buffer=%p\n", priv->dma_buffer);
558                 dev_dbg(dev, " dma_size=%d\n", dma_size);
559                 dev_dbg(dev, " dma_direction=%d\n", dma_direction);
560
561                 dma_addr = dma_map_single(dev,
562                                       priv->dma_buffer,
563                                       dma_size,
564                                       dma_direction);
565
566                 if (dma_mapping_error(dev, dma_addr)) {
567                         dev_err(dev, "Error in mapping dma buffer %p\n",
568                                 priv->dma_buffer);
569                         return -EIO;
570                 }
571
572                 dev_dbg(dev, " dma_addr = 0x%016llX\n",
573                         (unsigned long long)dma_addr);
574
575                 desc->dptr_low = lower_32_bits(dma_addr);
576                 desc->dptr_high = upper_32_bits(dma_addr);
577         }
578
579         reinit_completion(&priv->cmp);
580
581         /* Add the descriptor */
582         ismt_submit_desc(priv);
583
584         /* Now we wait for interrupt completion, 1s */
585         ret = wait_for_completion_timeout(&priv->cmp, HZ*1);
586
587         /* unmap the data buffer */
588         if (dma_size != 0)
589                 dma_unmap_single(&adap->dev, dma_addr, dma_size, dma_direction);
590
591         if (unlikely(!ret)) {
592                 dev_err(dev, "completion wait timed out\n");
593                 ret = -ETIMEDOUT;
594                 goto out;
595         }
596
597         /* do any post processing of the descriptor here */
598         ret = ismt_process_desc(desc, data, priv, size, read_write);
599
600 out:
601         /* Update the ring pointer */
602         priv->head++;
603         priv->head %= ISMT_DESC_ENTRIES;
604
605         return ret;
606 }
607
608 /**
609  * ismt_func() - report which i2c commands are supported by this adapter
610  * @adap: the i2c host adapter
611  */
612 static u32 ismt_func(struct i2c_adapter *adap)
613 {
614         return I2C_FUNC_SMBUS_QUICK             |
615                I2C_FUNC_SMBUS_BYTE              |
616                I2C_FUNC_SMBUS_BYTE_DATA         |
617                I2C_FUNC_SMBUS_WORD_DATA         |
618                I2C_FUNC_SMBUS_PROC_CALL         |
619                I2C_FUNC_SMBUS_BLOCK_DATA        |
620                I2C_FUNC_SMBUS_I2C_BLOCK         |
621                I2C_FUNC_SMBUS_PEC;
622 }
623
624 /**
625  * smbus_algorithm - the adapter algorithm and supported functionality
626  * @smbus_xfer: the adapter algorithm
627  * @functionality: functionality supported by the adapter
628  */
629 static const struct i2c_algorithm smbus_algorithm = {
630         .smbus_xfer     = ismt_access,
631         .functionality  = ismt_func,
632 };
633
634 /**
635  * ismt_handle_isr() - interrupt handler bottom half
636  * @priv: iSMT private data
637  */
638 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
639 {
640         complete(&priv->cmp);
641
642         return IRQ_HANDLED;
643 }
644
645
646 /**
647  * ismt_do_interrupt() - IRQ interrupt handler
648  * @vec: interrupt vector
649  * @data: iSMT private data
650  */
651 static irqreturn_t ismt_do_interrupt(int vec, void *data)
652 {
653         u32 val;
654         struct ismt_priv *priv = data;
655
656         /*
657          * check to see it's our interrupt, return IRQ_NONE if not ours
658          * since we are sharing interrupt
659          */
660         val = readl(priv->smba + ISMT_MSTR_MSTS);
661
662         if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
663                 return IRQ_NONE;
664         else
665                 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
666                        priv->smba + ISMT_MSTR_MSTS);
667
668         return ismt_handle_isr(priv);
669 }
670
671 /**
672  * ismt_do_msi_interrupt() - MSI interrupt handler
673  * @vec: interrupt vector
674  * @data: iSMT private data
675  */
676 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
677 {
678         return ismt_handle_isr(data);
679 }
680
681 /**
682  * ismt_hw_init() - initialize the iSMT hardware
683  * @priv: iSMT private data
684  */
685 static void ismt_hw_init(struct ismt_priv *priv)
686 {
687         u32 val;
688         struct device *dev = &priv->pci_dev->dev;
689
690         /* initialize the Master Descriptor Base Address (MDBA) */
691         writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
692
693         /* initialize the Master Control Register (MCTRL) */
694         writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
695
696         /* initialize the Master Status Register (MSTS) */
697         writel(0, priv->smba + ISMT_MSTR_MSTS);
698
699         /* initialize the Master Descriptor Size (MDS) */
700         val = readl(priv->smba + ISMT_MSTR_MDS);
701         writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
702                 priv->smba + ISMT_MSTR_MDS);
703
704         /*
705          * Set the SMBus speed (could use this for slow HW debuggers)
706          */
707
708         val = readl(priv->smba + ISMT_SPGT);
709
710         switch (bus_speed) {
711         case 0:
712                 break;
713
714         case 80:
715                 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
716                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
717                         priv->smba + ISMT_SPGT);
718                 break;
719
720         case 100:
721                 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
722                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
723                         priv->smba + ISMT_SPGT);
724                 break;
725
726         case 400:
727                 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
728                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
729                         priv->smba + ISMT_SPGT);
730                 break;
731
732         case 1000:
733                 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
734                 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
735                         priv->smba + ISMT_SPGT);
736                 break;
737
738         default:
739                 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
740                 break;
741         }
742
743         val = readl(priv->smba + ISMT_SPGT);
744
745         switch (val & ISMT_SPGT_SPD_MASK) {
746         case ISMT_SPGT_SPD_80K:
747                 bus_speed = 80;
748                 break;
749         case ISMT_SPGT_SPD_100K:
750                 bus_speed = 100;
751                 break;
752         case ISMT_SPGT_SPD_400K:
753                 bus_speed = 400;
754                 break;
755         case ISMT_SPGT_SPD_1M:
756                 bus_speed = 1000;
757                 break;
758         }
759         dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
760 }
761
762 /**
763  * ismt_dev_init() - initialize the iSMT data structures
764  * @priv: iSMT private data
765  */
766 static int ismt_dev_init(struct ismt_priv *priv)
767 {
768         /* allocate memory for the descriptor */
769         priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
770                                        (ISMT_DESC_ENTRIES
771                                                * sizeof(struct ismt_desc)),
772                                        &priv->io_rng_dma,
773                                        GFP_KERNEL);
774         if (!priv->hw)
775                 return -ENOMEM;
776
777         memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)));
778
779         priv->head = 0;
780         init_completion(&priv->cmp);
781
782         return 0;
783 }
784
785 /**
786  * ismt_int_init() - initialize interrupts
787  * @priv: iSMT private data
788  */
789 static int ismt_int_init(struct ismt_priv *priv)
790 {
791         int err;
792
793         /* Try using MSI interrupts */
794         err = pci_enable_msi(priv->pci_dev);
795         if (err) {
796                 dev_warn(&priv->pci_dev->dev,
797                          "Unable to use MSI interrupts, falling back to legacy\n");
798                 goto intx;
799         }
800
801         err = devm_request_irq(&priv->pci_dev->dev,
802                                priv->pci_dev->irq,
803                                ismt_do_msi_interrupt,
804                                0,
805                                "ismt-msi",
806                                priv);
807         if (err) {
808                 pci_disable_msi(priv->pci_dev);
809                 goto intx;
810         }
811
812         priv->using_msi = true;
813         goto done;
814
815         /* Try using legacy interrupts */
816 intx:
817         err = devm_request_irq(&priv->pci_dev->dev,
818                                priv->pci_dev->irq,
819                                ismt_do_interrupt,
820                                IRQF_SHARED,
821                                "ismt-intx",
822                                priv);
823         if (err) {
824                 dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
825                 return -ENODEV;
826         }
827
828         priv->using_msi = false;
829
830 done:
831         return 0;
832 }
833
834 static struct pci_driver ismt_driver;
835
836 /**
837  * ismt_probe() - probe for iSMT devices
838  * @pdev: PCI-Express device
839  * @id: PCI-Express device ID
840  */
841 static int
842 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
843 {
844         int err;
845         struct ismt_priv *priv;
846         unsigned long start, len;
847
848         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
849         if (!priv)
850                 return -ENOMEM;
851
852         pci_set_drvdata(pdev, priv);
853         i2c_set_adapdata(&priv->adapter, priv);
854         priv->adapter.owner = THIS_MODULE;
855
856         priv->adapter.class = I2C_CLASS_HWMON;
857
858         priv->adapter.algo = &smbus_algorithm;
859
860         /* set up the sysfs linkage to our parent device */
861         priv->adapter.dev.parent = &pdev->dev;
862
863         /* number of retries on lost arbitration */
864         priv->adapter.retries = ISMT_MAX_RETRIES;
865
866         priv->pci_dev = pdev;
867
868         err = pcim_enable_device(pdev);
869         if (err) {
870                 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
871                         err);
872                 return err;
873         }
874
875         /* enable bus mastering */
876         pci_set_master(pdev);
877
878         /* Determine the address of the SMBus area */
879         start = pci_resource_start(pdev, SMBBAR);
880         len = pci_resource_len(pdev, SMBBAR);
881         if (!start || !len) {
882                 dev_err(&pdev->dev,
883                         "SMBus base address uninitialized, upgrade BIOS\n");
884                 return -ENODEV;
885         }
886
887         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
888                  "SMBus iSMT adapter at %lx", start);
889
890         dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
891         dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
892
893         err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
894         if (err) {
895                 dev_err(&pdev->dev, "ACPI resource conflict!\n");
896                 return err;
897         }
898
899         err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
900         if (err) {
901                 dev_err(&pdev->dev,
902                         "Failed to request SMBus region 0x%lx-0x%lx\n",
903                         start, start + len);
904                 return err;
905         }
906
907         priv->smba = pcim_iomap(pdev, SMBBAR, len);
908         if (!priv->smba) {
909                 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
910                 err = -ENODEV;
911                 goto fail;
912         }
913
914         if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
915             (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
916                 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
917                     (pci_set_consistent_dma_mask(pdev,
918                                                  DMA_BIT_MASK(32)) != 0)) {
919                         dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n",
920                                 pdev);
921                         err = -ENODEV;
922                         goto fail;
923                 }
924         }
925
926         err = ismt_dev_init(priv);
927         if (err)
928                 goto fail;
929
930         ismt_hw_init(priv);
931
932         err = ismt_int_init(priv);
933         if (err)
934                 goto fail;
935
936         err = i2c_add_adapter(&priv->adapter);
937         if (err) {
938                 dev_err(&pdev->dev, "Failed to add SMBus iSMT adapter\n");
939                 err = -ENODEV;
940                 goto fail;
941         }
942         return 0;
943
944 fail:
945         pci_release_region(pdev, SMBBAR);
946         return err;
947 }
948
949 /**
950  * ismt_remove() - release driver resources
951  * @pdev: PCI-Express device
952  */
953 static void ismt_remove(struct pci_dev *pdev)
954 {
955         struct ismt_priv *priv = pci_get_drvdata(pdev);
956
957         i2c_del_adapter(&priv->adapter);
958         pci_release_region(pdev, SMBBAR);
959 }
960
961 /**
962  * ismt_suspend() - place the device in suspend
963  * @pdev: PCI-Express device
964  * @mesg: PM message
965  */
966 #ifdef CONFIG_PM
967 static int ismt_suspend(struct pci_dev *pdev, pm_message_t mesg)
968 {
969         pci_save_state(pdev);
970         pci_set_power_state(pdev, pci_choose_state(pdev, mesg));
971         return 0;
972 }
973
974 /**
975  * ismt_resume() - PCI resume code
976  * @pdev: PCI-Express device
977  */
978 static int ismt_resume(struct pci_dev *pdev)
979 {
980         pci_set_power_state(pdev, PCI_D0);
981         pci_restore_state(pdev);
982         return pci_enable_device(pdev);
983 }
984
985 #else
986
987 #define ismt_suspend NULL
988 #define ismt_resume NULL
989
990 #endif
991
992 static struct pci_driver ismt_driver = {
993         .name = "ismt_smbus",
994         .id_table = ismt_ids,
995         .probe = ismt_probe,
996         .remove = ismt_remove,
997         .suspend = ismt_suspend,
998         .resume = ismt_resume,
999 };
1000
1001 module_pci_driver(ismt_driver);
1002
1003 MODULE_LICENSE("Dual BSD/GPL");
1004 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
1005 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");