drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21  * Supports the following Intel I/O Controller Hubs (ICH):
  22  *
  23  *                                      I/O                     Block   I2C
  24  *                                      region  SMBus   Block   proc.   block
  25  * Chip name                    PCI ID  size    PEC     buffer  call    read
  26  * ---------------------------------------------------------------------------
  27  * 82801AA (ICH)                0x2413  16      no      no      no      no
  28  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40  * ICH10                        0x3a30  32      hard    yes     yes     yes
  41  * ICH10                        0x3a60  32      hard    yes     yes     yes
  42  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  62  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  63  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  64  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  65  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  66  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  67  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  68  *
  69  * Features supported by this driver:
  70  * Software PEC                         no
  71  * Hardware PEC                         yes
  72  * Block buffer                         yes
  73  * Block process call transaction       no
  74  * I2C block read transaction           yes (doesn't use the block buffer)
  75  * Slave mode                           no
  76  * SMBus Host Notify                    yes
  77  * Interrupt processing                 yes
  78  *
  79  * See the file Documentation/i2c/busses/i2c-i801 for details.
  80  */
  81
  82 #include <linux/interrupt.h>
  83 #include <linux/module.h>
  84 #include <linux/pci.h>
  85 #include <linux/kernel.h>
  86 #include <linux/stddef.h>
  87 #include <linux/delay.h>
  88 #include <linux/ioport.h>
  89 #include <linux/init.h>
  90 #include <linux/i2c.h>
  91 #include <linux/i2c-smbus.h>
  92 #include <linux/acpi.h>
  93 #include <linux/io.h>
  94 #include <linux/dmi.h>
  95 #include <linux/slab.h>
  96 #include <linux/wait.h>
  97 #include <linux/err.h>
  98 #include <linux/platform_device.h>
  99 #include <linux/platform_data/itco_wdt.h>
 100 #include <linux/pm_runtime.h>
 101
 102 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 103 #include <linux/gpio.h>
 104 #include <linux/i2c-mux-gpio.h>
 105 #endif
 106
 107 /* I801 SMBus address offsets */
 108 #define SMBHSTSTS(p)    (0 + (p)->smba)
 109 #define SMBHSTCNT(p)    (2 + (p)->smba)
 110 #define SMBHSTCMD(p)    (3 + (p)->smba)
 111 #define SMBHSTADD(p)    (4 + (p)->smba)
 112 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 113 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 114 #define SMBBLKDAT(p)    (7 + (p)->smba)
 115 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 116 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 117 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 118 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 119 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 120 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 121 #define SMBNTFDDAT(p)   (22 + (p)->smba)        /* ICH3 and later */
 122
 123 /* PCI Address Constants */
 124 #define SMBBAR          4
 125 #define SMBPCICTL       0x004
 126 #define SMBPCISTS       0x006
 127 #define SMBHSTCFG       0x040
 128 #define TCOBASE         0x050
 129 #define TCOCTL          0x054
 130
 131 #define ACPIBASE                0x040
 132 #define ACPIBASE_SMI_OFF        0x030
 133 #define ACPICTRL                0x044
 134 #define ACPICTRL_EN             0x080
 135
 136 #define SBREG_BAR               0x10
 137 #define SBREG_SMBCTRL           0xc6000c
 138
 139 /* Host status bits for SMBPCISTS */
 140 #define SMBPCISTS_INTS          0x08
 141
 142 /* Control bits for SMBPCICTL */
 143 #define SMBPCICTL_INTDIS        0x0400
 144
 145 /* Host configuration bits for SMBHSTCFG */
 146 #define SMBHSTCFG_HST_EN        1
 147 #define SMBHSTCFG_SMB_SMI_EN    2
 148 #define SMBHSTCFG_I2C_EN        4
 149
 150 /* TCO configuration bits for TCOCTL */
 151 #define TCOCTL_EN               0x0100
 152
 153 /* Auxiliary status register bits, ICH4+ only */
 154 #define SMBAUXSTS_CRCE          1
 155 #define SMBAUXSTS_STCO          2
 156
 157 /* Auxiliary control register bits, ICH4+ only */
 158 #define SMBAUXCTL_CRC           1
 159 #define SMBAUXCTL_E32B          2
 160
 161 /* Other settings */
 162 #define MAX_RETRIES             400
 163
 164 /* I801 command constants */
 165 #define I801_QUICK              0x00
 166 #define I801_BYTE               0x04
 167 #define I801_BYTE_DATA          0x08
 168 #define I801_WORD_DATA          0x0C
 169 #define I801_PROC_CALL          0x10    /* unimplemented */
 170 #define I801_BLOCK_DATA         0x14
 171 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 172
 173 /* I801 Host Control register bits */
 174 #define SMBHSTCNT_INTREN        0x01
 175 #define SMBHSTCNT_KILL          0x02
 176 #define SMBHSTCNT_LAST_BYTE     0x20
 177 #define SMBHSTCNT_START         0x40
 178 #define SMBHSTCNT_PEC_EN        0x80    /* ICH3 and later */
 179
 180 /* I801 Hosts Status register bits */
 181 #define SMBHSTSTS_BYTE_DONE     0x80
 182 #define SMBHSTSTS_INUSE_STS     0x40
 183 #define SMBHSTSTS_SMBALERT_STS  0x20
 184 #define SMBHSTSTS_FAILED        0x10
 185 #define SMBHSTSTS_BUS_ERR       0x08
 186 #define SMBHSTSTS_DEV_ERR       0x04
 187 #define SMBHSTSTS_INTR          0x02
 188 #define SMBHSTSTS_HOST_BUSY     0x01
 189
 190 /* Host Notify Status registers bits */
 191 #define SMBSLVSTS_HST_NTFY_STS  1
 192
 193 /* Host Notify Command registers bits */
 194 #define SMBSLVCMD_HST_NTFY_INTREN       0x01
 195
 196 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 197                                  SMBHSTSTS_DEV_ERR)
 198
 199 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 200                                  STATUS_ERROR_FLAGS)
 201
 202 /* Older devices have their ID defined in <linux/pci_ids.h> */
 203 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 204 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 205 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 206 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 207 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 208 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 209 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 210 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 211 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 212 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 213 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 214 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 215 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 216 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 217 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 218 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 219 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 220 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 221 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 222 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 223 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 224 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 225 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 226 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 227 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 228 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 229 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 230 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 231
 232 struct i801_mux_config {
 233         char *gpio_chip;
 234         unsigned values[3];
 235         int n_values;
 236         unsigned classes[3];
 237         unsigned gpios[2];              /* Relative to gpio_chip->base */
 238         int n_gpios;
 239 };
 240
 241 struct i801_priv {
 242         struct i2c_adapter adapter;
 243         unsigned long smba;
 244         unsigned char original_hstcfg;
 245         struct pci_dev *pci_dev;
 246         unsigned int features;
 247
 248         /* isr processing */
 249         wait_queue_head_t waitq;
 250         u8 status;
 251
 252         /* Command state used by isr for byte-by-byte block transactions */
 253         u8 cmd;
 254         bool is_read;
 255         int count;
 256         int len;
 257         u8 *data;
 258
 259 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 260         const struct i801_mux_config *mux_drvdata;
 261         struct platform_device *mux_pdev;
 262 #endif
 263         struct platform_device *tco_pdev;
 264
 265         /*
 266          * If set to true the host controller registers are reserved for
 267          * ACPI AML use. Protected by acpi_lock.
 268          */
 269         bool acpi_reserved;
 270         struct mutex acpi_lock;
 271         struct smbus_host_notify *host_notify;
 272 };
 273
 274 #define SMBHSTNTFY_SIZE         8
 275
 276 #define FEATURE_SMBUS_PEC       (1 << 0)
 277 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 278 #define FEATURE_BLOCK_PROC      (1 << 2)
 279 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 280 #define FEATURE_IRQ             (1 << 4)
 281 #define FEATURE_HOST_NOTIFY     (1 << 5)
 282 /* Not really a feature, but it's convenient to handle it as such */
 283 #define FEATURE_IDF             (1 << 15)
 284 #define FEATURE_TCO             (1 << 16)
 285
 286 static const char *i801_feature_names[] = {
 287         "SMBus PEC",
 288         "Block buffer",
 289         "Block process call",
 290         "I2C block read",
 291         "Interrupt",
 292         "SMBus Host Notify",
 293 };
 294
 295 static unsigned int disable_features;
 296 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 297 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 298         "\t\t  0x01  disable SMBus PEC\n"
 299         "\t\t  0x02  disable the block buffer\n"
 300         "\t\t  0x08  disable the I2C block read functionality\n"
 301         "\t\t  0x10  don't use interrupts\n"
 302         "\t\t  0x20  disable SMBus Host Notify ");
 303
 304 /* Make sure the SMBus host is ready to start transmitting.
 305    Return 0 if it is, -EBUSY if it is not. */
 306 static int i801_check_pre(struct i801_priv *priv)
 307 {
 308         int status;
 309
 310         status = inb_p(SMBHSTSTS(priv));
 311         if (status & SMBHSTSTS_HOST_BUSY) {
 312                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 313                 return -EBUSY;
 314         }
 315
 316         status &= STATUS_FLAGS;
 317         if (status) {
 318                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 319                         status);
 320                 outb_p(status, SMBHSTSTS(priv));
 321                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 322                 if (status) {
 323                         dev_err(&priv->pci_dev->dev,
 324                                 "Failed clearing status flags (%02x)\n",
 325                                 status);
 326                         return -EBUSY;
 327                 }
 328         }
 329
 330         /*
 331          * Clear CRC status if needed.
 332          * During normal operation, i801_check_post() takes care
 333          * of it after every operation.  We do it here only in case
 334          * the hardware was already in this state when the driver
 335          * started.
 336          */
 337         if (priv->features & FEATURE_SMBUS_PEC) {
 338                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 339                 if (status) {
 340                         dev_dbg(&priv->pci_dev->dev,
 341                                 "Clearing aux status flags (%02x)\n", status);
 342                         outb_p(status, SMBAUXSTS(priv));
 343                         status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 344                         if (status) {
 345                                 dev_err(&priv->pci_dev->dev,
 346                                         "Failed clearing aux status flags (%02x)\n",
 347                                         status);
 348                                 return -EBUSY;
 349                         }
 350                 }
 351         }
 352
 353         return 0;
 354 }
 355
 356 /*
 357  * Convert the status register to an error code, and clear it.
 358  * Note that status only contains the bits we want to clear, not the
 359  * actual register value.
 360  */
 361 static int i801_check_post(struct i801_priv *priv, int status)
 362 {
 363         int result = 0;
 364
 365         /*
 366          * If the SMBus is still busy, we give up
 367          * Note: This timeout condition only happens when using polling
 368          * transactions.  For interrupt operation, NAK/timeout is indicated by
 369          * DEV_ERR.
 370          */
 371         if (unlikely(status < 0)) {
 372                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 373                 /* try to stop the current command */
 374                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 375                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 376                        SMBHSTCNT(priv));
 377                 usleep_range(1000, 2000);
 378                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 379                        SMBHSTCNT(priv));
 380
 381                 /* Check if it worked */
 382                 status = inb_p(SMBHSTSTS(priv));
 383                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 384                     !(status & SMBHSTSTS_FAILED))
 385                         dev_err(&priv->pci_dev->dev,
 386                                 "Failed terminating the transaction\n");
 387                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 388                 return -ETIMEDOUT;
 389         }
 390
 391         if (status & SMBHSTSTS_FAILED) {
 392                 result = -EIO;
 393                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 394         }
 395         if (status & SMBHSTSTS_DEV_ERR) {
 396                 /*
 397                  * This may be a PEC error, check and clear it.
 398                  *
 399                  * AUXSTS is handled differently from HSTSTS.
 400                  * For HSTSTS, i801_isr() or i801_wait_intr()
 401                  * has already cleared the error bits in hardware,
 402                  * and we are passed a copy of the original value
 403                  * in "status".
 404                  * For AUXSTS, the hardware register is left
 405                  * for us to handle here.
 406                  * This is asymmetric, slightly iffy, but safe,
 407                  * since all this code is serialized and the CRCE
 408                  * bit is harmless as long as it's cleared before
 409                  * the next operation.
 410                  */
 411                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 412                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 413                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 414                         result = -EBADMSG;
 415                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 416                 } else {
 417                         result = -ENXIO;
 418                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 419                 }
 420         }
 421         if (status & SMBHSTSTS_BUS_ERR) {
 422                 result = -EAGAIN;
 423                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 424         }
 425
 426         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 427         outb_p(status, SMBHSTSTS(priv));
 428
 429         return result;
 430 }
 431
 432 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 433 static int i801_wait_intr(struct i801_priv *priv)
 434 {
 435         int timeout = 0;
 436         int status;
 437
 438         /* We will always wait for a fraction of a second! */
 439         do {
 440                 usleep_range(250, 500);
 441                 status = inb_p(SMBHSTSTS(priv));
 442         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 443                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 444                  (timeout++ < MAX_RETRIES));
 445
 446         if (timeout > MAX_RETRIES) {
 447                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 448                 return -ETIMEDOUT;
 449         }
 450         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 451 }
 452
 453 /* Wait for either BYTE_DONE or an error flag being set */
 454 static int i801_wait_byte_done(struct i801_priv *priv)
 455 {
 456         int timeout = 0;
 457         int status;
 458
 459         /* We will always wait for a fraction of a second! */
 460         do {
 461                 usleep_range(250, 500);
 462                 status = inb_p(SMBHSTSTS(priv));
 463         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 464                  (timeout++ < MAX_RETRIES));
 465
 466         if (timeout > MAX_RETRIES) {
 467                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 468                 return -ETIMEDOUT;
 469         }
 470         return status & STATUS_ERROR_FLAGS;
 471 }
 472
 473 static int i801_transaction(struct i801_priv *priv, int xact)
 474 {
 475         int status;
 476         int result;
 477         const struct i2c_adapter *adap = &priv->adapter;
 478
 479         result = i801_check_pre(priv);
 480         if (result < 0)
 481                 return result;
 482
 483         if (priv->features & FEATURE_IRQ) {
 484                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 485                        SMBHSTCNT(priv));
 486                 result = wait_event_timeout(priv->waitq,
 487                                             (status = priv->status),
 488                                             adap->timeout);
 489                 if (!result) {
 490                         status = -ETIMEDOUT;
 491                         dev_warn(&priv->pci_dev->dev,
 492                                  "Timeout waiting for interrupt!\n");
 493                 }
 494                 priv->status = 0;
 495                 return i801_check_post(priv, status);
 496         }
 497
 498         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 499          * SMBSCMD are passed in xact */
 500         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 501
 502         status = i801_wait_intr(priv);
 503         return i801_check_post(priv, status);
 504 }
 505
 506 static int i801_block_transaction_by_block(struct i801_priv *priv,
 507                                            union i2c_smbus_data *data,
 508                                            char read_write, int hwpec)
 509 {
 510         int i, len;
 511         int status;
 512
 513         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 514
 515         /* Use 32-byte buffer to process this transaction */
 516         if (read_write == I2C_SMBUS_WRITE) {
 517                 len = data->block[0];
 518                 outb_p(len, SMBHSTDAT0(priv));
 519                 for (i = 0; i < len; i++)
 520                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 521         }
 522
 523         status = i801_transaction(priv, I801_BLOCK_DATA |
 524                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 525         if (status)
 526                 return status;
 527
 528         if (read_write == I2C_SMBUS_READ) {
 529                 len = inb_p(SMBHSTDAT0(priv));
 530                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 531                         return -EPROTO;
 532
 533                 data->block[0] = len;
 534                 for (i = 0; i < len; i++)
 535                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 536         }
 537         return 0;
 538 }
 539
 540 static void i801_isr_byte_done(struct i801_priv *priv)
 541 {
 542         if (priv->is_read) {
 543                 /* For SMBus block reads, length is received with first byte */
 544                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 545                     (priv->count == 0)) {
 546                         priv->len = inb_p(SMBHSTDAT0(priv));
 547                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 548                                 dev_err(&priv->pci_dev->dev,
 549                                         "Illegal SMBus block read size %d\n",
 550                                         priv->len);
 551                                 /* FIXME: Recover */
 552                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 553                         } else {
 554                                 dev_dbg(&priv->pci_dev->dev,
 555                                         "SMBus block read size is %d\n",
 556                                         priv->len);
 557                         }
 558                         priv->data[-1] = priv->len;
 559                 }
 560
 561                 /* Read next byte */
 562                 if (priv->count < priv->len)
 563                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 564                 else
 565                         dev_dbg(&priv->pci_dev->dev,
 566                                 "Discarding extra byte on block read\n");
 567
 568                 /* Set LAST_BYTE for last byte of read transaction */
 569                 if (priv->count == priv->len - 1)
 570                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 571                                SMBHSTCNT(priv));
 572         } else if (priv->count < priv->len - 1) {
 573                 /* Write next byte, except for IRQ after last byte */
 574                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 575         }
 576
 577         /* Clear BYTE_DONE to continue with next byte */
 578         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 579 }
 580
 581 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 582 {
 583         unsigned short addr;
 584         unsigned int data;
 585
 586         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 587         data = inw_p(SMBNTFDDAT(priv));
 588
 589         i2c_handle_smbus_host_notify(priv->host_notify, addr, data);
 590
 591         /* clear Host Notify bit and return */
 592         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 593         return IRQ_HANDLED;
 594 }
 595
 596 /*
 597  * There are three kinds of interrupts:
 598  *
 599  * 1) i801 signals transaction completion with one of these interrupts:
 600  *      INTR - Success
 601  *      DEV_ERR - Invalid command, NAK or communication timeout
 602  *      BUS_ERR - SMI# transaction collision
 603  *      FAILED - transaction was canceled due to a KILL request
 604  *    When any of these occur, update ->status and wake up the waitq.
 605  *    ->status must be cleared before kicking off the next transaction.
 606  *
 607  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 608  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 609  *
 610  * 3) Host Notify interrupts
 611  */
 612 static irqreturn_t i801_isr(int irq, void *dev_id)
 613 {
 614         struct i801_priv *priv = dev_id;
 615         u16 pcists;
 616         u8 status;
 617
 618         /* Confirm this is our interrupt */
 619         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 620         if (!(pcists & SMBPCISTS_INTS))
 621                 return IRQ_NONE;
 622
 623         if (priv->features & FEATURE_HOST_NOTIFY) {
 624                 status = inb_p(SMBSLVSTS(priv));
 625                 if (status & SMBSLVSTS_HST_NTFY_STS)
 626                         return i801_host_notify_isr(priv);
 627         }
 628
 629         status = inb_p(SMBHSTSTS(priv));
 630         if (status & SMBHSTSTS_BYTE_DONE)
 631                 i801_isr_byte_done(priv);
 632
 633         /*
 634          * Clear irq sources and report transaction result.
 635          * ->status must be cleared before the next transaction is started.
 636          */
 637         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 638         if (status) {
 639                 outb_p(status, SMBHSTSTS(priv));
 640                 priv->status = status;
 641                 wake_up(&priv->waitq);
 642         }
 643
 644         return IRQ_HANDLED;
 645 }
 646
 647 /*
 648  * For "byte-by-byte" block transactions:
 649  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 650  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 651  */
 652 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 653                                                union i2c_smbus_data *data,
 654                                                char read_write, int command,
 655                                                int hwpec)
 656 {
 657         int i, len;
 658         int smbcmd;
 659         int status;
 660         int result;
 661         const struct i2c_adapter *adap = &priv->adapter;
 662
 663         result = i801_check_pre(priv);
 664         if (result < 0)
 665                 return result;
 666
 667         len = data->block[0];
 668
 669         if (read_write == I2C_SMBUS_WRITE) {
 670                 outb_p(len, SMBHSTDAT0(priv));
 671                 outb_p(data->block[1], SMBBLKDAT(priv));
 672         }
 673
 674         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 675             read_write == I2C_SMBUS_READ)
 676                 smbcmd = I801_I2C_BLOCK_DATA;
 677         else
 678                 smbcmd = I801_BLOCK_DATA;
 679
 680         if (priv->features & FEATURE_IRQ) {
 681                 priv->is_read = (read_write == I2C_SMBUS_READ);
 682                 if (len == 1 && priv->is_read)
 683                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 684                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 685                 priv->len = len;
 686                 priv->count = 0;
 687                 priv->data = &data->block[1];
 688
 689                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 690                 result = wait_event_timeout(priv->waitq,
 691                                             (status = priv->status),
 692                                             adap->timeout);
 693                 if (!result) {
 694                         status = -ETIMEDOUT;
 695                         dev_warn(&priv->pci_dev->dev,
 696                                  "Timeout waiting for interrupt!\n");
 697                 }
 698                 priv->status = 0;
 699                 return i801_check_post(priv, status);
 700         }
 701
 702         for (i = 1; i <= len; i++) {
 703                 if (i == len && read_write == I2C_SMBUS_READ)
 704                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 705                 outb_p(smbcmd, SMBHSTCNT(priv));
 706
 707                 if (i == 1)
 708                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 709                                SMBHSTCNT(priv));
 710
 711                 status = i801_wait_byte_done(priv);
 712                 if (status)
 713                         goto exit;
 714
 715                 if (i == 1 && read_write == I2C_SMBUS_READ
 716                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 717                         len = inb_p(SMBHSTDAT0(priv));
 718                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 719                                 dev_err(&priv->pci_dev->dev,
 720                                         "Illegal SMBus block read size %d\n",
 721                                         len);
 722                                 /* Recover */
 723                                 while (inb_p(SMBHSTSTS(priv)) &
 724                                        SMBHSTSTS_HOST_BUSY)
 725                                         outb_p(SMBHSTSTS_BYTE_DONE,
 726                                                SMBHSTSTS(priv));
 727                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 728                                 return -EPROTO;
 729                         }
 730                         data->block[0] = len;
 731                 }
 732
 733                 /* Retrieve/store value in SMBBLKDAT */
 734                 if (read_write == I2C_SMBUS_READ)
 735                         data->block[i] = inb_p(SMBBLKDAT(priv));
 736                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 737                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 738
 739                 /* signals SMBBLKDAT ready */
 740                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 741         }
 742
 743         status = i801_wait_intr(priv);
 744 exit:
 745         return i801_check_post(priv, status);
 746 }
 747
 748 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 749 {
 750         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 751         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 752                 return -EIO;
 753         return 0;
 754 }
 755
 756 /* Block transaction function */
 757 static int i801_block_transaction(struct i801_priv *priv,
 758                                   union i2c_smbus_data *data, char read_write,
 759                                   int command, int hwpec)
 760 {
 761         int result = 0;
 762         unsigned char hostc;
 763
 764         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 765                 if (read_write == I2C_SMBUS_WRITE) {
 766                         /* set I2C_EN bit in configuration register */
 767                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 768                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 769                                               hostc | SMBHSTCFG_I2C_EN);
 770                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 771                         dev_err(&priv->pci_dev->dev,
 772                                 "I2C block read is unsupported!\n");
 773                         return -EOPNOTSUPP;
 774                 }
 775         }
 776
 777         if (read_write == I2C_SMBUS_WRITE
 778          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 779                 if (data->block[0] < 1)
 780                         data->block[0] = 1;
 781                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 782                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 783         } else {
 784                 data->block[0] = 32;    /* max for SMBus block reads */
 785         }
 786
 787         /* Experience has shown that the block buffer can only be used for
 788            SMBus (not I2C) block transactions, even though the datasheet
 789            doesn't mention this limitation. */
 790         if ((priv->features & FEATURE_BLOCK_BUFFER)
 791          && command != I2C_SMBUS_I2C_BLOCK_DATA
 792          && i801_set_block_buffer_mode(priv) == 0)
 793                 result = i801_block_transaction_by_block(priv, data,
 794                                                          read_write, hwpec);
 795         else
 796                 result = i801_block_transaction_byte_by_byte(priv, data,
 797                                                              read_write,
 798                                                              command, hwpec);
 799
 800         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 801          && read_write == I2C_SMBUS_WRITE) {
 802                 /* restore saved configuration register value */
 803                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 804         }
 805         return result;
 806 }
 807
 808 /* Return negative errno on error. */
 809 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 810                        unsigned short flags, char read_write, u8 command,
 811                        int size, union i2c_smbus_data *data)
 812 {
 813         int hwpec;
 814         int block = 0;
 815         int ret = 0, xact = 0;
 816         struct i801_priv *priv = i2c_get_adapdata(adap);
 817
 818         mutex_lock(&priv->acpi_lock);
 819         if (priv->acpi_reserved) {
 820                 mutex_unlock(&priv->acpi_lock);
 821                 return -EBUSY;
 822         }
 823
 824         pm_runtime_get_sync(&priv->pci_dev->dev);
 825
 826         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 827                 && size != I2C_SMBUS_QUICK
 828                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 829
 830         switch (size) {
 831         case I2C_SMBUS_QUICK:
 832                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 833                        SMBHSTADD(priv));
 834                 xact = I801_QUICK;
 835                 break;
 836         case I2C_SMBUS_BYTE:
 837                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 838                        SMBHSTADD(priv));
 839                 if (read_write == I2C_SMBUS_WRITE)
 840                         outb_p(command, SMBHSTCMD(priv));
 841                 xact = I801_BYTE;
 842                 break;
 843         case I2C_SMBUS_BYTE_DATA:
 844                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 845                        SMBHSTADD(priv));
 846                 outb_p(command, SMBHSTCMD(priv));
 847                 if (read_write == I2C_SMBUS_WRITE)
 848                         outb_p(data->byte, SMBHSTDAT0(priv));
 849                 xact = I801_BYTE_DATA;
 850                 break;
 851         case I2C_SMBUS_WORD_DATA:
 852                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 853                        SMBHSTADD(priv));
 854                 outb_p(command, SMBHSTCMD(priv));
 855                 if (read_write == I2C_SMBUS_WRITE) {
 856                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 857                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 858                 }
 859                 xact = I801_WORD_DATA;
 860                 break;
 861         case I2C_SMBUS_BLOCK_DATA:
 862                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 863                        SMBHSTADD(priv));
 864                 outb_p(command, SMBHSTCMD(priv));
 865                 block = 1;
 866                 break;
 867         case I2C_SMBUS_I2C_BLOCK_DATA:
 868                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 869                  * bit should be cleared here, even when reading */
 870                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 871                 if (read_write == I2C_SMBUS_READ) {
 872                         /* NB: page 240 of ICH5 datasheet also shows
 873                          * that DATA1 is the cmd field when reading */
 874                         outb_p(command, SMBHSTDAT1(priv));
 875                 } else
 876                         outb_p(command, SMBHSTCMD(priv));
 877                 block = 1;
 878                 break;
 879         default:
 880                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 881                         size);
 882                 ret = -EOPNOTSUPP;
 883                 goto out;
 884         }
 885
 886         if (hwpec)      /* enable/disable hardware PEC */
 887                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 888         else
 889                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 890                        SMBAUXCTL(priv));
 891
 892         if (block)
 893                 ret = i801_block_transaction(priv, data, read_write, size,
 894                                              hwpec);
 895         else
 896                 ret = i801_transaction(priv, xact);
 897
 898         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 899            time, so we forcibly disable it after every transaction. Turn off
 900            E32B for the same reason. */
 901         if (hwpec || block)
 902                 outb_p(inb_p(SMBAUXCTL(priv)) &
 903                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 904
 905         if (block)
 906                 goto out;
 907         if (ret)
 908                 goto out;
 909         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 910                 goto out;
 911
 912         switch (xact & 0x7f) {
 913         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 914         case I801_BYTE_DATA:
 915                 data->byte = inb_p(SMBHSTDAT0(priv));
 916                 break;
 917         case I801_WORD_DATA:
 918                 data->word = inb_p(SMBHSTDAT0(priv)) +
 919                              (inb_p(SMBHSTDAT1(priv)) << 8);
 920                 break;
 921         }
 922
 923 out:
 924         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 925         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 926         mutex_unlock(&priv->acpi_lock);
 927         return ret;
 928 }
 929
 930
 931 static u32 i801_func(struct i2c_adapter *adapter)
 932 {
 933         struct i801_priv *priv = i2c_get_adapdata(adapter);
 934
 935         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 936                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 937                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 938                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 939                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 940                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 941                ((priv->features & FEATURE_HOST_NOTIFY) ?
 942                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 943 }
 944
 945 static int i801_enable_host_notify(struct i2c_adapter *adapter)
 946 {
 947         struct i801_priv *priv = i2c_get_adapdata(adapter);
 948
 949         if (!(priv->features & FEATURE_HOST_NOTIFY))
 950                 return -ENOTSUPP;
 951
 952         if (!priv->host_notify)
 953                 priv->host_notify = i2c_setup_smbus_host_notify(adapter);
 954         if (!priv->host_notify)
 955                 return -ENOMEM;
 956
 957         outb_p(SMBSLVCMD_HST_NTFY_INTREN, SMBSLVCMD(priv));
 958         /* clear Host Notify bit to allow a new notification */
 959         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 960
 961         return 0;
 962 }
 963
 964 static const struct i2c_algorithm smbus_algorithm = {
 965         .smbus_xfer     = i801_access,
 966         .functionality  = i801_func,
 967 };
 968
 969 static const struct pci_device_id i801_ids[] = {
 970         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 971         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 972         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 973         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 974         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 975         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 976         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 977         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 978         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 979         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 980         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 981         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 982         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 983         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 984         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 985         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 986         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 987         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 988         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 989         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 990         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 991         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 992         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 993         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 994         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 995         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 996         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 997         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 998         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 999         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1000         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1001         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1002         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1003         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1004         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1005         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1006         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1007         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1008         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1009         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1010         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1011         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1012         { 0, }
1013 };
1014
1015 MODULE_DEVICE_TABLE(pci, i801_ids);
1016
1017 #if defined CONFIG_X86 && defined CONFIG_DMI
1018 static unsigned char apanel_addr;
1019
1020 /* Scan the system ROM for the signature "FJKEYINF" */
1021 static __init const void __iomem *bios_signature(const void __iomem *bios)
1022 {
1023         ssize_t offset;
1024         const unsigned char signature[] = "FJKEYINF";
1025
1026         for (offset = 0; offset < 0x10000; offset += 0x10) {
1027                 if (check_signature(bios + offset, signature,
1028                                     sizeof(signature)-1))
1029                         return bios + offset;
1030         }
1031         return NULL;
1032 }
1033
1034 static void __init input_apanel_init(void)
1035 {
1036         void __iomem *bios;
1037         const void __iomem *p;
1038
1039         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1040         p = bios_signature(bios);
1041         if (p) {
1042                 /* just use the first address */
1043                 apanel_addr = readb(p + 8 + 3) >> 1;
1044         }
1045         iounmap(bios);
1046 }
1047
1048 struct dmi_onboard_device_info {
1049         const char *name;
1050         u8 type;
1051         unsigned short i2c_addr;
1052         const char *i2c_type;
1053 };
1054
1055 static const struct dmi_onboard_device_info dmi_devices[] = {
1056         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1057         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1058         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1059 };
1060
1061 static void dmi_check_onboard_device(u8 type, const char *name,
1062                                      struct i2c_adapter *adap)
1063 {
1064         int i;
1065         struct i2c_board_info info;
1066
1067         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1068                 /* & ~0x80, ignore enabled/disabled bit */
1069                 if ((type & ~0x80) != dmi_devices[i].type)
1070                         continue;
1071                 if (strcasecmp(name, dmi_devices[i].name))
1072                         continue;
1073
1074                 memset(&info, 0, sizeof(struct i2c_board_info));
1075                 info.addr = dmi_devices[i].i2c_addr;
1076                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1077                 i2c_new_device(adap, &info);
1078                 break;
1079         }
1080 }
1081
1082 /* We use our own function to check for onboard devices instead of
1083    dmi_find_device() as some buggy BIOS's have the devices we are interested
1084    in marked as disabled */
1085 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1086 {
1087         int i, count;
1088
1089         if (dm->type != 10)
1090                 return;
1091
1092         count = (dm->length - sizeof(struct dmi_header)) / 2;
1093         for (i = 0; i < count; i++) {
1094                 const u8 *d = (char *)(dm + 1) + (i * 2);
1095                 const char *name = ((char *) dm) + dm->length;
1096                 u8 type = d[0];
1097                 u8 s = d[1];
1098
1099                 if (!s)
1100                         continue;
1101                 s--;
1102                 while (s > 0 && name[0]) {
1103                         name += strlen(name) + 1;
1104                         s--;
1105                 }
1106                 if (name[0] == 0) /* Bogus string reference */
1107                         continue;
1108
1109                 dmi_check_onboard_device(type, name, adap);
1110         }
1111 }
1112
1113 /* Register optional slaves */
1114 static void i801_probe_optional_slaves(struct i801_priv *priv)
1115 {
1116         /* Only register slaves on main SMBus channel */
1117         if (priv->features & FEATURE_IDF)
1118                 return;
1119
1120         if (apanel_addr) {
1121                 struct i2c_board_info info;
1122
1123                 memset(&info, 0, sizeof(struct i2c_board_info));
1124                 info.addr = apanel_addr;
1125                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1126                 i2c_new_device(&priv->adapter, &info);
1127         }
1128
1129         if (dmi_name_in_vendors("FUJITSU"))
1130                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1131 }
1132 #else
1133 static void __init input_apanel_init(void) {}
1134 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1135 #endif  /* CONFIG_X86 && CONFIG_DMI */
1136
1137 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1138 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1139         .gpio_chip = "gpio_ich",
1140         .values = { 0x02, 0x03 },
1141         .n_values = 2,
1142         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1143         .gpios = { 52, 53 },
1144         .n_gpios = 2,
1145 };
1146
1147 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1148         .gpio_chip = "gpio_ich",
1149         .values = { 0x02, 0x03, 0x01 },
1150         .n_values = 3,
1151         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1152         .gpios = { 52, 53 },
1153         .n_gpios = 2,
1154 };
1155
1156 static const struct dmi_system_id mux_dmi_table[] = {
1157         {
1158                 .matches = {
1159                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1160                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1161                 },
1162                 .driver_data = &i801_mux_config_asus_z8_d12,
1163         },
1164         {
1165                 .matches = {
1166                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1167                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1168                 },
1169                 .driver_data = &i801_mux_config_asus_z8_d12,
1170         },
1171         {
1172                 .matches = {
1173                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1174                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1175                 },
1176                 .driver_data = &i801_mux_config_asus_z8_d12,
1177         },
1178         {
1179                 .matches = {
1180                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1181                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1182                 },
1183                 .driver_data = &i801_mux_config_asus_z8_d12,
1184         },
1185         {
1186                 .matches = {
1187                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1188                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1189                 },
1190                 .driver_data = &i801_mux_config_asus_z8_d12,
1191         },
1192         {
1193                 .matches = {
1194                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1195                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1196                 },
1197                 .driver_data = &i801_mux_config_asus_z8_d12,
1198         },
1199         {
1200                 .matches = {
1201                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1202                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1203                 },
1204                 .driver_data = &i801_mux_config_asus_z8_d18,
1205         },
1206         {
1207                 .matches = {
1208                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1209                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1210                 },
1211                 .driver_data = &i801_mux_config_asus_z8_d18,
1212         },
1213         {
1214                 .matches = {
1215                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1216                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1217                 },
1218                 .driver_data = &i801_mux_config_asus_z8_d12,
1219         },
1220         { }
1221 };
1222
1223 /* Setup multiplexing if needed */
1224 static int i801_add_mux(struct i801_priv *priv)
1225 {
1226         struct device *dev = &priv->adapter.dev;
1227         const struct i801_mux_config *mux_config;
1228         struct i2c_mux_gpio_platform_data gpio_data;
1229         int err;
1230
1231         if (!priv->mux_drvdata)
1232                 return 0;
1233         mux_config = priv->mux_drvdata;
1234
1235         /* Prepare the platform data */
1236         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1237         gpio_data.parent = priv->adapter.nr;
1238         gpio_data.values = mux_config->values;
1239         gpio_data.n_values = mux_config->n_values;
1240         gpio_data.classes = mux_config->classes;
1241         gpio_data.gpio_chip = mux_config->gpio_chip;
1242         gpio_data.gpios = mux_config->gpios;
1243         gpio_data.n_gpios = mux_config->n_gpios;
1244         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1245
1246         /* Register the mux device */
1247         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1248                                 PLATFORM_DEVID_AUTO, &gpio_data,
1249                                 sizeof(struct i2c_mux_gpio_platform_data));
1250         if (IS_ERR(priv->mux_pdev)) {
1251                 err = PTR_ERR(priv->mux_pdev);
1252                 priv->mux_pdev = NULL;
1253                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1254                 return err;
1255         }
1256
1257         return 0;
1258 }
1259
1260 static void i801_del_mux(struct i801_priv *priv)
1261 {
1262         if (priv->mux_pdev)
1263                 platform_device_unregister(priv->mux_pdev);
1264 }
1265
1266 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1267 {
1268         const struct dmi_system_id *id;
1269         const struct i801_mux_config *mux_config;
1270         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1271         int i;
1272
1273         id = dmi_first_match(mux_dmi_table);
1274         if (id) {
1275                 /* Remove branch classes from trunk */
1276                 mux_config = id->driver_data;
1277                 for (i = 0; i < mux_config->n_values; i++)
1278                         class &= ~mux_config->classes[i];
1279
1280                 /* Remember for later */
1281                 priv->mux_drvdata = mux_config;
1282         }
1283
1284         return class;
1285 }
1286 #else
1287 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1288 static inline void i801_del_mux(struct i801_priv *priv) { }
1289
1290 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1291 {
1292         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1293 }
1294 #endif
1295
1296 static const struct itco_wdt_platform_data tco_platform_data = {
1297         .name = "Intel PCH",
1298         .version = 4,
1299 };
1300
1301 static DEFINE_SPINLOCK(p2sb_spinlock);
1302
1303 static void i801_add_tco(struct i801_priv *priv)
1304 {
1305         struct pci_dev *pci_dev = priv->pci_dev;
1306         struct resource tco_res[3], *res;
1307         struct platform_device *pdev;
1308         unsigned int devfn;
1309         u32 tco_base, tco_ctl;
1310         u32 base_addr, ctrl_val;
1311         u64 base64_addr;
1312
1313         if (!(priv->features & FEATURE_TCO))
1314                 return;
1315
1316         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1317         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1318         if (!(tco_ctl & TCOCTL_EN))
1319                 return;
1320
1321         memset(tco_res, 0, sizeof(tco_res));
1322
1323         res = &tco_res[ICH_RES_IO_TCO];
1324         res->start = tco_base & ~1;
1325         res->end = res->start + 32 - 1;
1326         res->flags = IORESOURCE_IO;
1327
1328         /*
1329          * Power Management registers.
1330          */
1331         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1332         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1333
1334         res = &tco_res[ICH_RES_IO_SMI];
1335         res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1336         res->end = res->start + 3;
1337         res->flags = IORESOURCE_IO;
1338
1339         /*
1340          * Enable the ACPI I/O space.
1341          */
1342         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1343         ctrl_val |= ACPICTRL_EN;
1344         pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1345
1346         /*
1347          * We must access the NO_REBOOT bit over the Primary to Sideband
1348          * bridge (P2SB). The BIOS prevents the P2SB device from being
1349          * enumerated by the PCI subsystem, so we need to unhide/hide it
1350          * to lookup the P2SB BAR.
1351          */
1352         spin_lock(&p2sb_spinlock);
1353
1354         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1355
1356         /* Unhide the P2SB device */
1357         pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1358
1359         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1360         base64_addr = base_addr & 0xfffffff0;
1361
1362         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1363         base64_addr |= (u64)base_addr << 32;
1364
1365         /* Hide the P2SB device */
1366         pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1367         spin_unlock(&p2sb_spinlock);
1368
1369         res = &tco_res[ICH_RES_MEM_OFF];
1370         res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1371         res->end = res->start + 3;
1372         res->flags = IORESOURCE_MEM;
1373
1374         pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1375                                                  tco_res, 3, &tco_platform_data,
1376                                                  sizeof(tco_platform_data));
1377         if (IS_ERR(pdev)) {
1378                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1379                 return;
1380         }
1381
1382         priv->tco_pdev = pdev;
1383 }
1384
1385 #ifdef CONFIG_ACPI
1386 static acpi_status
1387 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1388                      u64 *value, void *handler_context, void *region_context)
1389 {
1390         struct i801_priv *priv = handler_context;
1391         struct pci_dev *pdev = priv->pci_dev;
1392         acpi_status status;
1393
1394         /*
1395          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1396          * further access from the driver itself. This device is now owned
1397          * by the system firmware.
1398          */
1399         mutex_lock(&priv->acpi_lock);
1400
1401         if (!priv->acpi_reserved) {
1402                 priv->acpi_reserved = true;
1403
1404                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1405                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1406
1407                 /*
1408                  * BIOS is accessing the host controller so prevent it from
1409                  * suspending automatically from now on.
1410                  */
1411                 pm_runtime_get_sync(&pdev->dev);
1412         }
1413
1414         if ((function & ACPI_IO_MASK) == ACPI_READ)
1415                 status = acpi_os_read_port(address, (u32 *)value, bits);
1416         else
1417                 status = acpi_os_write_port(address, (u32)*value, bits);
1418
1419         mutex_unlock(&priv->acpi_lock);
1420
1421         return status;
1422 }
1423
1424 static int i801_acpi_probe(struct i801_priv *priv)
1425 {
1426         struct acpi_device *adev;
1427         acpi_status status;
1428
1429         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1430         if (adev) {
1431                 status = acpi_install_address_space_handler(adev->handle,
1432                                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1433                                 NULL, priv);
1434                 if (ACPI_SUCCESS(status))
1435                         return 0;
1436         }
1437
1438         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1439 }
1440
1441 static void i801_acpi_remove(struct i801_priv *priv)
1442 {
1443         struct acpi_device *adev;
1444
1445         adev = ACPI_COMPANION(&priv->pci_dev->dev);
1446         if (!adev)
1447                 return;
1448
1449         acpi_remove_address_space_handler(adev->handle,
1450                 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1451
1452         mutex_lock(&priv->acpi_lock);
1453         if (priv->acpi_reserved)
1454                 pm_runtime_put(&priv->pci_dev->dev);
1455         mutex_unlock(&priv->acpi_lock);
1456 }
1457 #else
1458 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1459 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1460 #endif
1461
1462 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1463 {
1464         unsigned char temp;
1465         int err, i;
1466         struct i801_priv *priv;
1467
1468         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1469         if (!priv)
1470                 return -ENOMEM;
1471
1472         i2c_set_adapdata(&priv->adapter, priv);
1473         priv->adapter.owner = THIS_MODULE;
1474         priv->adapter.class = i801_get_adapter_class(priv);
1475         priv->adapter.algo = &smbus_algorithm;
1476         priv->adapter.dev.parent = &dev->dev;
1477         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1478         priv->adapter.retries = 3;
1479         mutex_init(&priv->acpi_lock);
1480
1481         priv->pci_dev = dev;
1482         switch (dev->device) {
1483         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1484         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1485         case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1486         case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1487         case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1488         case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1489                 priv->features |= FEATURE_I2C_BLOCK_READ;
1490                 priv->features |= FEATURE_IRQ;
1491                 priv->features |= FEATURE_SMBUS_PEC;
1492                 priv->features |= FEATURE_BLOCK_BUFFER;
1493                 /* If we have ACPI based watchdog use that instead */
1494                 if (!acpi_has_watchdog())
1495                         priv->features |= FEATURE_TCO;
1496                 priv->features |= FEATURE_HOST_NOTIFY;
1497                 break;
1498
1499         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1500         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1501         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1502         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1503         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1504         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1505                 priv->features |= FEATURE_IDF;
1506                 /* fall through */
1507         default:
1508                 priv->features |= FEATURE_I2C_BLOCK_READ;
1509                 priv->features |= FEATURE_IRQ;
1510                 /* fall through */
1511         case PCI_DEVICE_ID_INTEL_82801DB_3:
1512                 priv->features |= FEATURE_SMBUS_PEC;
1513                 priv->features |= FEATURE_BLOCK_BUFFER;
1514                 /* fall through */
1515         case PCI_DEVICE_ID_INTEL_82801CA_3:
1516                 priv->features |= FEATURE_HOST_NOTIFY;
1517                 /* fall through */
1518         case PCI_DEVICE_ID_INTEL_82801BA_2:
1519         case PCI_DEVICE_ID_INTEL_82801AB_3:
1520         case PCI_DEVICE_ID_INTEL_82801AA_3:
1521                 break;
1522         }
1523
1524         /* Disable features on user request */
1525         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1526                 if (priv->features & disable_features & (1 << i))
1527                         dev_notice(&dev->dev, "%s disabled by user\n",
1528                                    i801_feature_names[i]);
1529         }
1530         priv->features &= ~disable_features;
1531
1532         err = pcim_enable_device(dev);
1533         if (err) {
1534                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1535                         err);
1536                 return err;
1537         }
1538         pcim_pin_device(dev);
1539
1540         /* Determine the address of the SMBus area */
1541         priv->smba = pci_resource_start(dev, SMBBAR);
1542         if (!priv->smba) {
1543                 dev_err(&dev->dev,
1544                         "SMBus base address uninitialized, upgrade BIOS\n");
1545                 return -ENODEV;
1546         }
1547
1548         if (i801_acpi_probe(priv))
1549                 return -ENODEV;
1550
1551         err = pcim_iomap_regions(dev, 1 << SMBBAR,
1552                                  dev_driver_string(&dev->dev));
1553         if (err) {
1554                 dev_err(&dev->dev,
1555                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1556                         priv->smba,
1557                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1558                 i801_acpi_remove(priv);
1559                 return err;
1560         }
1561
1562         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1563         priv->original_hstcfg = temp;
1564         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1565         if (!(temp & SMBHSTCFG_HST_EN)) {
1566                 dev_info(&dev->dev, "Enabling SMBus device\n");
1567                 temp |= SMBHSTCFG_HST_EN;
1568         }
1569         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1570
1571         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1572                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1573                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1574                 priv->features &= ~FEATURE_IRQ;
1575         }
1576
1577         /* Clear special mode bits */
1578         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1579                 outb_p(inb_p(SMBAUXCTL(priv)) &
1580                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1581
1582         /* Default timeout in interrupt mode: 200 ms */
1583         priv->adapter.timeout = HZ / 5;
1584
1585         if (priv->features & FEATURE_IRQ) {
1586                 u16 pcictl, pcists;
1587
1588                 /* Complain if an interrupt is already pending */
1589                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1590                 if (pcists & SMBPCISTS_INTS)
1591                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1592
1593                 /* Check if interrupts have been disabled */
1594                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1595                 if (pcictl & SMBPCICTL_INTDIS) {
1596                         dev_info(&dev->dev, "Interrupts are disabled\n");
1597                         priv->features &= ~FEATURE_IRQ;
1598                 }
1599         }
1600
1601         if (priv->features & FEATURE_IRQ) {
1602                 init_waitqueue_head(&priv->waitq);
1603
1604                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1605                                        IRQF_SHARED,
1606                                        dev_driver_string(&dev->dev), priv);
1607                 if (err) {
1608                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1609                                 dev->irq, err);
1610                         priv->features &= ~FEATURE_IRQ;
1611                 }
1612         }
1613         dev_info(&dev->dev, "SMBus using %s\n",
1614                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1615
1616         i801_add_tco(priv);
1617
1618         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1619                 "SMBus I801 adapter at %04lx", priv->smba);
1620         err = i2c_add_adapter(&priv->adapter);
1621         if (err) {
1622                 i801_acpi_remove(priv);
1623                 return err;
1624         }
1625
1626         /*
1627          * Enable Host Notify for chips that supports it.
1628          * It is done after i2c_add_adapter() so that we are sure the work queue
1629          * is not used if i2c_add_adapter() fails.
1630          */
1631         err = i801_enable_host_notify(&priv->adapter);
1632         if (err && err != -ENOTSUPP)
1633                 dev_warn(&dev->dev, "Unable to enable SMBus Host Notify\n");
1634
1635         i801_probe_optional_slaves(priv);
1636         /* We ignore errors - multiplexing is optional */
1637         i801_add_mux(priv);
1638
1639         pci_set_drvdata(dev, priv);
1640
1641         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1642         pm_runtime_use_autosuspend(&dev->dev);
1643         pm_runtime_put_autosuspend(&dev->dev);
1644         pm_runtime_allow(&dev->dev);
1645
1646         return 0;
1647 }
1648
1649 static void i801_remove(struct pci_dev *dev)
1650 {
1651         struct i801_priv *priv = pci_get_drvdata(dev);
1652
1653         pm_runtime_forbid(&dev->dev);
1654         pm_runtime_get_noresume(&dev->dev);
1655
1656         i801_del_mux(priv);
1657         i2c_del_adapter(&priv->adapter);
1658         i801_acpi_remove(priv);
1659         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1660
1661         platform_device_unregister(priv->tco_pdev);
1662
1663         /*
1664          * do not call pci_disable_device(dev) since it can cause hard hangs on
1665          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1666          */
1667 }
1668
1669 #ifdef CONFIG_PM
1670 static int i801_suspend(struct device *dev)
1671 {
1672         struct pci_dev *pci_dev = to_pci_dev(dev);
1673         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1674
1675         pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1676         return 0;
1677 }
1678
1679 static int i801_resume(struct device *dev)
1680 {
1681         struct pci_dev *pci_dev = to_pci_dev(dev);
1682         struct i801_priv *priv = pci_get_drvdata(pci_dev);
1683         int err;
1684
1685         err = i801_enable_host_notify(&priv->adapter);
1686         if (err && err != -ENOTSUPP)
1687                 dev_warn(dev, "Unable to enable SMBus Host Notify\n");
1688
1689         return 0;
1690 }
1691 #endif
1692
1693 static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend,
1694                             i801_resume, NULL);
1695
1696 static struct pci_driver i801_driver = {
1697         .name           = "i801_smbus",
1698         .id_table       = i801_ids,
1699         .probe          = i801_probe,
1700         .remove         = i801_remove,
1701         .driver         = {
1702                 .pm     = &i801_pm_ops,
1703         },
1704 };
1705
1706 static int __init i2c_i801_init(void)
1707 {
1708         if (dmi_name_in_vendors("FUJITSU"))
1709                 input_apanel_init();
1710         return pci_register_driver(&i801_driver);
1711 }
1712
1713 static void __exit i2c_i801_exit(void)
1714 {
1715         pci_unregister_driver(&i801_driver);
1716 }
1717
1718 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1719 MODULE_DESCRIPTION("I801 SMBus driver");
1720 MODULE_LICENSE("GPL");
1721
1722 module_init(i2c_i801_init);
1723 module_exit(i2c_i801_exit);