drivers/i2c/busses/i2c-i801.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   4     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   5     <mdsxyz123@yahoo.com>
   6     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   7     Copyright (C) 2010         Intel Corporation,
   8                                David Woodhouse <dwmw2@infradead.org>
   9
  10 */
  11
  12 /*
  13  * Supports the following Intel I/O Controller Hubs (ICH):
  14  *
  15  *                                      I/O                     Block   I2C
  16  *                                      region  SMBus   Block   proc.   block
  17  * Chip name                    PCI ID  size    PEC     buffer  call    read
  18  * ---------------------------------------------------------------------------
  19  * 82801AA (ICH)                0x2413  16      no      no      no      no
  20  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  21  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  22  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  23  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  24  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  25  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  26  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  27  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  28  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  29  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  30  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  31  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  32  * ICH10                        0x3a30  32      hard    yes     yes     yes
  33  * ICH10                        0x3a60  32      hard    yes     yes     yes
  34  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  35  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  36  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  37  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  38  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  39  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  40  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  41  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  42  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  43  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  44  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  45  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  46  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  47  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  48  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  49  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  50  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  51  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  52  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  53  * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  54  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  55  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  56  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  57  * Emmitsburg (PCH)             0x1bc9  32      hard    yes     yes     yes
  58  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  59  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  60  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  61  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  62  * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  63  * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  64  * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  65  * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  66  * Ice Lake-LP (PCH)            0x34a3  32      hard    yes     yes     yes
  67  * Ice Lake-N (PCH)             0x38a3  32      hard    yes     yes     yes
  68  * Comet Lake (PCH)             0x02a3  32      hard    yes     yes     yes
  69  * Comet Lake-H (PCH)           0x06a3  32      hard    yes     yes     yes
  70  * Elkhart Lake (PCH)           0x4b23  32      hard    yes     yes     yes
  71  * Tiger Lake-LP (PCH)          0xa0a3  32      hard    yes     yes     yes
  72  * Tiger Lake-H (PCH)           0x43a3  32      hard    yes     yes     yes
  73  * Jasper Lake (SOC)            0x4da3  32      hard    yes     yes     yes
  74  * Comet Lake-V (PCH)           0xa3a3  32      hard    yes     yes     yes
  75  * Alder Lake-S (PCH)           0x7aa3  32      hard    yes     yes     yes
  76  * Alder Lake-P (PCH)           0x51a3  32      hard    yes     yes     yes
  77  * Alder Lake-M (PCH)           0x54a3  32      hard    yes     yes     yes
  78  * Raptor Lake-S (PCH)          0x7a23  32      hard    yes     yes     yes
  79  * Meteor Lake-P (SOC)          0x7e22  32      hard    yes     yes     yes
  80  *
  81  * Features supported by this driver:
  82  * Software PEC                         no
  83  * Hardware PEC                         yes
  84  * Block buffer                         yes
  85  * Block process call transaction       yes
  86  * I2C block read transaction           yes (doesn't use the block buffer)
  87  * Slave mode                           no
  88  * SMBus Host Notify                    yes
  89  * Interrupt processing                 yes
  90  *
  91  * See the file Documentation/i2c/busses/i2c-i801.rst for details.
  92  */
  93
  94 #define DRV_NAME        "i801_smbus"
  95
  96 #include <linux/interrupt.h>
  97 #include <linux/module.h>
  98 #include <linux/pci.h>
  99 #include <linux/kernel.h>
 100 #include <linux/stddef.h>
 101 #include <linux/delay.h>
 102 #include <linux/ioport.h>
 103 #include <linux/init.h>
 104 #include <linux/i2c.h>
 105 #include <linux/i2c-smbus.h>
 106 #include <linux/acpi.h>
 107 #include <linux/io.h>
 108 #include <linux/dmi.h>
 109 #include <linux/slab.h>
 110 #include <linux/string.h>
 111 #include <linux/completion.h>
 112 #include <linux/err.h>
 113 #include <linux/platform_device.h>
 114 #include <linux/platform_data/itco_wdt.h>
 115 #include <linux/platform_data/x86/p2sb.h>
 116 #include <linux/pm_runtime.h>
 117 #include <linux/mutex.h>
 118
 119 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 120 #include <linux/gpio/machine.h>
 121 #include <linux/platform_data/i2c-mux-gpio.h>
 122 #endif
 123
 124 /* I801 SMBus address offsets */
 125 #define SMBHSTSTS(p)    (0 + (p)->smba)
 126 #define SMBHSTCNT(p)    (2 + (p)->smba)
 127 #define SMBHSTCMD(p)    (3 + (p)->smba)
 128 #define SMBHSTADD(p)    (4 + (p)->smba)
 129 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 130 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 131 #define SMBBLKDAT(p)    (7 + (p)->smba)
 132 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 133 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 134 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 135 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 136 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 137 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 138
 139 /* PCI Address Constants */
 140 #define SMBBAR          4
 141 #define SMBHSTCFG       0x040
 142 #define TCOBASE         0x050
 143 #define TCOCTL          0x054
 144
 145 #define SBREG_SMBCTRL           0xc6000c
 146 #define SBREG_SMBCTRL_DNV       0xcf000c
 147
 148 /* Host configuration bits for SMBHSTCFG */
 149 #define SMBHSTCFG_HST_EN        BIT(0)
 150 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 151 #define SMBHSTCFG_I2C_EN        BIT(2)
 152 #define SMBHSTCFG_SPD_WD        BIT(4)
 153
 154 /* TCO configuration bits for TCOCTL */
 155 #define TCOCTL_EN               BIT(8)
 156
 157 /* Auxiliary status register bits, ICH4+ only */
 158 #define SMBAUXSTS_CRCE          BIT(0)
 159 #define SMBAUXSTS_STCO          BIT(1)
 160
 161 /* Auxiliary control register bits, ICH4+ only */
 162 #define SMBAUXCTL_CRC           BIT(0)
 163 #define SMBAUXCTL_E32B          BIT(1)
 164
 165 /* I801 command constants */
 166 #define I801_QUICK              0x00
 167 #define I801_BYTE               0x04
 168 #define I801_BYTE_DATA          0x08
 169 #define I801_WORD_DATA          0x0C
 170 #define I801_PROC_CALL          0x10
 171 #define I801_BLOCK_DATA         0x14
 172 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 173 #define I801_BLOCK_PROC_CALL    0x1C
 174
 175 /* I801 Host Control register bits */
 176 #define SMBHSTCNT_INTREN        BIT(0)
 177 #define SMBHSTCNT_KILL          BIT(1)
 178 #define SMBHSTCNT_LAST_BYTE     BIT(5)
 179 #define SMBHSTCNT_START         BIT(6)
 180 #define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 181
 182 /* I801 Hosts Status register bits */
 183 #define SMBHSTSTS_BYTE_DONE     BIT(7)
 184 #define SMBHSTSTS_INUSE_STS     BIT(6)
 185 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
 186 #define SMBHSTSTS_FAILED        BIT(4)
 187 #define SMBHSTSTS_BUS_ERR       BIT(3)
 188 #define SMBHSTSTS_DEV_ERR       BIT(2)
 189 #define SMBHSTSTS_INTR          BIT(1)
 190 #define SMBHSTSTS_HOST_BUSY     BIT(0)
 191
 192 /* Host Notify Status register bits */
 193 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 194
 195 /* Host Notify Command register bits */
 196 #define SMBSLVCMD_SMBALERT_DISABLE      BIT(2)
 197 #define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 198
 199 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 200                                  SMBHSTSTS_DEV_ERR)
 201
 202 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 203                                  STATUS_ERROR_FLAGS)
 204
 205 /* Older devices have their ID defined in <linux/pci_ids.h> */
 206 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS             0x02a3
 207 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS           0x06a3
 208 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 209 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 210 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 211 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS                   0x1bc9
 212 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 214 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 218 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 219 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 220 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 221 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 222 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 223 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 224 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS            0x34a3
 225 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS             0x38a3
 226 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 227 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS           0x43a3
 228 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS          0x4b23
 229 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS           0x4da3
 230 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS          0x51a3
 231 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS          0x54a3
 232 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 233 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS         0x7a23
 234 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS          0x7aa3
 235 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS         0x7e22
 236 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 237 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 238 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 239 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 240 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 241 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 242 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 243 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 244 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 245 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 246 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS          0xa0a3
 247 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 248 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 249 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 250 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 251 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 252 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS           0xa3a3
 253
 254 struct i801_mux_config {
 255         char *gpio_chip;
 256         unsigned values[3];
 257         int n_values;
 258         unsigned classes[3];
 259         unsigned gpios[2];              /* Relative to gpio_chip->base */
 260         int n_gpios;
 261 };
 262
 263 struct i801_priv {
 264         struct i2c_adapter adapter;
 265         unsigned long smba;
 266         unsigned char original_hstcfg;
 267         unsigned char original_hstcnt;
 268         unsigned char original_slvcmd;
 269         struct pci_dev *pci_dev;
 270         unsigned int features;
 271
 272         /* isr processing */
 273         struct completion done;
 274         u8 status;
 275
 276         /* Command state used by isr for byte-by-byte block transactions */
 277         u8 cmd;
 278         bool is_read;
 279         int count;
 280         int len;
 281         u8 *data;
 282
 283 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 284         const struct i801_mux_config *mux_drvdata;
 285         struct platform_device *mux_pdev;
 286         struct gpiod_lookup_table *lookup;
 287 #endif
 288         struct platform_device *tco_pdev;
 289
 290         /*
 291          * If set to true the host controller registers are reserved for
 292          * ACPI AML use. Protected by acpi_lock.
 293          */
 294         bool acpi_reserved;
 295         struct mutex acpi_lock;
 296 };
 297
 298 #define FEATURE_SMBUS_PEC       BIT(0)
 299 #define FEATURE_BLOCK_BUFFER    BIT(1)
 300 #define FEATURE_BLOCK_PROC      BIT(2)
 301 #define FEATURE_I2C_BLOCK_READ  BIT(3)
 302 #define FEATURE_IRQ             BIT(4)
 303 #define FEATURE_HOST_NOTIFY     BIT(5)
 304 /* Not really a feature, but it's convenient to handle it as such */
 305 #define FEATURE_IDF             BIT(15)
 306 #define FEATURE_TCO_SPT         BIT(16)
 307 #define FEATURE_TCO_CNL         BIT(17)
 308
 309 static const char *i801_feature_names[] = {
 310         "SMBus PEC",
 311         "Block buffer",
 312         "Block process call",
 313         "I2C block read",
 314         "Interrupt",
 315         "SMBus Host Notify",
 316 };
 317
 318 static unsigned int disable_features;
 319 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 320 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 321         "\t\t  0x01  disable SMBus PEC\n"
 322         "\t\t  0x02  disable the block buffer\n"
 323         "\t\t  0x08  disable the I2C block read functionality\n"
 324         "\t\t  0x10  don't use interrupts\n"
 325         "\t\t  0x20  disable SMBus Host Notify ");
 326
 327 /* Make sure the SMBus host is ready to start transmitting.
 328    Return 0 if it is, -EBUSY if it is not. */
 329 static int i801_check_pre(struct i801_priv *priv)
 330 {
 331         int status;
 332
 333         status = inb_p(SMBHSTSTS(priv));
 334         if (status & SMBHSTSTS_HOST_BUSY) {
 335                 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n");
 336                 return -EBUSY;
 337         }
 338
 339         status &= STATUS_FLAGS;
 340         if (status) {
 341                 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status);
 342                 outb_p(status, SMBHSTSTS(priv));
 343         }
 344
 345         /*
 346          * Clear CRC status if needed.
 347          * During normal operation, i801_check_post() takes care
 348          * of it after every operation.  We do it here only in case
 349          * the hardware was already in this state when the driver
 350          * started.
 351          */
 352         if (priv->features & FEATURE_SMBUS_PEC) {
 353                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 354                 if (status) {
 355                         pci_dbg(priv->pci_dev, "Clearing aux status flags (%02x)\n", status);
 356                         outb_p(status, SMBAUXSTS(priv));
 357                 }
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int i801_check_post(struct i801_priv *priv, int status)
 364 {
 365         int result = 0;
 366
 367         /*
 368          * If the SMBus is still busy, we give up
 369          */
 370         if (unlikely(status < 0)) {
 371                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 372                 /* try to stop the current command */
 373                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 374                 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
 375                 usleep_range(1000, 2000);
 376                 outb_p(0, SMBHSTCNT(priv));
 377
 378                 /* Check if it worked */
 379                 status = inb_p(SMBHSTSTS(priv));
 380                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 381                     !(status & SMBHSTSTS_FAILED))
 382                         dev_err(&priv->pci_dev->dev,
 383                                 "Failed terminating the transaction\n");
 384                 return -ETIMEDOUT;
 385         }
 386
 387         if (status & SMBHSTSTS_FAILED) {
 388                 result = -EIO;
 389                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 390         }
 391         if (status & SMBHSTSTS_DEV_ERR) {
 392                 /*
 393                  * This may be a PEC error, check and clear it.
 394                  *
 395                  * AUXSTS is handled differently from HSTSTS.
 396                  * For HSTSTS, i801_isr() or i801_wait_intr()
 397                  * has already cleared the error bits in hardware,
 398                  * and we are passed a copy of the original value
 399                  * in "status".
 400                  * For AUXSTS, the hardware register is left
 401                  * for us to handle here.
 402                  * This is asymmetric, slightly iffy, but safe,
 403                  * since all this code is serialized and the CRCE
 404                  * bit is harmless as long as it's cleared before
 405                  * the next operation.
 406                  */
 407                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 408                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 409                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 410                         result = -EBADMSG;
 411                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 412                 } else {
 413                         result = -ENXIO;
 414                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 415                 }
 416         }
 417         if (status & SMBHSTSTS_BUS_ERR) {
 418                 result = -EAGAIN;
 419                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 420         }
 421
 422         return result;
 423 }
 424
 425 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 426 static int i801_wait_intr(struct i801_priv *priv)
 427 {
 428         unsigned long timeout = jiffies + priv->adapter.timeout;
 429         int status, busy;
 430
 431         do {
 432                 usleep_range(250, 500);
 433                 status = inb_p(SMBHSTSTS(priv));
 434                 busy = status & SMBHSTSTS_HOST_BUSY;
 435                 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
 436                 if (!busy && status)
 437                         return status;
 438         } while (time_is_after_eq_jiffies(timeout));
 439
 440         return -ETIMEDOUT;
 441 }
 442
 443 /* Wait for either BYTE_DONE or an error flag being set */
 444 static int i801_wait_byte_done(struct i801_priv *priv)
 445 {
 446         unsigned long timeout = jiffies + priv->adapter.timeout;
 447         int status;
 448
 449         do {
 450                 usleep_range(250, 500);
 451                 status = inb_p(SMBHSTSTS(priv));
 452                 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
 453                         return status & STATUS_ERROR_FLAGS;
 454         } while (time_is_after_eq_jiffies(timeout));
 455
 456         return -ETIMEDOUT;
 457 }
 458
 459 static int i801_transaction(struct i801_priv *priv, int xact)
 460 {
 461         int status;
 462         unsigned long result;
 463         const struct i2c_adapter *adap = &priv->adapter;
 464
 465         status = i801_check_pre(priv);
 466         if (status < 0)
 467                 return status;
 468
 469         if (priv->features & FEATURE_IRQ) {
 470                 reinit_completion(&priv->done);
 471                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 472                        SMBHSTCNT(priv));
 473                 result = wait_for_completion_timeout(&priv->done, adap->timeout);
 474                 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
 475         }
 476
 477         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 478
 479         status = i801_wait_intr(priv);
 480         return i801_check_post(priv, status);
 481 }
 482
 483 static int i801_block_transaction_by_block(struct i801_priv *priv,
 484                                            union i2c_smbus_data *data,
 485                                            char read_write, int command)
 486 {
 487         int i, len, status, xact;
 488
 489         switch (command) {
 490         case I2C_SMBUS_BLOCK_PROC_CALL:
 491                 xact = I801_BLOCK_PROC_CALL;
 492                 break;
 493         case I2C_SMBUS_BLOCK_DATA:
 494                 xact = I801_BLOCK_DATA;
 495                 break;
 496         default:
 497                 return -EOPNOTSUPP;
 498         }
 499
 500         /* Set block buffer mode */
 501         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 502
 503         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 504
 505         if (read_write == I2C_SMBUS_WRITE) {
 506                 len = data->block[0];
 507                 outb_p(len, SMBHSTDAT0(priv));
 508                 for (i = 0; i < len; i++)
 509                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 510         }
 511
 512         status = i801_transaction(priv, xact);
 513         if (status)
 514                 goto out;
 515
 516         if (read_write == I2C_SMBUS_READ ||
 517             command == I2C_SMBUS_BLOCK_PROC_CALL) {
 518                 len = inb_p(SMBHSTDAT0(priv));
 519                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 520                         status = -EPROTO;
 521                         goto out;
 522                 }
 523
 524                 data->block[0] = len;
 525                 for (i = 0; i < len; i++)
 526                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 527         }
 528 out:
 529         outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_E32B, SMBAUXCTL(priv));
 530         return status;
 531 }
 532
 533 static void i801_isr_byte_done(struct i801_priv *priv)
 534 {
 535         if (priv->is_read) {
 536                 /* For SMBus block reads, length is received with first byte */
 537                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 538                     (priv->count == 0)) {
 539                         priv->len = inb_p(SMBHSTDAT0(priv));
 540                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 541                                 dev_err(&priv->pci_dev->dev,
 542                                         "Illegal SMBus block read size %d\n",
 543                                         priv->len);
 544                                 /* FIXME: Recover */
 545                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 546                         }
 547                         priv->data[-1] = priv->len;
 548                 }
 549
 550                 /* Read next byte */
 551                 if (priv->count < priv->len)
 552                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 553                 else
 554                         dev_dbg(&priv->pci_dev->dev,
 555                                 "Discarding extra byte on block read\n");
 556
 557                 /* Set LAST_BYTE for last byte of read transaction */
 558                 if (priv->count == priv->len - 1)
 559                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 560                                SMBHSTCNT(priv));
 561         } else if (priv->count < priv->len - 1) {
 562                 /* Write next byte, except for IRQ after last byte */
 563                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 564         }
 565 }
 566
 567 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 568 {
 569         unsigned short addr;
 570
 571         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 572
 573         /*
 574          * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 575          * always returns 0. Our current implementation doesn't provide
 576          * data, so we just ignore it.
 577          */
 578         i2c_handle_smbus_host_notify(&priv->adapter, addr);
 579
 580         /* clear Host Notify bit and return */
 581         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 582         return IRQ_HANDLED;
 583 }
 584
 585 /*
 586  * There are three kinds of interrupts:
 587  *
 588  * 1) i801 signals transaction completion with one of these interrupts:
 589  *      INTR - Success
 590  *      DEV_ERR - Invalid command, NAK or communication timeout
 591  *      BUS_ERR - SMI# transaction collision
 592  *      FAILED - transaction was canceled due to a KILL request
 593  *    When any of these occur, update ->status and signal completion.
 594  *
 595  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 596  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 597  *
 598  * 3) Host Notify interrupts
 599  */
 600 static irqreturn_t i801_isr(int irq, void *dev_id)
 601 {
 602         struct i801_priv *priv = dev_id;
 603         u16 pcists;
 604         u8 status;
 605
 606         /* Confirm this is our interrupt */
 607         pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
 608         if (!(pcists & PCI_STATUS_INTERRUPT))
 609                 return IRQ_NONE;
 610
 611         if (priv->features & FEATURE_HOST_NOTIFY) {
 612                 status = inb_p(SMBSLVSTS(priv));
 613                 if (status & SMBSLVSTS_HST_NTFY_STS)
 614                         return i801_host_notify_isr(priv);
 615         }
 616
 617         status = inb_p(SMBHSTSTS(priv));
 618         if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE)
 619                 i801_isr_byte_done(priv);
 620
 621         /*
 622          * Clear IRQ sources: SMB_ALERT status is set after signal assertion
 623          * independently of the interrupt generation being blocked or not
 624          * so clear it always when the status is set.
 625          */
 626         status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS;
 627         outb_p(status, SMBHSTSTS(priv));
 628
 629         status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
 630         if (status) {
 631                 priv->status = status;
 632                 complete(&priv->done);
 633         }
 634
 635         return IRQ_HANDLED;
 636 }
 637
 638 /*
 639  * For "byte-by-byte" block transactions:
 640  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 641  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 642  */
 643 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 644                                                union i2c_smbus_data *data,
 645                                                char read_write, int command)
 646 {
 647         int i, len;
 648         int smbcmd;
 649         int status;
 650         unsigned long result;
 651         const struct i2c_adapter *adap = &priv->adapter;
 652
 653         if (command == I2C_SMBUS_BLOCK_PROC_CALL)
 654                 return -EOPNOTSUPP;
 655
 656         status = i801_check_pre(priv);
 657         if (status < 0)
 658                 return status;
 659
 660         len = data->block[0];
 661
 662         if (read_write == I2C_SMBUS_WRITE) {
 663                 outb_p(len, SMBHSTDAT0(priv));
 664                 outb_p(data->block[1], SMBBLKDAT(priv));
 665         }
 666
 667         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 668             read_write == I2C_SMBUS_READ)
 669                 smbcmd = I801_I2C_BLOCK_DATA;
 670         else
 671                 smbcmd = I801_BLOCK_DATA;
 672
 673         if (priv->features & FEATURE_IRQ) {
 674                 priv->is_read = (read_write == I2C_SMBUS_READ);
 675                 if (len == 1 && priv->is_read)
 676                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 677                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 678                 priv->len = len;
 679                 priv->count = 0;
 680                 priv->data = &data->block[1];
 681
 682                 reinit_completion(&priv->done);
 683                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 684                 result = wait_for_completion_timeout(&priv->done, adap->timeout);
 685                 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
 686         }
 687
 688         for (i = 1; i <= len; i++) {
 689                 if (i == len && read_write == I2C_SMBUS_READ)
 690                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 691                 outb_p(smbcmd, SMBHSTCNT(priv));
 692
 693                 if (i == 1)
 694                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 695                                SMBHSTCNT(priv));
 696
 697                 status = i801_wait_byte_done(priv);
 698                 if (status)
 699                         goto exit;
 700
 701                 if (i == 1 && read_write == I2C_SMBUS_READ
 702                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 703                         len = inb_p(SMBHSTDAT0(priv));
 704                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 705                                 dev_err(&priv->pci_dev->dev,
 706                                         "Illegal SMBus block read size %d\n",
 707                                         len);
 708                                 /* Recover */
 709                                 while (inb_p(SMBHSTSTS(priv)) &
 710                                        SMBHSTSTS_HOST_BUSY)
 711                                         outb_p(SMBHSTSTS_BYTE_DONE,
 712                                                SMBHSTSTS(priv));
 713                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 714                                 return -EPROTO;
 715                         }
 716                         data->block[0] = len;
 717                 }
 718
 719                 /* Retrieve/store value in SMBBLKDAT */
 720                 if (read_write == I2C_SMBUS_READ)
 721                         data->block[i] = inb_p(SMBBLKDAT(priv));
 722                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 723                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 724
 725                 /* signals SMBBLKDAT ready */
 726                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 727         }
 728
 729         status = i801_wait_intr(priv);
 730 exit:
 731         return i801_check_post(priv, status);
 732 }
 733
 734 static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write)
 735 {
 736         outb_p((addr << 1) | (read_write & 0x01), SMBHSTADD(priv));
 737 }
 738
 739 /* Single value transaction function */
 740 static int i801_simple_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
 741                                    char read_write, int command)
 742 {
 743         int xact, ret;
 744
 745         switch (command) {
 746         case I2C_SMBUS_QUICK:
 747                 xact = I801_QUICK;
 748                 break;
 749         case I2C_SMBUS_BYTE:
 750                 xact = I801_BYTE;
 751                 break;
 752         case I2C_SMBUS_BYTE_DATA:
 753                 if (read_write == I2C_SMBUS_WRITE)
 754                         outb_p(data->byte, SMBHSTDAT0(priv));
 755                 xact = I801_BYTE_DATA;
 756                 break;
 757         case I2C_SMBUS_WORD_DATA:
 758                 if (read_write == I2C_SMBUS_WRITE) {
 759                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 760                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 761                 }
 762                 xact = I801_WORD_DATA;
 763                 break;
 764         case I2C_SMBUS_PROC_CALL:
 765                 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 766                 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 767                 xact = I801_PROC_CALL;
 768                 break;
 769         default:
 770                 return -EOPNOTSUPP;
 771         }
 772
 773         ret = i801_transaction(priv, xact);
 774         if (ret || read_write == I2C_SMBUS_WRITE)
 775                 return ret;
 776
 777         switch (command) {
 778         case I2C_SMBUS_BYTE:
 779         case I2C_SMBUS_BYTE_DATA:
 780                 data->byte = inb_p(SMBHSTDAT0(priv));
 781                 break;
 782         case I2C_SMBUS_WORD_DATA:
 783         case I2C_SMBUS_PROC_CALL:
 784                 data->word = inb_p(SMBHSTDAT0(priv)) +
 785                              (inb_p(SMBHSTDAT1(priv)) << 8);
 786                 break;
 787         }
 788
 789         return 0;
 790 }
 791
 792 /* Block transaction function */
 793 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
 794                                   char read_write, int command)
 795 {
 796         int result = 0;
 797         unsigned char hostc;
 798
 799         if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
 800                 data->block[0] = I2C_SMBUS_BLOCK_MAX;
 801         else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 802                 return -EPROTO;
 803
 804         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 805                 if (read_write == I2C_SMBUS_WRITE) {
 806                         /* set I2C_EN bit in configuration register */
 807                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 808                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 809                                               hostc | SMBHSTCFG_I2C_EN);
 810                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 811                         dev_err(&priv->pci_dev->dev,
 812                                 "I2C block read is unsupported!\n");
 813                         return -EOPNOTSUPP;
 814                 }
 815         }
 816
 817         /* Experience has shown that the block buffer can only be used for
 818            SMBus (not I2C) block transactions, even though the datasheet
 819            doesn't mention this limitation. */
 820         if ((priv->features & FEATURE_BLOCK_BUFFER) &&
 821             command != I2C_SMBUS_I2C_BLOCK_DATA)
 822                 result = i801_block_transaction_by_block(priv, data,
 823                                                          read_write,
 824                                                          command);
 825         else
 826                 result = i801_block_transaction_byte_by_byte(priv, data,
 827                                                              read_write,
 828                                                              command);
 829
 830         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 831          && read_write == I2C_SMBUS_WRITE) {
 832                 /* restore saved configuration register value */
 833                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 834         }
 835         return result;
 836 }
 837
 838 /* Return negative errno on error. */
 839 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 840                        unsigned short flags, char read_write, u8 command,
 841                        int size, union i2c_smbus_data *data)
 842 {
 843         int hwpec, ret, block = 0;
 844         struct i801_priv *priv = i2c_get_adapdata(adap);
 845
 846         mutex_lock(&priv->acpi_lock);
 847         if (priv->acpi_reserved) {
 848                 mutex_unlock(&priv->acpi_lock);
 849                 return -EBUSY;
 850         }
 851
 852         pm_runtime_get_sync(&priv->pci_dev->dev);
 853
 854         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 855                 && size != I2C_SMBUS_QUICK
 856                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 857
 858         switch (size) {
 859         case I2C_SMBUS_QUICK:
 860                 i801_set_hstadd(priv, addr, read_write);
 861                 break;
 862         case I2C_SMBUS_BYTE:
 863                 i801_set_hstadd(priv, addr, read_write);
 864                 if (read_write == I2C_SMBUS_WRITE)
 865                         outb_p(command, SMBHSTCMD(priv));
 866                 break;
 867         case I2C_SMBUS_BYTE_DATA:
 868                 i801_set_hstadd(priv, addr, read_write);
 869                 outb_p(command, SMBHSTCMD(priv));
 870                 break;
 871         case I2C_SMBUS_WORD_DATA:
 872                 i801_set_hstadd(priv, addr, read_write);
 873                 outb_p(command, SMBHSTCMD(priv));
 874                 break;
 875         case I2C_SMBUS_PROC_CALL:
 876                 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
 877                 outb_p(command, SMBHSTCMD(priv));
 878                 read_write = I2C_SMBUS_READ;
 879                 break;
 880         case I2C_SMBUS_BLOCK_DATA:
 881                 i801_set_hstadd(priv, addr, read_write);
 882                 outb_p(command, SMBHSTCMD(priv));
 883                 block = 1;
 884                 break;
 885         case I2C_SMBUS_I2C_BLOCK_DATA:
 886                 /*
 887                  * NB: page 240 of ICH5 datasheet shows that the R/#W
 888                  * bit should be cleared here, even when reading.
 889                  * However if SPD Write Disable is set (Lynx Point and later),
 890                  * the read will fail if we don't set the R/#W bit.
 891                  */
 892                 i801_set_hstadd(priv, addr,
 893                                 priv->original_hstcfg & SMBHSTCFG_SPD_WD ?
 894                                 read_write : I2C_SMBUS_WRITE);
 895                 if (read_write == I2C_SMBUS_READ) {
 896                         /* NB: page 240 of ICH5 datasheet also shows
 897                          * that DATA1 is the cmd field when reading */
 898                         outb_p(command, SMBHSTDAT1(priv));
 899                 } else
 900                         outb_p(command, SMBHSTCMD(priv));
 901                 block = 1;
 902                 break;
 903         case I2C_SMBUS_BLOCK_PROC_CALL:
 904                 /* Needs to be flagged as write transaction */
 905                 i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE);
 906                 outb_p(command, SMBHSTCMD(priv));
 907                 block = 1;
 908                 break;
 909         default:
 910                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 911                         size);
 912                 ret = -EOPNOTSUPP;
 913                 goto out;
 914         }
 915
 916         if (hwpec)      /* enable/disable hardware PEC */
 917                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 918         else
 919                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 920                        SMBAUXCTL(priv));
 921
 922         if (block)
 923                 ret = i801_block_transaction(priv, data, read_write, size);
 924         else
 925                 ret = i801_simple_transaction(priv, data, read_write, size);
 926
 927         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 928          * time, so we forcibly disable it after every transaction.
 929          */
 930         if (hwpec)
 931                 outb_p(inb_p(SMBAUXCTL(priv)) & ~SMBAUXCTL_CRC, SMBAUXCTL(priv));
 932 out:
 933         /*
 934          * Unlock the SMBus device for use by BIOS/ACPI,
 935          * and clear status flags if not done already.
 936          */
 937         outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv));
 938
 939         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 940         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 941         mutex_unlock(&priv->acpi_lock);
 942         return ret;
 943 }
 944
 945
 946 static u32 i801_func(struct i2c_adapter *adapter)
 947 {
 948         struct i801_priv *priv = i2c_get_adapdata(adapter);
 949
 950         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 951                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 952                I2C_FUNC_SMBUS_PROC_CALL |
 953                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 954                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 955                ((priv->features & FEATURE_BLOCK_PROC) ?
 956                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
 957                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 958                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 959                ((priv->features & FEATURE_HOST_NOTIFY) ?
 960                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 961 }
 962
 963 static void i801_enable_host_notify(struct i2c_adapter *adapter)
 964 {
 965         struct i801_priv *priv = i2c_get_adapdata(adapter);
 966
 967         if (!(priv->features & FEATURE_HOST_NOTIFY))
 968                 return;
 969
 970         /*
 971          * Enable host notify interrupt and block the generation of interrupt
 972          * from the SMB_ALERT signal because the driver does not support
 973          * SMBus Alert.
 974          */
 975         outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE |
 976                priv->original_slvcmd, SMBSLVCMD(priv));
 977
 978         /* clear Host Notify bit to allow a new notification */
 979         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 980 }
 981
 982 static void i801_disable_host_notify(struct i801_priv *priv)
 983 {
 984         if (!(priv->features & FEATURE_HOST_NOTIFY))
 985                 return;
 986
 987         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
 988 }
 989
 990 static const struct i2c_algorithm smbus_algorithm = {
 991         .smbus_xfer     = i801_access,
 992         .functionality  = i801_func,
 993 };
 994
 995 #define FEATURES_ICH5   (FEATURE_BLOCK_PROC | FEATURE_I2C_BLOCK_READ    | \
 996                          FEATURE_IRQ | FEATURE_SMBUS_PEC                | \
 997                          FEATURE_BLOCK_BUFFER | FEATURE_HOST_NOTIFY)
 998 #define FEATURES_ICH4   (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \
 999                          FEATURE_HOST_NOTIFY)
1000
1001 static const struct pci_device_id i801_ids[] = {
1002         { PCI_DEVICE_DATA(INTEL, 82801AA_3,             0)                               },
1003         { PCI_DEVICE_DATA(INTEL, 82801AB_3,             0)                               },
1004         { PCI_DEVICE_DATA(INTEL, 82801BA_2,             0)                               },
1005         { PCI_DEVICE_DATA(INTEL, 82801CA_3,             FEATURE_HOST_NOTIFY)             },
1006         { PCI_DEVICE_DATA(INTEL, 82801DB_3,             FEATURES_ICH4)                   },
1007         { PCI_DEVICE_DATA(INTEL, 82801EB_3,             FEATURES_ICH5)                   },
1008         { PCI_DEVICE_DATA(INTEL, ESB_4,                 FEATURES_ICH5)                   },
1009         { PCI_DEVICE_DATA(INTEL, ICH6_16,               FEATURES_ICH5)                   },
1010         { PCI_DEVICE_DATA(INTEL, ICH7_17,               FEATURES_ICH5)                   },
1011         { PCI_DEVICE_DATA(INTEL, ESB2_17,               FEATURES_ICH5)                   },
1012         { PCI_DEVICE_DATA(INTEL, ICH8_5,                FEATURES_ICH5)                   },
1013         { PCI_DEVICE_DATA(INTEL, ICH9_6,                FEATURES_ICH5)                   },
1014         { PCI_DEVICE_DATA(INTEL, EP80579_1,             FEATURES_ICH5)                   },
1015         { PCI_DEVICE_DATA(INTEL, ICH10_4,               FEATURES_ICH5)                   },
1016         { PCI_DEVICE_DATA(INTEL, ICH10_5,               FEATURES_ICH5)                   },
1017         { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS,   FEATURES_ICH5)                   },
1018         { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS,     FEATURES_ICH5)                   },
1019         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS,        FEATURES_ICH5)                   },
1020         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0,   FEATURES_ICH5 | FEATURE_IDF)     },
1021         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1,   FEATURES_ICH5 | FEATURE_IDF)     },
1022         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2,   FEATURES_ICH5 | FEATURE_IDF)     },
1023         { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS,        FEATURES_ICH5)                   },
1024         { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS,    FEATURES_ICH5)                   },
1025         { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS,       FEATURES_ICH5)                   },
1026         { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS,    FEATURES_ICH5)                   },
1027         { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS,          FEATURES_ICH5)                   },
1028         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS,       FEATURES_ICH5)                   },
1029         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0,   FEATURES_ICH5 | FEATURE_IDF)     },
1030         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1,   FEATURES_ICH5 | FEATURE_IDF)     },
1031         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2,   FEATURES_ICH5 | FEATURE_IDF)     },
1032         { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS,     FEATURES_ICH5)                   },
1033         { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS,      FEATURES_ICH5)                   },
1034         { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS,    FEATURES_ICH5)                   },
1035         { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5)                   },
1036         { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS,        FEATURES_ICH5)                   },
1037         { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS,        FEATURES_ICH5)                   },
1038         { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1039         { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1040         { PCI_DEVICE_DATA(INTEL, CDF_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_CNL) },
1041         { PCI_DEVICE_DATA(INTEL, DNV_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_SPT) },
1042         { PCI_DEVICE_DATA(INTEL, EBG_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_CNL) },
1043         { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS,         FEATURES_ICH5)                   },
1044         { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_SPT) },
1045         { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1046         { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1047         { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1048         { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_CNL) },
1049         { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS,      FEATURES_ICH5 | FEATURE_TCO_CNL) },
1050         { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_CNL) },
1051         { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_CNL) },
1052         { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1053         { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_SPT) },
1054         { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1055         { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1056         { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1057         { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1058         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1059         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1060         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1061         { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_CNL) },
1062         { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_CNL) },
1063         { 0, }
1064 };
1065
1066 MODULE_DEVICE_TABLE(pci, i801_ids);
1067
1068 #if defined CONFIG_X86 && defined CONFIG_DMI
1069 static unsigned char apanel_addr;
1070
1071 /* Scan the system ROM for the signature "FJKEYINF" */
1072 static __init const void __iomem *bios_signature(const void __iomem *bios)
1073 {
1074         ssize_t offset;
1075         const unsigned char signature[] = "FJKEYINF";
1076
1077         for (offset = 0; offset < 0x10000; offset += 0x10) {
1078                 if (check_signature(bios + offset, signature,
1079                                     sizeof(signature)-1))
1080                         return bios + offset;
1081         }
1082         return NULL;
1083 }
1084
1085 static void __init input_apanel_init(void)
1086 {
1087         void __iomem *bios;
1088         const void __iomem *p;
1089
1090         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1091         p = bios_signature(bios);
1092         if (p) {
1093                 /* just use the first address */
1094                 apanel_addr = readb(p + 8 + 3) >> 1;
1095         }
1096         iounmap(bios);
1097 }
1098
1099 struct dmi_onboard_device_info {
1100         const char *name;
1101         u8 type;
1102         unsigned short i2c_addr;
1103         const char *i2c_type;
1104 };
1105
1106 static const struct dmi_onboard_device_info dmi_devices[] = {
1107         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1108         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1109         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1110 };
1111
1112 static void dmi_check_onboard_device(u8 type, const char *name,
1113                                      struct i2c_adapter *adap)
1114 {
1115         int i;
1116         struct i2c_board_info info;
1117
1118         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1119                 /* & ~0x80, ignore enabled/disabled bit */
1120                 if ((type & ~0x80) != dmi_devices[i].type)
1121                         continue;
1122                 if (strcasecmp(name, dmi_devices[i].name))
1123                         continue;
1124
1125                 memset(&info, 0, sizeof(struct i2c_board_info));
1126                 info.addr = dmi_devices[i].i2c_addr;
1127                 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1128                 i2c_new_client_device(adap, &info);
1129                 break;
1130         }
1131 }
1132
1133 /* We use our own function to check for onboard devices instead of
1134    dmi_find_device() as some buggy BIOS's have the devices we are interested
1135    in marked as disabled */
1136 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1137 {
1138         int i, count;
1139
1140         if (dm->type != 10)
1141                 return;
1142
1143         count = (dm->length - sizeof(struct dmi_header)) / 2;
1144         for (i = 0; i < count; i++) {
1145                 const u8 *d = (char *)(dm + 1) + (i * 2);
1146                 const char *name = ((char *) dm) + dm->length;
1147                 u8 type = d[0];
1148                 u8 s = d[1];
1149
1150                 if (!s)
1151                         continue;
1152                 s--;
1153                 while (s > 0 && name[0]) {
1154                         name += strlen(name) + 1;
1155                         s--;
1156                 }
1157                 if (name[0] == 0) /* Bogus string reference */
1158                         continue;
1159
1160                 dmi_check_onboard_device(type, name, adap);
1161         }
1162 }
1163
1164 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1165 static const char *const acpi_smo8800_ids[] = {
1166         "SMO8800",
1167         "SMO8801",
1168         "SMO8810",
1169         "SMO8811",
1170         "SMO8820",
1171         "SMO8821",
1172         "SMO8830",
1173         "SMO8831",
1174 };
1175
1176 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1177                                              u32 nesting_level,
1178                                              void *context,
1179                                              void **return_value)
1180 {
1181         struct acpi_device_info *info;
1182         acpi_status status;
1183         char *hid;
1184         int i;
1185
1186         status = acpi_get_object_info(obj_handle, &info);
1187         if (ACPI_FAILURE(status))
1188                 return AE_OK;
1189
1190         if (!(info->valid & ACPI_VALID_HID))
1191                 goto smo88xx_not_found;
1192
1193         hid = info->hardware_id.string;
1194         if (!hid)
1195                 goto smo88xx_not_found;
1196
1197         i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1198         if (i < 0)
1199                 goto smo88xx_not_found;
1200
1201         kfree(info);
1202
1203         *return_value = NULL;
1204         return AE_CTRL_TERMINATE;
1205
1206 smo88xx_not_found:
1207         kfree(info);
1208         return AE_OK;
1209 }
1210
1211 static bool is_dell_system_with_lis3lv02d(void)
1212 {
1213         void *err = ERR_PTR(-ENOENT);
1214
1215         if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc."))
1216                 return false;
1217
1218         /*
1219          * Check that ACPI device SMO88xx is present and is functioning.
1220          * Function acpi_get_devices() already filters all ACPI devices
1221          * which are not present or are not functioning.
1222          * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1223          * accelerometer but unfortunately ACPI does not provide any other
1224          * information (like I2C address).
1225          */
1226         acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err);
1227
1228         return !IS_ERR(err);
1229 }
1230
1231 /*
1232  * Accelerometer's I2C address is not specified in DMI nor ACPI,
1233  * so it is needed to define mapping table based on DMI product names.
1234  */
1235 static const struct {
1236         const char *dmi_product_name;
1237         unsigned short i2c_addr;
1238 } dell_lis3lv02d_devices[] = {
1239         /*
1240          * Dell platform team told us that these Latitude devices have
1241          * ST microelectronics accelerometer at I2C address 0x29.
1242          */
1243         { "Latitude E5250",     0x29 },
1244         { "Latitude E5450",     0x29 },
1245         { "Latitude E5550",     0x29 },
1246         { "Latitude E6440",     0x29 },
1247         { "Latitude E6440 ATG", 0x29 },
1248         { "Latitude E6540",     0x29 },
1249         /*
1250          * Additional individual entries were added after verification.
1251          */
1252         { "Latitude 5480",      0x29 },
1253         { "Vostro V131",        0x1d },
1254         { "Vostro 5568",        0x29 },
1255 };
1256
1257 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1258 {
1259         struct i2c_board_info info;
1260         const char *dmi_product_name;
1261         int i;
1262
1263         dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1264         for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1265                 if (strcmp(dmi_product_name,
1266                            dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1267                         break;
1268         }
1269
1270         if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1271                 dev_warn(&priv->pci_dev->dev,
1272                          "Accelerometer lis3lv02d is present on SMBus but its"
1273                          " address is unknown, skipping registration\n");
1274                 return;
1275         }
1276
1277         memset(&info, 0, sizeof(struct i2c_board_info));
1278         info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1279         strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1280         i2c_new_client_device(&priv->adapter, &info);
1281 }
1282
1283 /* Register optional slaves */
1284 static void i801_probe_optional_slaves(struct i801_priv *priv)
1285 {
1286         /* Only register slaves on main SMBus channel */
1287         if (priv->features & FEATURE_IDF)
1288                 return;
1289
1290         if (apanel_addr) {
1291                 struct i2c_board_info info = {
1292                         .addr = apanel_addr,
1293                         .type = "fujitsu_apanel",
1294                 };
1295
1296                 i2c_new_client_device(&priv->adapter, &info);
1297         }
1298
1299         if (dmi_name_in_vendors("FUJITSU"))
1300                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1301
1302         if (is_dell_system_with_lis3lv02d())
1303                 register_dell_lis3lv02d_i2c_device(priv);
1304
1305         /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1306 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1307         if (!priv->mux_drvdata)
1308 #endif
1309                 i2c_register_spd(&priv->adapter);
1310 }
1311 #else
1312 static void __init input_apanel_init(void) {}
1313 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1314 #endif  /* CONFIG_X86 && CONFIG_DMI */
1315
1316 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1317 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1318         .gpio_chip = "gpio_ich",
1319         .values = { 0x02, 0x03 },
1320         .n_values = 2,
1321         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1322         .gpios = { 52, 53 },
1323         .n_gpios = 2,
1324 };
1325
1326 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1327         .gpio_chip = "gpio_ich",
1328         .values = { 0x02, 0x03, 0x01 },
1329         .n_values = 3,
1330         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1331         .gpios = { 52, 53 },
1332         .n_gpios = 2,
1333 };
1334
1335 static const struct dmi_system_id mux_dmi_table[] = {
1336         {
1337                 .matches = {
1338                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1339                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1340                 },
1341                 .driver_data = &i801_mux_config_asus_z8_d12,
1342         },
1343         {
1344                 .matches = {
1345                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1346                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1347                 },
1348                 .driver_data = &i801_mux_config_asus_z8_d12,
1349         },
1350         {
1351                 .matches = {
1352                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1353                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1354                 },
1355                 .driver_data = &i801_mux_config_asus_z8_d12,
1356         },
1357         {
1358                 .matches = {
1359                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1360                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1361                 },
1362                 .driver_data = &i801_mux_config_asus_z8_d12,
1363         },
1364         {
1365                 .matches = {
1366                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1367                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1368                 },
1369                 .driver_data = &i801_mux_config_asus_z8_d12,
1370         },
1371         {
1372                 .matches = {
1373                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1374                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1375                 },
1376                 .driver_data = &i801_mux_config_asus_z8_d12,
1377         },
1378         {
1379                 .matches = {
1380                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1381                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1382                 },
1383                 .driver_data = &i801_mux_config_asus_z8_d18,
1384         },
1385         {
1386                 .matches = {
1387                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1388                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1389                 },
1390                 .driver_data = &i801_mux_config_asus_z8_d18,
1391         },
1392         {
1393                 .matches = {
1394                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1395                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1396                 },
1397                 .driver_data = &i801_mux_config_asus_z8_d12,
1398         },
1399         { }
1400 };
1401
1402 /* Setup multiplexing if needed */
1403 static void i801_add_mux(struct i801_priv *priv)
1404 {
1405         struct device *dev = &priv->adapter.dev;
1406         const struct i801_mux_config *mux_config;
1407         struct i2c_mux_gpio_platform_data gpio_data;
1408         struct gpiod_lookup_table *lookup;
1409         int i;
1410
1411         if (!priv->mux_drvdata)
1412                 return;
1413         mux_config = priv->mux_drvdata;
1414
1415         /* Prepare the platform data */
1416         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1417         gpio_data.parent = priv->adapter.nr;
1418         gpio_data.values = mux_config->values;
1419         gpio_data.n_values = mux_config->n_values;
1420         gpio_data.classes = mux_config->classes;
1421         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1422
1423         /* Register GPIO descriptor lookup table */
1424         lookup = devm_kzalloc(dev,
1425                               struct_size(lookup, table, mux_config->n_gpios + 1),
1426                               GFP_KERNEL);
1427         if (!lookup)
1428                 return;
1429         lookup->dev_id = "i2c-mux-gpio";
1430         for (i = 0; i < mux_config->n_gpios; i++)
1431                 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip,
1432                                                mux_config->gpios[i], "mux", 0);
1433         gpiod_add_lookup_table(lookup);
1434         priv->lookup = lookup;
1435
1436         /*
1437          * Register the mux device, we use PLATFORM_DEVID_NONE here
1438          * because since we are referring to the GPIO chip by name we are
1439          * anyways in deep trouble if there is more than one of these
1440          * devices, and there should likely only be one platform controller
1441          * hub.
1442          */
1443         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1444                                 PLATFORM_DEVID_NONE, &gpio_data,
1445                                 sizeof(struct i2c_mux_gpio_platform_data));
1446         if (IS_ERR(priv->mux_pdev)) {
1447                 gpiod_remove_lookup_table(lookup);
1448                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1449         }
1450 }
1451
1452 static void i801_del_mux(struct i801_priv *priv)
1453 {
1454         platform_device_unregister(priv->mux_pdev);
1455         gpiod_remove_lookup_table(priv->lookup);
1456 }
1457
1458 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1459 {
1460         const struct dmi_system_id *id;
1461         const struct i801_mux_config *mux_config;
1462         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1463         int i;
1464
1465         id = dmi_first_match(mux_dmi_table);
1466         if (id) {
1467                 /* Remove branch classes from trunk */
1468                 mux_config = id->driver_data;
1469                 for (i = 0; i < mux_config->n_values; i++)
1470                         class &= ~mux_config->classes[i];
1471
1472                 /* Remember for later */
1473                 priv->mux_drvdata = mux_config;
1474         }
1475
1476         return class;
1477 }
1478 #else
1479 static inline void i801_add_mux(struct i801_priv *priv) { }
1480 static inline void i801_del_mux(struct i801_priv *priv) { }
1481
1482 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1483 {
1484         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1485 }
1486 #endif
1487
1488 static struct platform_device *
1489 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1490                  struct resource *tco_res)
1491 {
1492         static const struct itco_wdt_platform_data pldata = {
1493                 .name = "Intel PCH",
1494                 .version = 4,
1495         };
1496         struct resource *res;
1497         int ret;
1498
1499         /*
1500          * We must access the NO_REBOOT bit over the Primary to Sideband
1501          * (P2SB) bridge.
1502          */
1503
1504         res = &tco_res[1];
1505         ret = p2sb_bar(pci_dev->bus, 0, res);
1506         if (ret)
1507                 return ERR_PTR(ret);
1508
1509         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1510                 res->start += SBREG_SMBCTRL_DNV;
1511         else
1512                 res->start += SBREG_SMBCTRL;
1513
1514         res->end = res->start + 3;
1515
1516         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1517                                         tco_res, 2, &pldata, sizeof(pldata));
1518 }
1519
1520 static struct platform_device *
1521 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1522                  struct resource *tco_res)
1523 {
1524         static const struct itco_wdt_platform_data pldata = {
1525                 .name = "Intel PCH",
1526                 .version = 6,
1527         };
1528
1529         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1530                                                  tco_res, 1, &pldata, sizeof(pldata));
1531 }
1532
1533 static void i801_add_tco(struct i801_priv *priv)
1534 {
1535         struct pci_dev *pci_dev = priv->pci_dev;
1536         struct resource tco_res[2], *res;
1537         u32 tco_base, tco_ctl;
1538
1539         /* If we have ACPI based watchdog use that instead */
1540         if (acpi_has_watchdog())
1541                 return;
1542
1543         if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1544                 return;
1545
1546         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1547         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1548         if (!(tco_ctl & TCOCTL_EN))
1549                 return;
1550
1551         memset(tco_res, 0, sizeof(tco_res));
1552         /*
1553          * Always populate the main iTCO IO resource here. The second entry
1554          * for NO_REBOOT MMIO is filled by the SPT specific function.
1555          */
1556         res = &tco_res[0];
1557         res->start = tco_base & ~1;
1558         res->end = res->start + 32 - 1;
1559         res->flags = IORESOURCE_IO;
1560
1561         if (priv->features & FEATURE_TCO_CNL)
1562                 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1563         else
1564                 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1565
1566         if (IS_ERR(priv->tco_pdev))
1567                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1568 }
1569
1570 #ifdef CONFIG_ACPI
1571 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1572                                       acpi_physical_address address)
1573 {
1574         return address >= priv->smba &&
1575                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1576 }
1577
1578 static acpi_status
1579 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1580                      u64 *value, void *handler_context, void *region_context)
1581 {
1582         struct i801_priv *priv = handler_context;
1583         struct pci_dev *pdev = priv->pci_dev;
1584         acpi_status status;
1585
1586         /*
1587          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1588          * further access from the driver itself. This device is now owned
1589          * by the system firmware.
1590          */
1591         mutex_lock(&priv->acpi_lock);
1592
1593         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1594                 priv->acpi_reserved = true;
1595
1596                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1597                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1598
1599                 /*
1600                  * BIOS is accessing the host controller so prevent it from
1601                  * suspending automatically from now on.
1602                  */
1603                 pm_runtime_get_sync(&pdev->dev);
1604         }
1605
1606         if ((function & ACPI_IO_MASK) == ACPI_READ)
1607                 status = acpi_os_read_port(address, (u32 *)value, bits);
1608         else
1609                 status = acpi_os_write_port(address, (u32)*value, bits);
1610
1611         mutex_unlock(&priv->acpi_lock);
1612
1613         return status;
1614 }
1615
1616 static int i801_acpi_probe(struct i801_priv *priv)
1617 {
1618         acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1619         acpi_status status;
1620
1621         status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO,
1622                                                     i801_acpi_io_handler, NULL, priv);
1623         if (ACPI_SUCCESS(status))
1624                 return 0;
1625
1626         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1627 }
1628
1629 static void i801_acpi_remove(struct i801_priv *priv)
1630 {
1631         acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1632
1633         acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1634 }
1635 #else
1636 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1637 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1638 #endif
1639
1640 static void i801_setup_hstcfg(struct i801_priv *priv)
1641 {
1642         unsigned char hstcfg = priv->original_hstcfg;
1643
1644         hstcfg &= ~SMBHSTCFG_I2C_EN;    /* SMBus timing */
1645         hstcfg |= SMBHSTCFG_HST_EN;
1646         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1647 }
1648
1649 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1650 {
1651         int err, i;
1652         struct i801_priv *priv;
1653
1654         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1655         if (!priv)
1656                 return -ENOMEM;
1657
1658         i2c_set_adapdata(&priv->adapter, priv);
1659         priv->adapter.owner = THIS_MODULE;
1660         priv->adapter.class = i801_get_adapter_class(priv);
1661         priv->adapter.algo = &smbus_algorithm;
1662         priv->adapter.dev.parent = &dev->dev;
1663         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1664         priv->adapter.retries = 3;
1665         mutex_init(&priv->acpi_lock);
1666
1667         priv->pci_dev = dev;
1668         priv->features = id->driver_data;
1669
1670         /* Disable features on user request */
1671         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1672                 if (priv->features & disable_features & (1 << i))
1673                         dev_notice(&dev->dev, "%s disabled by user\n",
1674                                    i801_feature_names[i]);
1675         }
1676         priv->features &= ~disable_features;
1677
1678         /* The block process call uses block buffer mode */
1679         if (!(priv->features & FEATURE_BLOCK_BUFFER))
1680                 priv->features &= ~FEATURE_BLOCK_PROC;
1681
1682         err = pcim_enable_device(dev);
1683         if (err) {
1684                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1685                         err);
1686                 return err;
1687         }
1688         pcim_pin_device(dev);
1689
1690         /* Determine the address of the SMBus area */
1691         priv->smba = pci_resource_start(dev, SMBBAR);
1692         if (!priv->smba) {
1693                 dev_err(&dev->dev,
1694                         "SMBus base address uninitialized, upgrade BIOS\n");
1695                 return -ENODEV;
1696         }
1697
1698         if (i801_acpi_probe(priv))
1699                 return -ENODEV;
1700
1701         err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME);
1702         if (err) {
1703                 dev_err(&dev->dev,
1704                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1705                         priv->smba,
1706                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1707                 i801_acpi_remove(priv);
1708                 return err;
1709         }
1710
1711         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1712         i801_setup_hstcfg(priv);
1713         if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1714                 dev_info(&dev->dev, "Enabling SMBus device\n");
1715
1716         if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1717                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1718                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1719                 priv->features &= ~FEATURE_IRQ;
1720         }
1721         if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1722                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1723
1724         /* Clear special mode bits */
1725         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1726                 outb_p(inb_p(SMBAUXCTL(priv)) &
1727                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1728
1729         /* Default timeout in interrupt mode: 200 ms */
1730         priv->adapter.timeout = HZ / 5;
1731
1732         if (dev->irq == IRQ_NOTCONNECTED)
1733                 priv->features &= ~FEATURE_IRQ;
1734
1735         if (priv->features & FEATURE_IRQ) {
1736                 u16 pcists;
1737
1738                 /* Complain if an interrupt is already pending */
1739                 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1740                 if (pcists & PCI_STATUS_INTERRUPT)
1741                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1742         }
1743
1744         if (priv->features & FEATURE_IRQ) {
1745                 init_completion(&priv->done);
1746
1747                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1748                                        IRQF_SHARED, DRV_NAME, priv);
1749                 if (err) {
1750                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1751                                 dev->irq, err);
1752                         priv->features &= ~FEATURE_IRQ;
1753                 }
1754         }
1755         dev_info(&dev->dev, "SMBus using %s\n",
1756                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1757
1758         /* Host notification uses an interrupt */
1759         if (!(priv->features & FEATURE_IRQ))
1760                 priv->features &= ~FEATURE_HOST_NOTIFY;
1761
1762         /* Remember original Interrupt and Host Notify settings */
1763         priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL;
1764         if (priv->features & FEATURE_HOST_NOTIFY)
1765                 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1766
1767         i801_add_tco(priv);
1768
1769         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1770                 "SMBus I801 adapter at %04lx", priv->smba);
1771         err = i2c_add_adapter(&priv->adapter);
1772         if (err) {
1773                 i801_acpi_remove(priv);
1774                 return err;
1775         }
1776
1777         i801_enable_host_notify(&priv->adapter);
1778
1779         i801_probe_optional_slaves(priv);
1780         /* We ignore errors - multiplexing is optional */
1781         i801_add_mux(priv);
1782
1783         pci_set_drvdata(dev, priv);
1784
1785         dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1786         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1787         pm_runtime_use_autosuspend(&dev->dev);
1788         pm_runtime_put_autosuspend(&dev->dev);
1789         pm_runtime_allow(&dev->dev);
1790
1791         return 0;
1792 }
1793
1794 static void i801_remove(struct pci_dev *dev)
1795 {
1796         struct i801_priv *priv = pci_get_drvdata(dev);
1797
1798         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1799         i801_disable_host_notify(priv);
1800         i801_del_mux(priv);
1801         i2c_del_adapter(&priv->adapter);
1802         i801_acpi_remove(priv);
1803         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1804
1805         platform_device_unregister(priv->tco_pdev);
1806
1807         /* if acpi_reserved is set then usage_count is incremented already */
1808         if (!priv->acpi_reserved)
1809                 pm_runtime_get_noresume(&dev->dev);
1810
1811         /*
1812          * do not call pci_disable_device(dev) since it can cause hard hangs on
1813          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1814          */
1815 }
1816
1817 static void i801_shutdown(struct pci_dev *dev)
1818 {
1819         struct i801_priv *priv = pci_get_drvdata(dev);
1820
1821         /* Restore config registers to avoid hard hang on some systems */
1822         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1823         i801_disable_host_notify(priv);
1824         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1825 }
1826
1827 #ifdef CONFIG_PM_SLEEP
1828 static int i801_suspend(struct device *dev)
1829 {
1830         struct i801_priv *priv = dev_get_drvdata(dev);
1831
1832         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1833         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1834         return 0;
1835 }
1836
1837 static int i801_resume(struct device *dev)
1838 {
1839         struct i801_priv *priv = dev_get_drvdata(dev);
1840
1841         i801_setup_hstcfg(priv);
1842         i801_enable_host_notify(&priv->adapter);
1843
1844         return 0;
1845 }
1846 #endif
1847
1848 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1849
1850 static struct pci_driver i801_driver = {
1851         .name           = DRV_NAME,
1852         .id_table       = i801_ids,
1853         .probe          = i801_probe,
1854         .remove         = i801_remove,
1855         .shutdown       = i801_shutdown,
1856         .driver         = {
1857                 .pm     = &i801_pm_ops,
1858                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1859         },
1860 };
1861
1862 static int __init i2c_i801_init(void)
1863 {
1864         if (dmi_name_in_vendors("FUJITSU"))
1865                 input_apanel_init();
1866         return pci_register_driver(&i801_driver);
1867 }
1868
1869 static void __exit i2c_i801_exit(void)
1870 {
1871         pci_unregister_driver(&i801_driver);
1872 }
1873
1874 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1875 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1876 MODULE_DESCRIPTION("I801 SMBus driver");
1877 MODULE_LICENSE("GPL");
1878
1879 module_init(i2c_i801_init);
1880 module_exit(i2c_i801_exit);