2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
21 * Supports the following Intel I/O Controller Hubs (ICH):
24 * region SMBus Block proc. block
25 * Chip name PCI ID size PEC buffer call read
26 * ---------------------------------------------------------------------------
27 * 82801AA (ICH) 0x2413 16 no no no no
28 * 82801AB (ICH0) 0x2423 16 no no no no
29 * 82801BA (ICH2) 0x2443 16 no no no no
30 * 82801CA (ICH3) 0x2483 32 soft no no no
31 * 82801DB (ICH4) 0x24c3 32 hard yes no no
32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
33 * 6300ESB 0x25a4 32 hard yes yes yes
34 * 82801F (ICH6) 0x266a 32 hard yes yes yes
35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
36 * 82801G (ICH7) 0x27da 32 hard yes yes yes
37 * 82801H (ICH8) 0x283e 32 hard yes yes yes
38 * 82801I (ICH9) 0x2930 32 hard yes yes yes
39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
40 * ICH10 0x3a30 32 hard yes yes yes
41 * ICH10 0x3a60 32 hard yes yes yes
42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
61 * Braswell (SOC) 0x2292 32 hard yes yes yes
62 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
63 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
64 * DNV (SOC) 0x19df 32 hard yes yes yes
65 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
66 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
67 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
68 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
69 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
70 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
71 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
72 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
73 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
74 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
76 * Features supported by this driver:
80 * Block process call transaction no
81 * I2C block read transaction yes (doesn't use the block buffer)
83 * SMBus Host Notify yes
84 * Interrupt processing yes
86 * See the file Documentation/i2c/busses/i2c-i801 for details.
89 #include <linux/interrupt.h>
90 #include <linux/module.h>
91 #include <linux/pci.h>
92 #include <linux/kernel.h>
93 #include <linux/stddef.h>
94 #include <linux/delay.h>
95 #include <linux/ioport.h>
96 #include <linux/init.h>
97 #include <linux/i2c.h>
98 #include <linux/i2c-smbus.h>
99 #include <linux/acpi.h>
100 #include <linux/io.h>
101 #include <linux/dmi.h>
102 #include <linux/slab.h>
103 #include <linux/wait.h>
104 #include <linux/err.h>
105 #include <linux/platform_device.h>
106 #include <linux/platform_data/itco_wdt.h>
107 #include <linux/pm_runtime.h>
109 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
110 #include <linux/gpio.h>
111 #include <linux/platform_data/i2c-mux-gpio.h>
114 /* I801 SMBus address offsets */
115 #define SMBHSTSTS(p) (0 + (p)->smba)
116 #define SMBHSTCNT(p) (2 + (p)->smba)
117 #define SMBHSTCMD(p) (3 + (p)->smba)
118 #define SMBHSTADD(p) (4 + (p)->smba)
119 #define SMBHSTDAT0(p) (5 + (p)->smba)
120 #define SMBHSTDAT1(p) (6 + (p)->smba)
121 #define SMBBLKDAT(p) (7 + (p)->smba)
122 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
123 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
124 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
125 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
126 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
127 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
129 /* PCI Address Constants */
131 #define SMBPCICTL 0x004
132 #define SMBPCISTS 0x006
133 #define SMBHSTCFG 0x040
134 #define TCOBASE 0x050
137 #define ACPIBASE 0x040
138 #define ACPIBASE_SMI_OFF 0x030
139 #define ACPICTRL 0x044
140 #define ACPICTRL_EN 0x080
142 #define SBREG_BAR 0x10
143 #define SBREG_SMBCTRL 0xc6000c
144 #define SBREG_SMBCTRL_DNV 0xcf000c
146 /* Host status bits for SMBPCISTS */
147 #define SMBPCISTS_INTS BIT(3)
149 /* Control bits for SMBPCICTL */
150 #define SMBPCICTL_INTDIS BIT(10)
152 /* Host configuration bits for SMBHSTCFG */
153 #define SMBHSTCFG_HST_EN BIT(0)
154 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
155 #define SMBHSTCFG_I2C_EN BIT(2)
156 #define SMBHSTCFG_SPD_WD BIT(4)
158 /* TCO configuration bits for TCOCTL */
159 #define TCOCTL_EN BIT(8)
161 /* Auxiliary status register bits, ICH4+ only */
162 #define SMBAUXSTS_CRCE BIT(0)
163 #define SMBAUXSTS_STCO BIT(1)
165 /* Auxiliary control register bits, ICH4+ only */
166 #define SMBAUXCTL_CRC BIT(0)
167 #define SMBAUXCTL_E32B BIT(1)
170 #define MAX_RETRIES 400
172 /* I801 command constants */
173 #define I801_QUICK 0x00
174 #define I801_BYTE 0x04
175 #define I801_BYTE_DATA 0x08
176 #define I801_WORD_DATA 0x0C
177 #define I801_PROC_CALL 0x10 /* unimplemented */
178 #define I801_BLOCK_DATA 0x14
179 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
181 /* I801 Host Control register bits */
182 #define SMBHSTCNT_INTREN BIT(0)
183 #define SMBHSTCNT_KILL BIT(1)
184 #define SMBHSTCNT_LAST_BYTE BIT(5)
185 #define SMBHSTCNT_START BIT(6)
186 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
188 /* I801 Hosts Status register bits */
189 #define SMBHSTSTS_BYTE_DONE BIT(7)
190 #define SMBHSTSTS_INUSE_STS BIT(6)
191 #define SMBHSTSTS_SMBALERT_STS BIT(5)
192 #define SMBHSTSTS_FAILED BIT(4)
193 #define SMBHSTSTS_BUS_ERR BIT(3)
194 #define SMBHSTSTS_DEV_ERR BIT(2)
195 #define SMBHSTSTS_INTR BIT(1)
196 #define SMBHSTSTS_HOST_BUSY BIT(0)
198 /* Host Notify Status register bits */
199 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
201 /* Host Notify Command register bits */
202 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
204 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
207 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
210 /* Older devices have their ID defined in <linux/pci_ids.h> */
211 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
212 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
213 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
214 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
216 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
218 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
219 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
220 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
221 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
222 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
223 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
224 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
225 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
226 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
227 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
228 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
229 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
230 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
231 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
232 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
233 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
234 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
235 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
236 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
237 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
238 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
239 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
240 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
241 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
242 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
243 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
244 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
246 struct i801_mux_config {
251 unsigned gpios[2]; /* Relative to gpio_chip->base */
256 struct i2c_adapter adapter;
258 unsigned char original_hstcfg;
259 unsigned char original_slvcmd;
260 struct pci_dev *pci_dev;
261 unsigned int features;
264 wait_queue_head_t waitq;
267 /* Command state used by isr for byte-by-byte block transactions */
274 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
275 const struct i801_mux_config *mux_drvdata;
276 struct platform_device *mux_pdev;
278 struct platform_device *tco_pdev;
281 * If set to true the host controller registers are reserved for
282 * ACPI AML use. Protected by acpi_lock.
285 struct mutex acpi_lock;
288 #define FEATURE_SMBUS_PEC BIT(0)
289 #define FEATURE_BLOCK_BUFFER BIT(1)
290 #define FEATURE_BLOCK_PROC BIT(2)
291 #define FEATURE_I2C_BLOCK_READ BIT(3)
292 #define FEATURE_IRQ BIT(4)
293 #define FEATURE_HOST_NOTIFY BIT(5)
294 /* Not really a feature, but it's convenient to handle it as such */
295 #define FEATURE_IDF BIT(15)
296 #define FEATURE_TCO BIT(16)
298 static const char *i801_feature_names[] = {
301 "Block process call",
307 static unsigned int disable_features;
308 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
309 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
310 "\t\t 0x01 disable SMBus PEC\n"
311 "\t\t 0x02 disable the block buffer\n"
312 "\t\t 0x08 disable the I2C block read functionality\n"
313 "\t\t 0x10 don't use interrupts\n"
314 "\t\t 0x20 disable SMBus Host Notify ");
316 /* Make sure the SMBus host is ready to start transmitting.
317 Return 0 if it is, -EBUSY if it is not. */
318 static int i801_check_pre(struct i801_priv *priv)
322 status = inb_p(SMBHSTSTS(priv));
323 if (status & SMBHSTSTS_HOST_BUSY) {
324 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
328 status &= STATUS_FLAGS;
330 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
332 outb_p(status, SMBHSTSTS(priv));
333 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
335 dev_err(&priv->pci_dev->dev,
336 "Failed clearing status flags (%02x)\n",
343 * Clear CRC status if needed.
344 * During normal operation, i801_check_post() takes care
345 * of it after every operation. We do it here only in case
346 * the hardware was already in this state when the driver
349 if (priv->features & FEATURE_SMBUS_PEC) {
350 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
352 dev_dbg(&priv->pci_dev->dev,
353 "Clearing aux status flags (%02x)\n", status);
354 outb_p(status, SMBAUXSTS(priv));
355 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
357 dev_err(&priv->pci_dev->dev,
358 "Failed clearing aux status flags (%02x)\n",
369 * Convert the status register to an error code, and clear it.
370 * Note that status only contains the bits we want to clear, not the
371 * actual register value.
373 static int i801_check_post(struct i801_priv *priv, int status)
378 * If the SMBus is still busy, we give up
379 * Note: This timeout condition only happens when using polling
380 * transactions. For interrupt operation, NAK/timeout is indicated by
383 if (unlikely(status < 0)) {
384 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
385 /* try to stop the current command */
386 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
387 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
389 usleep_range(1000, 2000);
390 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
393 /* Check if it worked */
394 status = inb_p(SMBHSTSTS(priv));
395 if ((status & SMBHSTSTS_HOST_BUSY) ||
396 !(status & SMBHSTSTS_FAILED))
397 dev_err(&priv->pci_dev->dev,
398 "Failed terminating the transaction\n");
399 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
403 if (status & SMBHSTSTS_FAILED) {
405 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
407 if (status & SMBHSTSTS_DEV_ERR) {
409 * This may be a PEC error, check and clear it.
411 * AUXSTS is handled differently from HSTSTS.
412 * For HSTSTS, i801_isr() or i801_wait_intr()
413 * has already cleared the error bits in hardware,
414 * and we are passed a copy of the original value
416 * For AUXSTS, the hardware register is left
417 * for us to handle here.
418 * This is asymmetric, slightly iffy, but safe,
419 * since all this code is serialized and the CRCE
420 * bit is harmless as long as it's cleared before
421 * the next operation.
423 if ((priv->features & FEATURE_SMBUS_PEC) &&
424 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
425 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
427 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
430 dev_dbg(&priv->pci_dev->dev, "No response\n");
433 if (status & SMBHSTSTS_BUS_ERR) {
435 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
438 /* Clear status flags except BYTE_DONE, to be cleared by caller */
439 outb_p(status, SMBHSTSTS(priv));
444 /* Wait for BUSY being cleared and either INTR or an error flag being set */
445 static int i801_wait_intr(struct i801_priv *priv)
450 /* We will always wait for a fraction of a second! */
452 usleep_range(250, 500);
453 status = inb_p(SMBHSTSTS(priv));
454 } while (((status & SMBHSTSTS_HOST_BUSY) ||
455 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
456 (timeout++ < MAX_RETRIES));
458 if (timeout > MAX_RETRIES) {
459 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
462 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
465 /* Wait for either BYTE_DONE or an error flag being set */
466 static int i801_wait_byte_done(struct i801_priv *priv)
471 /* We will always wait for a fraction of a second! */
473 usleep_range(250, 500);
474 status = inb_p(SMBHSTSTS(priv));
475 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
476 (timeout++ < MAX_RETRIES));
478 if (timeout > MAX_RETRIES) {
479 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
482 return status & STATUS_ERROR_FLAGS;
485 static int i801_transaction(struct i801_priv *priv, int xact)
489 const struct i2c_adapter *adap = &priv->adapter;
491 result = i801_check_pre(priv);
495 if (priv->features & FEATURE_IRQ) {
496 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
498 result = wait_event_timeout(priv->waitq,
499 (status = priv->status),
503 dev_warn(&priv->pci_dev->dev,
504 "Timeout waiting for interrupt!\n");
507 return i801_check_post(priv, status);
510 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
511 * SMBSCMD are passed in xact */
512 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
514 status = i801_wait_intr(priv);
515 return i801_check_post(priv, status);
518 static int i801_block_transaction_by_block(struct i801_priv *priv,
519 union i2c_smbus_data *data,
520 char read_write, int hwpec)
525 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
527 /* Use 32-byte buffer to process this transaction */
528 if (read_write == I2C_SMBUS_WRITE) {
529 len = data->block[0];
530 outb_p(len, SMBHSTDAT0(priv));
531 for (i = 0; i < len; i++)
532 outb_p(data->block[i+1], SMBBLKDAT(priv));
535 status = i801_transaction(priv, I801_BLOCK_DATA |
536 (hwpec ? SMBHSTCNT_PEC_EN : 0));
540 if (read_write == I2C_SMBUS_READ) {
541 len = inb_p(SMBHSTDAT0(priv));
542 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
545 data->block[0] = len;
546 for (i = 0; i < len; i++)
547 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
552 static void i801_isr_byte_done(struct i801_priv *priv)
555 /* For SMBus block reads, length is received with first byte */
556 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
557 (priv->count == 0)) {
558 priv->len = inb_p(SMBHSTDAT0(priv));
559 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
560 dev_err(&priv->pci_dev->dev,
561 "Illegal SMBus block read size %d\n",
564 priv->len = I2C_SMBUS_BLOCK_MAX;
566 dev_dbg(&priv->pci_dev->dev,
567 "SMBus block read size is %d\n",
570 priv->data[-1] = priv->len;
574 if (priv->count < priv->len)
575 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
577 dev_dbg(&priv->pci_dev->dev,
578 "Discarding extra byte on block read\n");
580 /* Set LAST_BYTE for last byte of read transaction */
581 if (priv->count == priv->len - 1)
582 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
584 } else if (priv->count < priv->len - 1) {
585 /* Write next byte, except for IRQ after last byte */
586 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
589 /* Clear BYTE_DONE to continue with next byte */
590 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
593 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
597 addr = inb_p(SMBNTFDADD(priv)) >> 1;
600 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
601 * always returns 0. Our current implementation doesn't provide
602 * data, so we just ignore it.
604 i2c_handle_smbus_host_notify(&priv->adapter, addr);
606 /* clear Host Notify bit and return */
607 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
612 * There are three kinds of interrupts:
614 * 1) i801 signals transaction completion with one of these interrupts:
616 * DEV_ERR - Invalid command, NAK or communication timeout
617 * BUS_ERR - SMI# transaction collision
618 * FAILED - transaction was canceled due to a KILL request
619 * When any of these occur, update ->status and wake up the waitq.
620 * ->status must be cleared before kicking off the next transaction.
622 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
623 * occurs for each byte of a byte-by-byte to prepare the next byte.
625 * 3) Host Notify interrupts
627 static irqreturn_t i801_isr(int irq, void *dev_id)
629 struct i801_priv *priv = dev_id;
633 /* Confirm this is our interrupt */
634 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
635 if (!(pcists & SMBPCISTS_INTS))
638 if (priv->features & FEATURE_HOST_NOTIFY) {
639 status = inb_p(SMBSLVSTS(priv));
640 if (status & SMBSLVSTS_HST_NTFY_STS)
641 return i801_host_notify_isr(priv);
644 status = inb_p(SMBHSTSTS(priv));
645 if (status & SMBHSTSTS_BYTE_DONE)
646 i801_isr_byte_done(priv);
649 * Clear irq sources and report transaction result.
650 * ->status must be cleared before the next transaction is started.
652 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
654 outb_p(status, SMBHSTSTS(priv));
655 priv->status = status;
656 wake_up(&priv->waitq);
663 * For "byte-by-byte" block transactions:
664 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
665 * I2C read uses cmd=I801_I2C_BLOCK_DATA
667 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
668 union i2c_smbus_data *data,
669 char read_write, int command,
676 const struct i2c_adapter *adap = &priv->adapter;
678 result = i801_check_pre(priv);
682 len = data->block[0];
684 if (read_write == I2C_SMBUS_WRITE) {
685 outb_p(len, SMBHSTDAT0(priv));
686 outb_p(data->block[1], SMBBLKDAT(priv));
689 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
690 read_write == I2C_SMBUS_READ)
691 smbcmd = I801_I2C_BLOCK_DATA;
693 smbcmd = I801_BLOCK_DATA;
695 if (priv->features & FEATURE_IRQ) {
696 priv->is_read = (read_write == I2C_SMBUS_READ);
697 if (len == 1 && priv->is_read)
698 smbcmd |= SMBHSTCNT_LAST_BYTE;
699 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
702 priv->data = &data->block[1];
704 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
705 result = wait_event_timeout(priv->waitq,
706 (status = priv->status),
710 dev_warn(&priv->pci_dev->dev,
711 "Timeout waiting for interrupt!\n");
714 return i801_check_post(priv, status);
717 for (i = 1; i <= len; i++) {
718 if (i == len && read_write == I2C_SMBUS_READ)
719 smbcmd |= SMBHSTCNT_LAST_BYTE;
720 outb_p(smbcmd, SMBHSTCNT(priv));
723 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
726 status = i801_wait_byte_done(priv);
730 if (i == 1 && read_write == I2C_SMBUS_READ
731 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
732 len = inb_p(SMBHSTDAT0(priv));
733 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
734 dev_err(&priv->pci_dev->dev,
735 "Illegal SMBus block read size %d\n",
738 while (inb_p(SMBHSTSTS(priv)) &
740 outb_p(SMBHSTSTS_BYTE_DONE,
742 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
745 data->block[0] = len;
748 /* Retrieve/store value in SMBBLKDAT */
749 if (read_write == I2C_SMBUS_READ)
750 data->block[i] = inb_p(SMBBLKDAT(priv));
751 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
752 outb_p(data->block[i+1], SMBBLKDAT(priv));
754 /* signals SMBBLKDAT ready */
755 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
758 status = i801_wait_intr(priv);
760 return i801_check_post(priv, status);
763 static int i801_set_block_buffer_mode(struct i801_priv *priv)
765 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
766 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
771 /* Block transaction function */
772 static int i801_block_transaction(struct i801_priv *priv,
773 union i2c_smbus_data *data, char read_write,
774 int command, int hwpec)
779 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
780 if (read_write == I2C_SMBUS_WRITE) {
781 /* set I2C_EN bit in configuration register */
782 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
783 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
784 hostc | SMBHSTCFG_I2C_EN);
785 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
786 dev_err(&priv->pci_dev->dev,
787 "I2C block read is unsupported!\n");
792 if (read_write == I2C_SMBUS_WRITE
793 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
794 if (data->block[0] < 1)
796 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
797 data->block[0] = I2C_SMBUS_BLOCK_MAX;
799 data->block[0] = 32; /* max for SMBus block reads */
802 /* Experience has shown that the block buffer can only be used for
803 SMBus (not I2C) block transactions, even though the datasheet
804 doesn't mention this limitation. */
805 if ((priv->features & FEATURE_BLOCK_BUFFER)
806 && command != I2C_SMBUS_I2C_BLOCK_DATA
807 && i801_set_block_buffer_mode(priv) == 0)
808 result = i801_block_transaction_by_block(priv, data,
811 result = i801_block_transaction_byte_by_byte(priv, data,
815 if (command == I2C_SMBUS_I2C_BLOCK_DATA
816 && read_write == I2C_SMBUS_WRITE) {
817 /* restore saved configuration register value */
818 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
823 /* Return negative errno on error. */
824 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
825 unsigned short flags, char read_write, u8 command,
826 int size, union i2c_smbus_data *data)
830 int ret = 0, xact = 0;
831 struct i801_priv *priv = i2c_get_adapdata(adap);
833 mutex_lock(&priv->acpi_lock);
834 if (priv->acpi_reserved) {
835 mutex_unlock(&priv->acpi_lock);
839 pm_runtime_get_sync(&priv->pci_dev->dev);
841 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
842 && size != I2C_SMBUS_QUICK
843 && size != I2C_SMBUS_I2C_BLOCK_DATA;
846 case I2C_SMBUS_QUICK:
847 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
852 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
854 if (read_write == I2C_SMBUS_WRITE)
855 outb_p(command, SMBHSTCMD(priv));
858 case I2C_SMBUS_BYTE_DATA:
859 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
861 outb_p(command, SMBHSTCMD(priv));
862 if (read_write == I2C_SMBUS_WRITE)
863 outb_p(data->byte, SMBHSTDAT0(priv));
864 xact = I801_BYTE_DATA;
866 case I2C_SMBUS_WORD_DATA:
867 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
869 outb_p(command, SMBHSTCMD(priv));
870 if (read_write == I2C_SMBUS_WRITE) {
871 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
872 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
874 xact = I801_WORD_DATA;
876 case I2C_SMBUS_BLOCK_DATA:
877 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
879 outb_p(command, SMBHSTCMD(priv));
882 case I2C_SMBUS_I2C_BLOCK_DATA:
884 * NB: page 240 of ICH5 datasheet shows that the R/#W
885 * bit should be cleared here, even when reading.
886 * However if SPD Write Disable is set (Lynx Point and later),
887 * the read will fail if we don't set the R/#W bit.
889 outb_p(((addr & 0x7f) << 1) |
890 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
891 (read_write & 0x01) : 0),
893 if (read_write == I2C_SMBUS_READ) {
894 /* NB: page 240 of ICH5 datasheet also shows
895 * that DATA1 is the cmd field when reading */
896 outb_p(command, SMBHSTDAT1(priv));
898 outb_p(command, SMBHSTCMD(priv));
902 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
908 if (hwpec) /* enable/disable hardware PEC */
909 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
911 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
915 ret = i801_block_transaction(priv, data, read_write, size,
918 ret = i801_transaction(priv, xact);
920 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
921 time, so we forcibly disable it after every transaction. Turn off
922 E32B for the same reason. */
924 outb_p(inb_p(SMBAUXCTL(priv)) &
925 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
931 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
934 switch (xact & 0x7f) {
935 case I801_BYTE: /* Result put in SMBHSTDAT0 */
937 data->byte = inb_p(SMBHSTDAT0(priv));
940 data->word = inb_p(SMBHSTDAT0(priv)) +
941 (inb_p(SMBHSTDAT1(priv)) << 8);
946 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
947 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
948 mutex_unlock(&priv->acpi_lock);
953 static u32 i801_func(struct i2c_adapter *adapter)
955 struct i801_priv *priv = i2c_get_adapdata(adapter);
957 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
958 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
959 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
960 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
961 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
962 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
963 ((priv->features & FEATURE_HOST_NOTIFY) ?
964 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
967 static void i801_enable_host_notify(struct i2c_adapter *adapter)
969 struct i801_priv *priv = i2c_get_adapdata(adapter);
971 if (!(priv->features & FEATURE_HOST_NOTIFY))
974 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
975 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
978 /* clear Host Notify bit to allow a new notification */
979 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
982 static void i801_disable_host_notify(struct i801_priv *priv)
984 if (!(priv->features & FEATURE_HOST_NOTIFY))
987 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
990 static const struct i2c_algorithm smbus_algorithm = {
991 .smbus_xfer = i801_access,
992 .functionality = i801_func,
995 static const struct pci_device_id i801_ids[] = {
996 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
997 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
998 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
999 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
1000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
1001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1002 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1003 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1047 MODULE_DEVICE_TABLE(pci, i801_ids);
1049 #if defined CONFIG_X86 && defined CONFIG_DMI
1050 static unsigned char apanel_addr;
1052 /* Scan the system ROM for the signature "FJKEYINF" */
1053 static __init const void __iomem *bios_signature(const void __iomem *bios)
1056 const unsigned char signature[] = "FJKEYINF";
1058 for (offset = 0; offset < 0x10000; offset += 0x10) {
1059 if (check_signature(bios + offset, signature,
1060 sizeof(signature)-1))
1061 return bios + offset;
1066 static void __init input_apanel_init(void)
1069 const void __iomem *p;
1071 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1072 p = bios_signature(bios);
1074 /* just use the first address */
1075 apanel_addr = readb(p + 8 + 3) >> 1;
1080 struct dmi_onboard_device_info {
1083 unsigned short i2c_addr;
1084 const char *i2c_type;
1087 static const struct dmi_onboard_device_info dmi_devices[] = {
1088 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1089 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1090 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1093 static void dmi_check_onboard_device(u8 type, const char *name,
1094 struct i2c_adapter *adap)
1097 struct i2c_board_info info;
1099 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1100 /* & ~0x80, ignore enabled/disabled bit */
1101 if ((type & ~0x80) != dmi_devices[i].type)
1103 if (strcasecmp(name, dmi_devices[i].name))
1106 memset(&info, 0, sizeof(struct i2c_board_info));
1107 info.addr = dmi_devices[i].i2c_addr;
1108 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1109 i2c_new_device(adap, &info);
1114 /* We use our own function to check for onboard devices instead of
1115 dmi_find_device() as some buggy BIOS's have the devices we are interested
1116 in marked as disabled */
1117 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1124 count = (dm->length - sizeof(struct dmi_header)) / 2;
1125 for (i = 0; i < count; i++) {
1126 const u8 *d = (char *)(dm + 1) + (i * 2);
1127 const char *name = ((char *) dm) + dm->length;
1134 while (s > 0 && name[0]) {
1135 name += strlen(name) + 1;
1138 if (name[0] == 0) /* Bogus string reference */
1141 dmi_check_onboard_device(type, name, adap);
1145 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1146 static const char *const acpi_smo8800_ids[] = {
1157 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1160 void **return_value)
1162 struct acpi_device_info *info;
1167 status = acpi_get_object_info(obj_handle, &info);
1168 if (!ACPI_SUCCESS(status) || !(info->valid & ACPI_VALID_HID))
1171 hid = info->hardware_id.string;
1175 for (i = 0; i < ARRAY_SIZE(acpi_smo8800_ids); ++i) {
1176 if (strcmp(hid, acpi_smo8800_ids[i]) == 0) {
1177 *((bool *)return_value) = true;
1178 return AE_CTRL_TERMINATE;
1185 static bool is_dell_system_with_lis3lv02d(void)
1190 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1191 if (strcmp(vendor, "Dell Inc.") != 0)
1195 * Check that ACPI device SMO88xx is present and is functioning.
1196 * Function acpi_get_devices() already filters all ACPI devices
1197 * which are not present or are not functioning.
1198 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1199 * accelerometer but unfortunately ACPI does not provide any other
1200 * information (like I2C address).
1203 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
1210 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1211 * so it is needed to define mapping table based on DMI product names.
1213 static const struct {
1214 const char *dmi_product_name;
1215 unsigned short i2c_addr;
1216 } dell_lis3lv02d_devices[] = {
1218 * Dell platform team told us that these Latitude devices have
1219 * ST microelectronics accelerometer at I2C address 0x29.
1221 { "Latitude E5250", 0x29 },
1222 { "Latitude E5450", 0x29 },
1223 { "Latitude E5550", 0x29 },
1224 { "Latitude E6440", 0x29 },
1225 { "Latitude E6440 ATG", 0x29 },
1226 { "Latitude E6540", 0x29 },
1228 * Additional individual entries were added after verification.
1230 { "Vostro V131", 0x1d },
1233 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1235 struct i2c_board_info info;
1236 const char *dmi_product_name;
1239 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1240 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1241 if (strcmp(dmi_product_name,
1242 dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1246 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1247 dev_warn(&priv->pci_dev->dev,
1248 "Accelerometer lis3lv02d is present on SMBus but its"
1249 " address is unknown, skipping registration\n");
1253 memset(&info, 0, sizeof(struct i2c_board_info));
1254 info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1255 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1256 i2c_new_device(&priv->adapter, &info);
1259 /* Register optional slaves */
1260 static void i801_probe_optional_slaves(struct i801_priv *priv)
1262 /* Only register slaves on main SMBus channel */
1263 if (priv->features & FEATURE_IDF)
1267 struct i2c_board_info info;
1269 memset(&info, 0, sizeof(struct i2c_board_info));
1270 info.addr = apanel_addr;
1271 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1272 i2c_new_device(&priv->adapter, &info);
1275 if (dmi_name_in_vendors("FUJITSU"))
1276 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1278 if (is_dell_system_with_lis3lv02d())
1279 register_dell_lis3lv02d_i2c_device(priv);
1282 static void __init input_apanel_init(void) {}
1283 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1284 #endif /* CONFIG_X86 && CONFIG_DMI */
1286 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1287 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1288 .gpio_chip = "gpio_ich",
1289 .values = { 0x02, 0x03 },
1291 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1292 .gpios = { 52, 53 },
1296 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1297 .gpio_chip = "gpio_ich",
1298 .values = { 0x02, 0x03, 0x01 },
1300 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1301 .gpios = { 52, 53 },
1305 static const struct dmi_system_id mux_dmi_table[] = {
1308 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1309 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1311 .driver_data = &i801_mux_config_asus_z8_d12,
1315 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1316 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1318 .driver_data = &i801_mux_config_asus_z8_d12,
1322 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1323 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1325 .driver_data = &i801_mux_config_asus_z8_d12,
1329 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1330 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1332 .driver_data = &i801_mux_config_asus_z8_d12,
1336 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1337 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1339 .driver_data = &i801_mux_config_asus_z8_d12,
1343 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1344 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1346 .driver_data = &i801_mux_config_asus_z8_d12,
1350 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1351 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1353 .driver_data = &i801_mux_config_asus_z8_d18,
1357 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1358 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1360 .driver_data = &i801_mux_config_asus_z8_d18,
1364 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1365 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1367 .driver_data = &i801_mux_config_asus_z8_d12,
1372 /* Setup multiplexing if needed */
1373 static int i801_add_mux(struct i801_priv *priv)
1375 struct device *dev = &priv->adapter.dev;
1376 const struct i801_mux_config *mux_config;
1377 struct i2c_mux_gpio_platform_data gpio_data;
1380 if (!priv->mux_drvdata)
1382 mux_config = priv->mux_drvdata;
1384 /* Prepare the platform data */
1385 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1386 gpio_data.parent = priv->adapter.nr;
1387 gpio_data.values = mux_config->values;
1388 gpio_data.n_values = mux_config->n_values;
1389 gpio_data.classes = mux_config->classes;
1390 gpio_data.gpio_chip = mux_config->gpio_chip;
1391 gpio_data.gpios = mux_config->gpios;
1392 gpio_data.n_gpios = mux_config->n_gpios;
1393 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1395 /* Register the mux device */
1396 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1397 PLATFORM_DEVID_AUTO, &gpio_data,
1398 sizeof(struct i2c_mux_gpio_platform_data));
1399 if (IS_ERR(priv->mux_pdev)) {
1400 err = PTR_ERR(priv->mux_pdev);
1401 priv->mux_pdev = NULL;
1402 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1409 static void i801_del_mux(struct i801_priv *priv)
1412 platform_device_unregister(priv->mux_pdev);
1415 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1417 const struct dmi_system_id *id;
1418 const struct i801_mux_config *mux_config;
1419 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1422 id = dmi_first_match(mux_dmi_table);
1424 /* Remove branch classes from trunk */
1425 mux_config = id->driver_data;
1426 for (i = 0; i < mux_config->n_values; i++)
1427 class &= ~mux_config->classes[i];
1429 /* Remember for later */
1430 priv->mux_drvdata = mux_config;
1436 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1437 static inline void i801_del_mux(struct i801_priv *priv) { }
1439 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1441 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1445 static const struct itco_wdt_platform_data tco_platform_data = {
1446 .name = "Intel PCH",
1450 static DEFINE_SPINLOCK(p2sb_spinlock);
1452 static void i801_add_tco(struct i801_priv *priv)
1454 struct pci_dev *pci_dev = priv->pci_dev;
1455 struct resource tco_res[3], *res;
1456 struct platform_device *pdev;
1458 u32 tco_base, tco_ctl;
1459 u32 base_addr, ctrl_val;
1463 if (!(priv->features & FEATURE_TCO))
1466 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1467 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1468 if (!(tco_ctl & TCOCTL_EN))
1471 memset(tco_res, 0, sizeof(tco_res));
1473 res = &tco_res[ICH_RES_IO_TCO];
1474 res->start = tco_base & ~1;
1475 res->end = res->start + 32 - 1;
1476 res->flags = IORESOURCE_IO;
1479 * Power Management registers.
1481 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1482 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1484 res = &tco_res[ICH_RES_IO_SMI];
1485 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1486 res->end = res->start + 3;
1487 res->flags = IORESOURCE_IO;
1490 * Enable the ACPI I/O space.
1492 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1493 ctrl_val |= ACPICTRL_EN;
1494 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1497 * We must access the NO_REBOOT bit over the Primary to Sideband
1498 * bridge (P2SB). The BIOS prevents the P2SB device from being
1499 * enumerated by the PCI subsystem, so we need to unhide/hide it
1500 * to lookup the P2SB BAR.
1502 spin_lock(&p2sb_spinlock);
1504 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1506 /* Unhide the P2SB device, if it is hidden */
1507 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1509 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1511 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1512 base64_addr = base_addr & 0xfffffff0;
1514 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1515 base64_addr |= (u64)base_addr << 32;
1517 /* Hide the P2SB device, if it was hidden before */
1519 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1520 spin_unlock(&p2sb_spinlock);
1522 res = &tco_res[ICH_RES_MEM_OFF];
1523 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1524 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1526 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1528 res->end = res->start + 3;
1529 res->flags = IORESOURCE_MEM;
1531 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1532 tco_res, 3, &tco_platform_data,
1533 sizeof(tco_platform_data));
1535 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1539 priv->tco_pdev = pdev;
1543 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1544 acpi_physical_address address)
1546 return address >= priv->smba &&
1547 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1551 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1552 u64 *value, void *handler_context, void *region_context)
1554 struct i801_priv *priv = handler_context;
1555 struct pci_dev *pdev = priv->pci_dev;
1559 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1560 * further access from the driver itself. This device is now owned
1561 * by the system firmware.
1563 mutex_lock(&priv->acpi_lock);
1565 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1566 priv->acpi_reserved = true;
1568 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1569 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1572 * BIOS is accessing the host controller so prevent it from
1573 * suspending automatically from now on.
1575 pm_runtime_get_sync(&pdev->dev);
1578 if ((function & ACPI_IO_MASK) == ACPI_READ)
1579 status = acpi_os_read_port(address, (u32 *)value, bits);
1581 status = acpi_os_write_port(address, (u32)*value, bits);
1583 mutex_unlock(&priv->acpi_lock);
1588 static int i801_acpi_probe(struct i801_priv *priv)
1590 struct acpi_device *adev;
1593 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1595 status = acpi_install_address_space_handler(adev->handle,
1596 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1598 if (ACPI_SUCCESS(status))
1602 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1605 static void i801_acpi_remove(struct i801_priv *priv)
1607 struct acpi_device *adev;
1609 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1613 acpi_remove_address_space_handler(adev->handle,
1614 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1616 mutex_lock(&priv->acpi_lock);
1617 if (priv->acpi_reserved)
1618 pm_runtime_put(&priv->pci_dev->dev);
1619 mutex_unlock(&priv->acpi_lock);
1622 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1623 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1626 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1630 struct i801_priv *priv;
1632 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1636 i2c_set_adapdata(&priv->adapter, priv);
1637 priv->adapter.owner = THIS_MODULE;
1638 priv->adapter.class = i801_get_adapter_class(priv);
1639 priv->adapter.algo = &smbus_algorithm;
1640 priv->adapter.dev.parent = &dev->dev;
1641 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1642 priv->adapter.retries = 3;
1643 mutex_init(&priv->acpi_lock);
1645 priv->pci_dev = dev;
1646 switch (dev->device) {
1647 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1648 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1649 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1650 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1651 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1652 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1653 case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1654 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1655 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1656 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1657 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1658 priv->features |= FEATURE_I2C_BLOCK_READ;
1659 priv->features |= FEATURE_IRQ;
1660 priv->features |= FEATURE_SMBUS_PEC;
1661 priv->features |= FEATURE_BLOCK_BUFFER;
1662 /* If we have ACPI based watchdog use that instead */
1663 if (!acpi_has_watchdog())
1664 priv->features |= FEATURE_TCO;
1665 priv->features |= FEATURE_HOST_NOTIFY;
1668 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1669 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1670 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1671 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1672 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1673 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1674 priv->features |= FEATURE_IDF;
1677 priv->features |= FEATURE_I2C_BLOCK_READ;
1678 priv->features |= FEATURE_IRQ;
1680 case PCI_DEVICE_ID_INTEL_82801DB_3:
1681 priv->features |= FEATURE_SMBUS_PEC;
1682 priv->features |= FEATURE_BLOCK_BUFFER;
1684 case PCI_DEVICE_ID_INTEL_82801CA_3:
1685 priv->features |= FEATURE_HOST_NOTIFY;
1687 case PCI_DEVICE_ID_INTEL_82801BA_2:
1688 case PCI_DEVICE_ID_INTEL_82801AB_3:
1689 case PCI_DEVICE_ID_INTEL_82801AA_3:
1693 /* Disable features on user request */
1694 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1695 if (priv->features & disable_features & (1 << i))
1696 dev_notice(&dev->dev, "%s disabled by user\n",
1697 i801_feature_names[i]);
1699 priv->features &= ~disable_features;
1701 err = pcim_enable_device(dev);
1703 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1707 pcim_pin_device(dev);
1709 /* Determine the address of the SMBus area */
1710 priv->smba = pci_resource_start(dev, SMBBAR);
1713 "SMBus base address uninitialized, upgrade BIOS\n");
1717 if (i801_acpi_probe(priv))
1720 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1721 dev_driver_string(&dev->dev));
1724 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1726 (unsigned long long)pci_resource_end(dev, SMBBAR));
1727 i801_acpi_remove(priv);
1731 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1732 priv->original_hstcfg = temp;
1733 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1734 if (!(temp & SMBHSTCFG_HST_EN)) {
1735 dev_info(&dev->dev, "Enabling SMBus device\n");
1736 temp |= SMBHSTCFG_HST_EN;
1738 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1740 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1741 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1742 /* Disable SMBus interrupt feature if SMBus using SMI# */
1743 priv->features &= ~FEATURE_IRQ;
1745 if (temp & SMBHSTCFG_SPD_WD)
1746 dev_info(&dev->dev, "SPD Write Disable is set\n");
1748 /* Clear special mode bits */
1749 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1750 outb_p(inb_p(SMBAUXCTL(priv)) &
1751 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1753 /* Remember original Host Notify setting */
1754 if (priv->features & FEATURE_HOST_NOTIFY)
1755 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1757 /* Default timeout in interrupt mode: 200 ms */
1758 priv->adapter.timeout = HZ / 5;
1760 if (dev->irq == IRQ_NOTCONNECTED)
1761 priv->features &= ~FEATURE_IRQ;
1763 if (priv->features & FEATURE_IRQ) {
1766 /* Complain if an interrupt is already pending */
1767 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1768 if (pcists & SMBPCISTS_INTS)
1769 dev_warn(&dev->dev, "An interrupt is pending!\n");
1771 /* Check if interrupts have been disabled */
1772 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1773 if (pcictl & SMBPCICTL_INTDIS) {
1774 dev_info(&dev->dev, "Interrupts are disabled\n");
1775 priv->features &= ~FEATURE_IRQ;
1779 if (priv->features & FEATURE_IRQ) {
1780 init_waitqueue_head(&priv->waitq);
1782 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1784 dev_driver_string(&dev->dev), priv);
1786 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1788 priv->features &= ~FEATURE_IRQ;
1791 dev_info(&dev->dev, "SMBus using %s\n",
1792 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1796 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1797 "SMBus I801 adapter at %04lx", priv->smba);
1798 err = i2c_add_adapter(&priv->adapter);
1800 i801_acpi_remove(priv);
1804 i801_enable_host_notify(&priv->adapter);
1806 i801_probe_optional_slaves(priv);
1807 /* We ignore errors - multiplexing is optional */
1810 pci_set_drvdata(dev, priv);
1812 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1813 pm_runtime_use_autosuspend(&dev->dev);
1814 pm_runtime_put_autosuspend(&dev->dev);
1815 pm_runtime_allow(&dev->dev);
1820 static void i801_remove(struct pci_dev *dev)
1822 struct i801_priv *priv = pci_get_drvdata(dev);
1824 pm_runtime_forbid(&dev->dev);
1825 pm_runtime_get_noresume(&dev->dev);
1827 i801_disable_host_notify(priv);
1829 i2c_del_adapter(&priv->adapter);
1830 i801_acpi_remove(priv);
1831 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1833 platform_device_unregister(priv->tco_pdev);
1836 * do not call pci_disable_device(dev) since it can cause hard hangs on
1837 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1841 static void i801_shutdown(struct pci_dev *dev)
1843 struct i801_priv *priv = pci_get_drvdata(dev);
1845 /* Restore config registers to avoid hard hang on some systems */
1846 i801_disable_host_notify(priv);
1847 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1850 #ifdef CONFIG_PM_SLEEP
1851 static int i801_suspend(struct device *dev)
1853 struct pci_dev *pci_dev = to_pci_dev(dev);
1854 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1856 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1860 static int i801_resume(struct device *dev)
1862 struct pci_dev *pci_dev = to_pci_dev(dev);
1863 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1865 i801_enable_host_notify(&priv->adapter);
1871 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1873 static struct pci_driver i801_driver = {
1874 .name = "i801_smbus",
1875 .id_table = i801_ids,
1876 .probe = i801_probe,
1877 .remove = i801_remove,
1878 .shutdown = i801_shutdown,
1884 static int __init i2c_i801_init(void)
1886 if (dmi_name_in_vendors("FUJITSU"))
1887 input_apanel_init();
1888 return pci_register_driver(&i801_driver);
1891 static void __exit i2c_i801_exit(void)
1893 pci_unregister_driver(&i801_driver);
1896 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1897 MODULE_DESCRIPTION("I801 SMBus driver");
1898 MODULE_LICENSE("GPL");
1900 module_init(i2c_i801_init);
1901 module_exit(i2c_i801_exit);