drivers/i2c/busses/i2c-i801.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   4     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   5     <mdsxyz123@yahoo.com>
   6     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   7     Copyright (C) 2010         Intel Corporation,
   8                                David Woodhouse <dwmw2@infradead.org>
   9
  10 */
  11
  12 /*
  13  * Supports the following Intel I/O Controller Hubs (ICH):
  14  *
  15  *                                      I/O                     Block   I2C
  16  *                                      region  SMBus   Block   proc.   block
  17  * Chip name                    PCI ID  size    PEC     buffer  call    read
  18  * ---------------------------------------------------------------------------
  19  * 82801AA (ICH)                0x2413  16      no      no      no      no
  20  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  21  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  22  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  23  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  24  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  25  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  26  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  27  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  28  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  29  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  30  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  31  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  32  * ICH10                        0x3a30  32      hard    yes     yes     yes
  33  * ICH10                        0x3a60  32      hard    yes     yes     yes
  34  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  35  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  36  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  37  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  38  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  39  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  40  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  41  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  42  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  43  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  44  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  45  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  46  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  47  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  48  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  49  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  50  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  51  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  52  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  53  * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  54  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  55  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  56  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  57  * Emmitsburg (PCH)             0x1bc9  32      hard    yes     yes     yes
  58  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  59  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  60  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  61  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  62  * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  63  * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  64  * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  65  * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  66  * Ice Lake-LP (PCH)            0x34a3  32      hard    yes     yes     yes
  67  * Ice Lake-N (PCH)             0x38a3  32      hard    yes     yes     yes
  68  * Comet Lake (PCH)             0x02a3  32      hard    yes     yes     yes
  69  * Comet Lake-H (PCH)           0x06a3  32      hard    yes     yes     yes
  70  * Elkhart Lake (PCH)           0x4b23  32      hard    yes     yes     yes
  71  * Tiger Lake-LP (PCH)          0xa0a3  32      hard    yes     yes     yes
  72  * Tiger Lake-H (PCH)           0x43a3  32      hard    yes     yes     yes
  73  * Jasper Lake (SOC)            0x4da3  32      hard    yes     yes     yes
  74  * Comet Lake-V (PCH)           0xa3a3  32      hard    yes     yes     yes
  75  * Alder Lake-S (PCH)           0x7aa3  32      hard    yes     yes     yes
  76  * Alder Lake-P (PCH)           0x51a3  32      hard    yes     yes     yes
  77  * Alder Lake-M (PCH)           0x54a3  32      hard    yes     yes     yes
  78  *
  79  * Features supported by this driver:
  80  * Software PEC                         no
  81  * Hardware PEC                         yes
  82  * Block buffer                         yes
  83  * Block process call transaction       yes
  84  * I2C block read transaction           yes (doesn't use the block buffer)
  85  * Slave mode                           no
  86  * SMBus Host Notify                    yes
  87  * Interrupt processing                 yes
  88  *
  89  * See the file Documentation/i2c/busses/i2c-i801.rst for details.
  90  */
  91
  92 #define DRV_NAME        "i801_smbus"
  93
  94 #include <linux/interrupt.h>
  95 #include <linux/module.h>
  96 #include <linux/pci.h>
  97 #include <linux/kernel.h>
  98 #include <linux/stddef.h>
  99 #include <linux/delay.h>
 100 #include <linux/ioport.h>
 101 #include <linux/init.h>
 102 #include <linux/i2c.h>
 103 #include <linux/i2c-smbus.h>
 104 #include <linux/acpi.h>
 105 #include <linux/io.h>
 106 #include <linux/dmi.h>
 107 #include <linux/slab.h>
 108 #include <linux/string.h>
 109 #include <linux/completion.h>
 110 #include <linux/err.h>
 111 #include <linux/platform_device.h>
 112 #include <linux/platform_data/itco_wdt.h>
 113 #include <linux/pm_runtime.h>
 114 #include <linux/mutex.h>
 115
 116 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 117 #include <linux/gpio/machine.h>
 118 #include <linux/platform_data/i2c-mux-gpio.h>
 119 #endif
 120
 121 /* I801 SMBus address offsets */
 122 #define SMBHSTSTS(p)    (0 + (p)->smba)
 123 #define SMBHSTCNT(p)    (2 + (p)->smba)
 124 #define SMBHSTCMD(p)    (3 + (p)->smba)
 125 #define SMBHSTADD(p)    (4 + (p)->smba)
 126 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 127 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 128 #define SMBBLKDAT(p)    (7 + (p)->smba)
 129 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 130 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 131 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 132 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 133 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 134 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 135
 136 /* PCI Address Constants */
 137 #define SMBBAR          4
 138 #define SMBHSTCFG       0x040
 139 #define TCOBASE         0x050
 140 #define TCOCTL          0x054
 141
 142 #define SBREG_BAR               0x10
 143 #define SBREG_SMBCTRL           0xc6000c
 144 #define SBREG_SMBCTRL_DNV       0xcf000c
 145
 146 /* Host configuration bits for SMBHSTCFG */
 147 #define SMBHSTCFG_HST_EN        BIT(0)
 148 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 149 #define SMBHSTCFG_I2C_EN        BIT(2)
 150 #define SMBHSTCFG_SPD_WD        BIT(4)
 151
 152 /* TCO configuration bits for TCOCTL */
 153 #define TCOCTL_EN               BIT(8)
 154
 155 /* Auxiliary status register bits, ICH4+ only */
 156 #define SMBAUXSTS_CRCE          BIT(0)
 157 #define SMBAUXSTS_STCO          BIT(1)
 158
 159 /* Auxiliary control register bits, ICH4+ only */
 160 #define SMBAUXCTL_CRC           BIT(0)
 161 #define SMBAUXCTL_E32B          BIT(1)
 162
 163 /* I801 command constants */
 164 #define I801_QUICK              0x00
 165 #define I801_BYTE               0x04
 166 #define I801_BYTE_DATA          0x08
 167 #define I801_WORD_DATA          0x0C
 168 #define I801_PROC_CALL          0x10    /* unimplemented */
 169 #define I801_BLOCK_DATA         0x14
 170 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 171 #define I801_BLOCK_PROC_CALL    0x1C
 172
 173 /* I801 Host Control register bits */
 174 #define SMBHSTCNT_INTREN        BIT(0)
 175 #define SMBHSTCNT_KILL          BIT(1)
 176 #define SMBHSTCNT_LAST_BYTE     BIT(5)
 177 #define SMBHSTCNT_START         BIT(6)
 178 #define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 179
 180 /* I801 Hosts Status register bits */
 181 #define SMBHSTSTS_BYTE_DONE     BIT(7)
 182 #define SMBHSTSTS_INUSE_STS     BIT(6)
 183 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
 184 #define SMBHSTSTS_FAILED        BIT(4)
 185 #define SMBHSTSTS_BUS_ERR       BIT(3)
 186 #define SMBHSTSTS_DEV_ERR       BIT(2)
 187 #define SMBHSTSTS_INTR          BIT(1)
 188 #define SMBHSTSTS_HOST_BUSY     BIT(0)
 189
 190 /* Host Notify Status register bits */
 191 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 192
 193 /* Host Notify Command register bits */
 194 #define SMBSLVCMD_SMBALERT_DISABLE      BIT(2)
 195 #define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 196
 197 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 198                                  SMBHSTSTS_DEV_ERR)
 199
 200 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 201                                  STATUS_ERROR_FLAGS)
 202
 203 /* Older devices have their ID defined in <linux/pci_ids.h> */
 204 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS             0x02a3
 205 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS           0x06a3
 206 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 207 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 208 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 209 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS                   0x1bc9
 210 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 212 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 216 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 217 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 218 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 219 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 220 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 221 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 222 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS            0x34a3
 223 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS             0x38a3
 224 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 225 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS           0x43a3
 226 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS          0x4b23
 227 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS           0x4da3
 228 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS          0x51a3
 229 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS          0x54a3
 230 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 231 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS          0x7aa3
 232 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 233 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 234 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 235 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 236 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 237 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 238 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 239 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 240 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 241 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 242 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS          0xa0a3
 243 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 244 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 245 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 246 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 247 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 248 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS           0xa3a3
 249
 250 struct i801_mux_config {
 251         char *gpio_chip;
 252         unsigned values[3];
 253         int n_values;
 254         unsigned classes[3];
 255         unsigned gpios[2];              /* Relative to gpio_chip->base */
 256         int n_gpios;
 257 };
 258
 259 struct i801_priv {
 260         struct i2c_adapter adapter;
 261         unsigned long smba;
 262         unsigned char original_hstcfg;
 263         unsigned char original_hstcnt;
 264         unsigned char original_slvcmd;
 265         struct pci_dev *pci_dev;
 266         unsigned int features;
 267
 268         /* isr processing */
 269         struct completion done;
 270         u8 status;
 271
 272         /* Command state used by isr for byte-by-byte block transactions */
 273         u8 cmd;
 274         bool is_read;
 275         int count;
 276         int len;
 277         u8 *data;
 278
 279 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 280         const struct i801_mux_config *mux_drvdata;
 281         struct platform_device *mux_pdev;
 282         struct gpiod_lookup_table *lookup;
 283 #endif
 284         struct platform_device *tco_pdev;
 285
 286         /*
 287          * If set to true the host controller registers are reserved for
 288          * ACPI AML use. Protected by acpi_lock.
 289          */
 290         bool acpi_reserved;
 291         struct mutex acpi_lock;
 292 };
 293
 294 #define FEATURE_SMBUS_PEC       BIT(0)
 295 #define FEATURE_BLOCK_BUFFER    BIT(1)
 296 #define FEATURE_BLOCK_PROC      BIT(2)
 297 #define FEATURE_I2C_BLOCK_READ  BIT(3)
 298 #define FEATURE_IRQ             BIT(4)
 299 #define FEATURE_HOST_NOTIFY     BIT(5)
 300 /* Not really a feature, but it's convenient to handle it as such */
 301 #define FEATURE_IDF             BIT(15)
 302 #define FEATURE_TCO_SPT         BIT(16)
 303 #define FEATURE_TCO_CNL         BIT(17)
 304
 305 static const char *i801_feature_names[] = {
 306         "SMBus PEC",
 307         "Block buffer",
 308         "Block process call",
 309         "I2C block read",
 310         "Interrupt",
 311         "SMBus Host Notify",
 312 };
 313
 314 static unsigned int disable_features;
 315 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 316 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 317         "\t\t  0x01  disable SMBus PEC\n"
 318         "\t\t  0x02  disable the block buffer\n"
 319         "\t\t  0x08  disable the I2C block read functionality\n"
 320         "\t\t  0x10  don't use interrupts\n"
 321         "\t\t  0x20  disable SMBus Host Notify ");
 322
 323 /* Make sure the SMBus host is ready to start transmitting.
 324    Return 0 if it is, -EBUSY if it is not. */
 325 static int i801_check_pre(struct i801_priv *priv)
 326 {
 327         int status;
 328
 329         status = inb_p(SMBHSTSTS(priv));
 330         if (status & SMBHSTSTS_HOST_BUSY) {
 331                 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n");
 332                 return -EBUSY;
 333         }
 334
 335         status &= STATUS_FLAGS;
 336         if (status) {
 337                 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status);
 338                 outb_p(status, SMBHSTSTS(priv));
 339         }
 340
 341         /*
 342          * Clear CRC status if needed.
 343          * During normal operation, i801_check_post() takes care
 344          * of it after every operation.  We do it here only in case
 345          * the hardware was already in this state when the driver
 346          * started.
 347          */
 348         if (priv->features & FEATURE_SMBUS_PEC) {
 349                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 350                 if (status) {
 351                         pci_dbg(priv->pci_dev, "Clearing aux status flags (%02x)\n", status);
 352                         outb_p(status, SMBAUXSTS(priv));
 353                 }
 354         }
 355
 356         return 0;
 357 }
 358
 359 /*
 360  * Convert the status register to an error code, and clear it.
 361  * Note that status only contains the bits we want to clear, not the
 362  * actual register value.
 363  */
 364 static int i801_check_post(struct i801_priv *priv, int status)
 365 {
 366         int result = 0;
 367
 368         /*
 369          * If the SMBus is still busy, we give up
 370          * Note: This timeout condition only happens when using polling
 371          * transactions.  For interrupt operation, NAK/timeout is indicated by
 372          * DEV_ERR.
 373          */
 374         if (unlikely(status < 0)) {
 375                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 376                 /* try to stop the current command */
 377                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 378                 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
 379                 usleep_range(1000, 2000);
 380                 outb_p(0, SMBHSTCNT(priv));
 381
 382                 /* Check if it worked */
 383                 status = inb_p(SMBHSTSTS(priv));
 384                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 385                     !(status & SMBHSTSTS_FAILED))
 386                         dev_err(&priv->pci_dev->dev,
 387                                 "Failed terminating the transaction\n");
 388                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 389                 return -ETIMEDOUT;
 390         }
 391
 392         if (status & SMBHSTSTS_FAILED) {
 393                 result = -EIO;
 394                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 395         }
 396         if (status & SMBHSTSTS_DEV_ERR) {
 397                 /*
 398                  * This may be a PEC error, check and clear it.
 399                  *
 400                  * AUXSTS is handled differently from HSTSTS.
 401                  * For HSTSTS, i801_isr() or i801_wait_intr()
 402                  * has already cleared the error bits in hardware,
 403                  * and we are passed a copy of the original value
 404                  * in "status".
 405                  * For AUXSTS, the hardware register is left
 406                  * for us to handle here.
 407                  * This is asymmetric, slightly iffy, but safe,
 408                  * since all this code is serialized and the CRCE
 409                  * bit is harmless as long as it's cleared before
 410                  * the next operation.
 411                  */
 412                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 413                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 414                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 415                         result = -EBADMSG;
 416                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 417                 } else {
 418                         result = -ENXIO;
 419                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 420                 }
 421         }
 422         if (status & SMBHSTSTS_BUS_ERR) {
 423                 result = -EAGAIN;
 424                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 425         }
 426
 427         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 428         outb_p(status, SMBHSTSTS(priv));
 429
 430         return result;
 431 }
 432
 433 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 434 static int i801_wait_intr(struct i801_priv *priv)
 435 {
 436         unsigned long timeout = jiffies + priv->adapter.timeout;
 437         int status, busy;
 438
 439         do {
 440                 usleep_range(250, 500);
 441                 status = inb_p(SMBHSTSTS(priv));
 442                 busy = status & SMBHSTSTS_HOST_BUSY;
 443                 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
 444                 if (!busy && status)
 445                         return status;
 446         } while (time_is_after_eq_jiffies(timeout));
 447
 448         return -ETIMEDOUT;
 449 }
 450
 451 /* Wait for either BYTE_DONE or an error flag being set */
 452 static int i801_wait_byte_done(struct i801_priv *priv)
 453 {
 454         unsigned long timeout = jiffies + priv->adapter.timeout;
 455         int status;
 456
 457         do {
 458                 usleep_range(250, 500);
 459                 status = inb_p(SMBHSTSTS(priv));
 460                 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
 461                         return status & STATUS_ERROR_FLAGS;
 462         } while (time_is_after_eq_jiffies(timeout));
 463
 464         return -ETIMEDOUT;
 465 }
 466
 467 static int i801_transaction(struct i801_priv *priv, int xact)
 468 {
 469         int status;
 470         unsigned long result;
 471         const struct i2c_adapter *adap = &priv->adapter;
 472
 473         status = i801_check_pre(priv);
 474         if (status < 0)
 475                 return status;
 476
 477         if (priv->features & FEATURE_IRQ) {
 478                 reinit_completion(&priv->done);
 479                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 480                        SMBHSTCNT(priv));
 481                 result = wait_for_completion_timeout(&priv->done, adap->timeout);
 482                 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
 483         }
 484
 485         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 486          * SMBSCMD are passed in xact */
 487         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 488
 489         status = i801_wait_intr(priv);
 490         return i801_check_post(priv, status);
 491 }
 492
 493 static int i801_block_transaction_by_block(struct i801_priv *priv,
 494                                            union i2c_smbus_data *data,
 495                                            char read_write, int command)
 496 {
 497         int i, len, status, xact;
 498
 499         switch (command) {
 500         case I2C_SMBUS_BLOCK_PROC_CALL:
 501                 xact = I801_BLOCK_PROC_CALL;
 502                 break;
 503         case I2C_SMBUS_BLOCK_DATA:
 504                 xact = I801_BLOCK_DATA;
 505                 break;
 506         default:
 507                 return -EOPNOTSUPP;
 508         }
 509
 510         /* Set block buffer mode */
 511         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 512
 513         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 514
 515         if (read_write == I2C_SMBUS_WRITE) {
 516                 len = data->block[0];
 517                 outb_p(len, SMBHSTDAT0(priv));
 518                 for (i = 0; i < len; i++)
 519                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 520         }
 521
 522         status = i801_transaction(priv, xact);
 523         if (status)
 524                 return status;
 525
 526         if (read_write == I2C_SMBUS_READ ||
 527             command == I2C_SMBUS_BLOCK_PROC_CALL) {
 528                 len = inb_p(SMBHSTDAT0(priv));
 529                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 530                         return -EPROTO;
 531
 532                 data->block[0] = len;
 533                 for (i = 0; i < len; i++)
 534                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 535         }
 536         return 0;
 537 }
 538
 539 static void i801_isr_byte_done(struct i801_priv *priv)
 540 {
 541         if (priv->is_read) {
 542                 /* For SMBus block reads, length is received with first byte */
 543                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 544                     (priv->count == 0)) {
 545                         priv->len = inb_p(SMBHSTDAT0(priv));
 546                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 547                                 dev_err(&priv->pci_dev->dev,
 548                                         "Illegal SMBus block read size %d\n",
 549                                         priv->len);
 550                                 /* FIXME: Recover */
 551                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 552                         }
 553                         priv->data[-1] = priv->len;
 554                 }
 555
 556                 /* Read next byte */
 557                 if (priv->count < priv->len)
 558                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 559                 else
 560                         dev_dbg(&priv->pci_dev->dev,
 561                                 "Discarding extra byte on block read\n");
 562
 563                 /* Set LAST_BYTE for last byte of read transaction */
 564                 if (priv->count == priv->len - 1)
 565                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 566                                SMBHSTCNT(priv));
 567         } else if (priv->count < priv->len - 1) {
 568                 /* Write next byte, except for IRQ after last byte */
 569                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 570         }
 571
 572         /* Clear BYTE_DONE to continue with next byte */
 573         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 574 }
 575
 576 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 577 {
 578         unsigned short addr;
 579
 580         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 581
 582         /*
 583          * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 584          * always returns 0. Our current implementation doesn't provide
 585          * data, so we just ignore it.
 586          */
 587         i2c_handle_smbus_host_notify(&priv->adapter, addr);
 588
 589         /* clear Host Notify bit and return */
 590         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 591         return IRQ_HANDLED;
 592 }
 593
 594 /*
 595  * There are three kinds of interrupts:
 596  *
 597  * 1) i801 signals transaction completion with one of these interrupts:
 598  *      INTR - Success
 599  *      DEV_ERR - Invalid command, NAK or communication timeout
 600  *      BUS_ERR - SMI# transaction collision
 601  *      FAILED - transaction was canceled due to a KILL request
 602  *    When any of these occur, update ->status and signal completion.
 603  *    ->status must be cleared before kicking off the next transaction.
 604  *
 605  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 606  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 607  *
 608  * 3) Host Notify interrupts
 609  */
 610 static irqreturn_t i801_isr(int irq, void *dev_id)
 611 {
 612         struct i801_priv *priv = dev_id;
 613         u16 pcists;
 614         u8 status;
 615
 616         /* Confirm this is our interrupt */
 617         pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
 618         if (!(pcists & PCI_STATUS_INTERRUPT))
 619                 return IRQ_NONE;
 620
 621         if (priv->features & FEATURE_HOST_NOTIFY) {
 622                 status = inb_p(SMBSLVSTS(priv));
 623                 if (status & SMBSLVSTS_HST_NTFY_STS)
 624                         return i801_host_notify_isr(priv);
 625         }
 626
 627         status = inb_p(SMBHSTSTS(priv));
 628         if (status & SMBHSTSTS_BYTE_DONE)
 629                 i801_isr_byte_done(priv);
 630
 631         /*
 632          * Clear remaining IRQ sources: Completion of last command, errors
 633          * and the SMB_ALERT signal. SMB_ALERT status is set after signal
 634          * assertion independently of the interrupt generation being blocked
 635          * or not so clear it always when the status is set.
 636          */
 637         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS | SMBHSTSTS_SMBALERT_STS;
 638         if (status)
 639                 outb_p(status, SMBHSTSTS(priv));
 640         status &= ~SMBHSTSTS_SMBALERT_STS; /* SMB_ALERT not reported */
 641         /*
 642          * Report transaction result.
 643          * ->status must be cleared before the next transaction is started.
 644          */
 645         if (status) {
 646                 priv->status = status;
 647                 complete(&priv->done);
 648         }
 649
 650         return IRQ_HANDLED;
 651 }
 652
 653 /*
 654  * For "byte-by-byte" block transactions:
 655  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 656  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 657  */
 658 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 659                                                union i2c_smbus_data *data,
 660                                                char read_write, int command)
 661 {
 662         int i, len;
 663         int smbcmd;
 664         int status;
 665         unsigned long result;
 666         const struct i2c_adapter *adap = &priv->adapter;
 667
 668         if (command == I2C_SMBUS_BLOCK_PROC_CALL)
 669                 return -EOPNOTSUPP;
 670
 671         status = i801_check_pre(priv);
 672         if (status < 0)
 673                 return status;
 674
 675         len = data->block[0];
 676
 677         if (read_write == I2C_SMBUS_WRITE) {
 678                 outb_p(len, SMBHSTDAT0(priv));
 679                 outb_p(data->block[1], SMBBLKDAT(priv));
 680         }
 681
 682         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 683             read_write == I2C_SMBUS_READ)
 684                 smbcmd = I801_I2C_BLOCK_DATA;
 685         else
 686                 smbcmd = I801_BLOCK_DATA;
 687
 688         if (priv->features & FEATURE_IRQ) {
 689                 priv->is_read = (read_write == I2C_SMBUS_READ);
 690                 if (len == 1 && priv->is_read)
 691                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 692                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 693                 priv->len = len;
 694                 priv->count = 0;
 695                 priv->data = &data->block[1];
 696
 697                 reinit_completion(&priv->done);
 698                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 699                 result = wait_for_completion_timeout(&priv->done, adap->timeout);
 700                 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
 701         }
 702
 703         for (i = 1; i <= len; i++) {
 704                 if (i == len && read_write == I2C_SMBUS_READ)
 705                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 706                 outb_p(smbcmd, SMBHSTCNT(priv));
 707
 708                 if (i == 1)
 709                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 710                                SMBHSTCNT(priv));
 711
 712                 status = i801_wait_byte_done(priv);
 713                 if (status)
 714                         goto exit;
 715
 716                 if (i == 1 && read_write == I2C_SMBUS_READ
 717                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 718                         len = inb_p(SMBHSTDAT0(priv));
 719                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 720                                 dev_err(&priv->pci_dev->dev,
 721                                         "Illegal SMBus block read size %d\n",
 722                                         len);
 723                                 /* Recover */
 724                                 while (inb_p(SMBHSTSTS(priv)) &
 725                                        SMBHSTSTS_HOST_BUSY)
 726                                         outb_p(SMBHSTSTS_BYTE_DONE,
 727                                                SMBHSTSTS(priv));
 728                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 729                                 return -EPROTO;
 730                         }
 731                         data->block[0] = len;
 732                 }
 733
 734                 /* Retrieve/store value in SMBBLKDAT */
 735                 if (read_write == I2C_SMBUS_READ)
 736                         data->block[i] = inb_p(SMBBLKDAT(priv));
 737                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 738                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 739
 740                 /* signals SMBBLKDAT ready */
 741                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 742         }
 743
 744         status = i801_wait_intr(priv);
 745 exit:
 746         return i801_check_post(priv, status);
 747 }
 748
 749 /* Block transaction function */
 750 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
 751                                   char read_write, int command)
 752 {
 753         int result = 0;
 754         unsigned char hostc;
 755
 756         if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
 757                 data->block[0] = I2C_SMBUS_BLOCK_MAX;
 758         else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 759                 return -EPROTO;
 760
 761         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 762                 if (read_write == I2C_SMBUS_WRITE) {
 763                         /* set I2C_EN bit in configuration register */
 764                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 765                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 766                                               hostc | SMBHSTCFG_I2C_EN);
 767                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 768                         dev_err(&priv->pci_dev->dev,
 769                                 "I2C block read is unsupported!\n");
 770                         return -EOPNOTSUPP;
 771                 }
 772         }
 773
 774         /* Experience has shown that the block buffer can only be used for
 775            SMBus (not I2C) block transactions, even though the datasheet
 776            doesn't mention this limitation. */
 777         if ((priv->features & FEATURE_BLOCK_BUFFER) &&
 778             command != I2C_SMBUS_I2C_BLOCK_DATA)
 779                 result = i801_block_transaction_by_block(priv, data,
 780                                                          read_write,
 781                                                          command);
 782         else
 783                 result = i801_block_transaction_byte_by_byte(priv, data,
 784                                                              read_write,
 785                                                              command);
 786
 787         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 788          && read_write == I2C_SMBUS_WRITE) {
 789                 /* restore saved configuration register value */
 790                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 791         }
 792         return result;
 793 }
 794
 795 /* Return negative errno on error. */
 796 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 797                        unsigned short flags, char read_write, u8 command,
 798                        int size, union i2c_smbus_data *data)
 799 {
 800         int hwpec;
 801         int block = 0;
 802         int ret = 0, xact = 0;
 803         struct i801_priv *priv = i2c_get_adapdata(adap);
 804
 805         mutex_lock(&priv->acpi_lock);
 806         if (priv->acpi_reserved) {
 807                 mutex_unlock(&priv->acpi_lock);
 808                 return -EBUSY;
 809         }
 810
 811         pm_runtime_get_sync(&priv->pci_dev->dev);
 812
 813         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 814                 && size != I2C_SMBUS_QUICK
 815                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 816
 817         switch (size) {
 818         case I2C_SMBUS_QUICK:
 819                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 820                        SMBHSTADD(priv));
 821                 xact = I801_QUICK;
 822                 break;
 823         case I2C_SMBUS_BYTE:
 824                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 825                        SMBHSTADD(priv));
 826                 if (read_write == I2C_SMBUS_WRITE)
 827                         outb_p(command, SMBHSTCMD(priv));
 828                 xact = I801_BYTE;
 829                 break;
 830         case I2C_SMBUS_BYTE_DATA:
 831                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 832                        SMBHSTADD(priv));
 833                 outb_p(command, SMBHSTCMD(priv));
 834                 if (read_write == I2C_SMBUS_WRITE)
 835                         outb_p(data->byte, SMBHSTDAT0(priv));
 836                 xact = I801_BYTE_DATA;
 837                 break;
 838         case I2C_SMBUS_WORD_DATA:
 839                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 840                        SMBHSTADD(priv));
 841                 outb_p(command, SMBHSTCMD(priv));
 842                 if (read_write == I2C_SMBUS_WRITE) {
 843                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 844                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 845                 }
 846                 xact = I801_WORD_DATA;
 847                 break;
 848         case I2C_SMBUS_BLOCK_DATA:
 849                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 850                        SMBHSTADD(priv));
 851                 outb_p(command, SMBHSTCMD(priv));
 852                 block = 1;
 853                 break;
 854         case I2C_SMBUS_I2C_BLOCK_DATA:
 855                 /*
 856                  * NB: page 240 of ICH5 datasheet shows that the R/#W
 857                  * bit should be cleared here, even when reading.
 858                  * However if SPD Write Disable is set (Lynx Point and later),
 859                  * the read will fail if we don't set the R/#W bit.
 860                  */
 861                 outb_p(((addr & 0x7f) << 1) |
 862                        ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
 863                         (read_write & 0x01) : 0),
 864                        SMBHSTADD(priv));
 865                 if (read_write == I2C_SMBUS_READ) {
 866                         /* NB: page 240 of ICH5 datasheet also shows
 867                          * that DATA1 is the cmd field when reading */
 868                         outb_p(command, SMBHSTDAT1(priv));
 869                 } else
 870                         outb_p(command, SMBHSTCMD(priv));
 871                 block = 1;
 872                 break;
 873         case I2C_SMBUS_BLOCK_PROC_CALL:
 874                 /*
 875                  * Bit 0 of the slave address register always indicate a write
 876                  * command.
 877                  */
 878                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 879                 outb_p(command, SMBHSTCMD(priv));
 880                 block = 1;
 881                 break;
 882         default:
 883                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 884                         size);
 885                 ret = -EOPNOTSUPP;
 886                 goto out;
 887         }
 888
 889         if (hwpec)      /* enable/disable hardware PEC */
 890                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 891         else
 892                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 893                        SMBAUXCTL(priv));
 894
 895         if (block)
 896                 ret = i801_block_transaction(priv, data, read_write, size);
 897         else
 898                 ret = i801_transaction(priv, xact);
 899
 900         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 901            time, so we forcibly disable it after every transaction. Turn off
 902            E32B for the same reason. */
 903         if (hwpec || block)
 904                 outb_p(inb_p(SMBAUXCTL(priv)) &
 905                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 906
 907         if (block)
 908                 goto out;
 909         if (ret)
 910                 goto out;
 911         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 912                 goto out;
 913
 914         switch (xact & 0x7f) {
 915         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 916         case I801_BYTE_DATA:
 917                 data->byte = inb_p(SMBHSTDAT0(priv));
 918                 break;
 919         case I801_WORD_DATA:
 920                 data->word = inb_p(SMBHSTDAT0(priv)) +
 921                              (inb_p(SMBHSTDAT1(priv)) << 8);
 922                 break;
 923         }
 924
 925 out:
 926         /* Unlock the SMBus device for use by BIOS/ACPI */
 927         outb_p(SMBHSTSTS_INUSE_STS, SMBHSTSTS(priv));
 928
 929         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 930         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 931         mutex_unlock(&priv->acpi_lock);
 932         return ret;
 933 }
 934
 935
 936 static u32 i801_func(struct i2c_adapter *adapter)
 937 {
 938         struct i801_priv *priv = i2c_get_adapdata(adapter);
 939
 940         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 941                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 942                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 943                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 944                ((priv->features & FEATURE_BLOCK_PROC) ?
 945                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
 946                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 947                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 948                ((priv->features & FEATURE_HOST_NOTIFY) ?
 949                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 950 }
 951
 952 static void i801_enable_host_notify(struct i2c_adapter *adapter)
 953 {
 954         struct i801_priv *priv = i2c_get_adapdata(adapter);
 955
 956         if (!(priv->features & FEATURE_HOST_NOTIFY))
 957                 return;
 958
 959         /*
 960          * Enable host notify interrupt and block the generation of interrupt
 961          * from the SMB_ALERT signal because the driver does not support
 962          * SMBus Alert.
 963          */
 964         outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE |
 965                priv->original_slvcmd, SMBSLVCMD(priv));
 966
 967         /* clear Host Notify bit to allow a new notification */
 968         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 969 }
 970
 971 static void i801_disable_host_notify(struct i801_priv *priv)
 972 {
 973         if (!(priv->features & FEATURE_HOST_NOTIFY))
 974                 return;
 975
 976         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
 977 }
 978
 979 static const struct i2c_algorithm smbus_algorithm = {
 980         .smbus_xfer     = i801_access,
 981         .functionality  = i801_func,
 982 };
 983
 984 #define FEATURES_ICH5   (FEATURE_BLOCK_PROC | FEATURE_I2C_BLOCK_READ    | \
 985                          FEATURE_IRQ | FEATURE_SMBUS_PEC                | \
 986                          FEATURE_BLOCK_BUFFER | FEATURE_HOST_NOTIFY)
 987 #define FEATURES_ICH4   (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \
 988                          FEATURE_HOST_NOTIFY)
 989
 990 static const struct pci_device_id i801_ids[] = {
 991         { PCI_DEVICE_DATA(INTEL, 82801AA_3,             0)                               },
 992         { PCI_DEVICE_DATA(INTEL, 82801AB_3,             0)                               },
 993         { PCI_DEVICE_DATA(INTEL, 82801BA_2,             0)                               },
 994         { PCI_DEVICE_DATA(INTEL, 82801CA_3,             FEATURE_HOST_NOTIFY)             },
 995         { PCI_DEVICE_DATA(INTEL, 82801DB_3,             FEATURES_ICH4)                   },
 996         { PCI_DEVICE_DATA(INTEL, 82801EB_3,             FEATURES_ICH5)                   },
 997         { PCI_DEVICE_DATA(INTEL, ESB_4,                 FEATURES_ICH5)                   },
 998         { PCI_DEVICE_DATA(INTEL, ICH6_16,               FEATURES_ICH5)                   },
 999         { PCI_DEVICE_DATA(INTEL, ICH7_17,               FEATURES_ICH5)                   },
1000         { PCI_DEVICE_DATA(INTEL, ESB2_17,               FEATURES_ICH5)                   },
1001         { PCI_DEVICE_DATA(INTEL, ICH8_5,                FEATURES_ICH5)                   },
1002         { PCI_DEVICE_DATA(INTEL, ICH9_6,                FEATURES_ICH5)                   },
1003         { PCI_DEVICE_DATA(INTEL, EP80579_1,             FEATURES_ICH5)                   },
1004         { PCI_DEVICE_DATA(INTEL, ICH10_4,               FEATURES_ICH5)                   },
1005         { PCI_DEVICE_DATA(INTEL, ICH10_5,               FEATURES_ICH5)                   },
1006         { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS,   FEATURES_ICH5)                   },
1007         { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS,     FEATURES_ICH5)                   },
1008         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS,        FEATURES_ICH5)                   },
1009         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0,   FEATURES_ICH5 | FEATURE_IDF)     },
1010         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1,   FEATURES_ICH5 | FEATURE_IDF)     },
1011         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2,   FEATURES_ICH5 | FEATURE_IDF)     },
1012         { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS,        FEATURES_ICH5)                   },
1013         { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS,    FEATURES_ICH5)                   },
1014         { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS,       FEATURES_ICH5)                   },
1015         { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS,    FEATURES_ICH5)                   },
1016         { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS,          FEATURES_ICH5)                   },
1017         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS,       FEATURES_ICH5)                   },
1018         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0,   FEATURES_ICH5 | FEATURE_IDF)     },
1019         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1,   FEATURES_ICH5 | FEATURE_IDF)     },
1020         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2,   FEATURES_ICH5 | FEATURE_IDF)     },
1021         { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS,     FEATURES_ICH5)                   },
1022         { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS,      FEATURES_ICH5)                   },
1023         { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS,    FEATURES_ICH5)                   },
1024         { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5)                   },
1025         { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS,        FEATURES_ICH5)                   },
1026         { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS,        FEATURES_ICH5)                   },
1027         { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1028         { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1029         { PCI_DEVICE_DATA(INTEL, CDF_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_CNL) },
1030         { PCI_DEVICE_DATA(INTEL, DNV_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_SPT) },
1031         { PCI_DEVICE_DATA(INTEL, EBG_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_CNL) },
1032         { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS,         FEATURES_ICH5)                   },
1033         { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_SPT) },
1034         { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1035         { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1036         { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1037         { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_CNL) },
1038         { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS,      FEATURES_ICH5 | FEATURE_TCO_CNL) },
1039         { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_CNL) },
1040         { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_CNL) },
1041         { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1042         { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_SPT) },
1043         { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1044         { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1045         { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1046         { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1047         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1048         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1049         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1050         { 0, }
1051 };
1052
1053 MODULE_DEVICE_TABLE(pci, i801_ids);
1054
1055 #if defined CONFIG_X86 && defined CONFIG_DMI
1056 static unsigned char apanel_addr;
1057
1058 /* Scan the system ROM for the signature "FJKEYINF" */
1059 static __init const void __iomem *bios_signature(const void __iomem *bios)
1060 {
1061         ssize_t offset;
1062         const unsigned char signature[] = "FJKEYINF";
1063
1064         for (offset = 0; offset < 0x10000; offset += 0x10) {
1065                 if (check_signature(bios + offset, signature,
1066                                     sizeof(signature)-1))
1067                         return bios + offset;
1068         }
1069         return NULL;
1070 }
1071
1072 static void __init input_apanel_init(void)
1073 {
1074         void __iomem *bios;
1075         const void __iomem *p;
1076
1077         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1078         p = bios_signature(bios);
1079         if (p) {
1080                 /* just use the first address */
1081                 apanel_addr = readb(p + 8 + 3) >> 1;
1082         }
1083         iounmap(bios);
1084 }
1085
1086 struct dmi_onboard_device_info {
1087         const char *name;
1088         u8 type;
1089         unsigned short i2c_addr;
1090         const char *i2c_type;
1091 };
1092
1093 static const struct dmi_onboard_device_info dmi_devices[] = {
1094         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1095         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1096         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1097 };
1098
1099 static void dmi_check_onboard_device(u8 type, const char *name,
1100                                      struct i2c_adapter *adap)
1101 {
1102         int i;
1103         struct i2c_board_info info;
1104
1105         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1106                 /* & ~0x80, ignore enabled/disabled bit */
1107                 if ((type & ~0x80) != dmi_devices[i].type)
1108                         continue;
1109                 if (strcasecmp(name, dmi_devices[i].name))
1110                         continue;
1111
1112                 memset(&info, 0, sizeof(struct i2c_board_info));
1113                 info.addr = dmi_devices[i].i2c_addr;
1114                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1115                 i2c_new_client_device(adap, &info);
1116                 break;
1117         }
1118 }
1119
1120 /* We use our own function to check for onboard devices instead of
1121    dmi_find_device() as some buggy BIOS's have the devices we are interested
1122    in marked as disabled */
1123 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1124 {
1125         int i, count;
1126
1127         if (dm->type != 10)
1128                 return;
1129
1130         count = (dm->length - sizeof(struct dmi_header)) / 2;
1131         for (i = 0; i < count; i++) {
1132                 const u8 *d = (char *)(dm + 1) + (i * 2);
1133                 const char *name = ((char *) dm) + dm->length;
1134                 u8 type = d[0];
1135                 u8 s = d[1];
1136
1137                 if (!s)
1138                         continue;
1139                 s--;
1140                 while (s > 0 && name[0]) {
1141                         name += strlen(name) + 1;
1142                         s--;
1143                 }
1144                 if (name[0] == 0) /* Bogus string reference */
1145                         continue;
1146
1147                 dmi_check_onboard_device(type, name, adap);
1148         }
1149 }
1150
1151 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1152 static const char *const acpi_smo8800_ids[] = {
1153         "SMO8800",
1154         "SMO8801",
1155         "SMO8810",
1156         "SMO8811",
1157         "SMO8820",
1158         "SMO8821",
1159         "SMO8830",
1160         "SMO8831",
1161 };
1162
1163 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1164                                              u32 nesting_level,
1165                                              void *context,
1166                                              void **return_value)
1167 {
1168         struct acpi_device_info *info;
1169         acpi_status status;
1170         char *hid;
1171         int i;
1172
1173         status = acpi_get_object_info(obj_handle, &info);
1174         if (ACPI_FAILURE(status))
1175                 return AE_OK;
1176
1177         if (!(info->valid & ACPI_VALID_HID))
1178                 goto smo88xx_not_found;
1179
1180         hid = info->hardware_id.string;
1181         if (!hid)
1182                 goto smo88xx_not_found;
1183
1184         i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1185         if (i < 0)
1186                 goto smo88xx_not_found;
1187
1188         kfree(info);
1189
1190         *return_value = NULL;
1191         return AE_CTRL_TERMINATE;
1192
1193 smo88xx_not_found:
1194         kfree(info);
1195         return AE_OK;
1196 }
1197
1198 static bool is_dell_system_with_lis3lv02d(void)
1199 {
1200         void *err = ERR_PTR(-ENOENT);
1201
1202         if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc."))
1203                 return false;
1204
1205         /*
1206          * Check that ACPI device SMO88xx is present and is functioning.
1207          * Function acpi_get_devices() already filters all ACPI devices
1208          * which are not present or are not functioning.
1209          * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1210          * accelerometer but unfortunately ACPI does not provide any other
1211          * information (like I2C address).
1212          */
1213         acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err);
1214
1215         return !IS_ERR(err);
1216 }
1217
1218 /*
1219  * Accelerometer's I2C address is not specified in DMI nor ACPI,
1220  * so it is needed to define mapping table based on DMI product names.
1221  */
1222 static const struct {
1223         const char *dmi_product_name;
1224         unsigned short i2c_addr;
1225 } dell_lis3lv02d_devices[] = {
1226         /*
1227          * Dell platform team told us that these Latitude devices have
1228          * ST microelectronics accelerometer at I2C address 0x29.
1229          */
1230         { "Latitude E5250",     0x29 },
1231         { "Latitude E5450",     0x29 },
1232         { "Latitude E5550",     0x29 },
1233         { "Latitude E6440",     0x29 },
1234         { "Latitude E6440 ATG", 0x29 },
1235         { "Latitude E6540",     0x29 },
1236         /*
1237          * Additional individual entries were added after verification.
1238          */
1239         { "Latitude 5480",      0x29 },
1240         { "Vostro V131",        0x1d },
1241 };
1242
1243 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1244 {
1245         struct i2c_board_info info;
1246         const char *dmi_product_name;
1247         int i;
1248
1249         dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1250         for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1251                 if (strcmp(dmi_product_name,
1252                            dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1253                         break;
1254         }
1255
1256         if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1257                 dev_warn(&priv->pci_dev->dev,
1258                          "Accelerometer lis3lv02d is present on SMBus but its"
1259                          " address is unknown, skipping registration\n");
1260                 return;
1261         }
1262
1263         memset(&info, 0, sizeof(struct i2c_board_info));
1264         info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1265         strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1266         i2c_new_client_device(&priv->adapter, &info);
1267 }
1268
1269 /* Register optional slaves */
1270 static void i801_probe_optional_slaves(struct i801_priv *priv)
1271 {
1272         /* Only register slaves on main SMBus channel */
1273         if (priv->features & FEATURE_IDF)
1274                 return;
1275
1276         if (apanel_addr) {
1277                 struct i2c_board_info info = {
1278                         .addr = apanel_addr,
1279                         .type = "fujitsu_apanel",
1280                 };
1281
1282                 i2c_new_client_device(&priv->adapter, &info);
1283         }
1284
1285         if (dmi_name_in_vendors("FUJITSU"))
1286                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1287
1288         if (is_dell_system_with_lis3lv02d())
1289                 register_dell_lis3lv02d_i2c_device(priv);
1290
1291         /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1292 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1293         if (!priv->mux_drvdata)
1294 #endif
1295                 i2c_register_spd(&priv->adapter);
1296 }
1297 #else
1298 static void __init input_apanel_init(void) {}
1299 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1300 #endif  /* CONFIG_X86 && CONFIG_DMI */
1301
1302 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1303 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1304         .gpio_chip = "gpio_ich",
1305         .values = { 0x02, 0x03 },
1306         .n_values = 2,
1307         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1308         .gpios = { 52, 53 },
1309         .n_gpios = 2,
1310 };
1311
1312 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1313         .gpio_chip = "gpio_ich",
1314         .values = { 0x02, 0x03, 0x01 },
1315         .n_values = 3,
1316         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1317         .gpios = { 52, 53 },
1318         .n_gpios = 2,
1319 };
1320
1321 static const struct dmi_system_id mux_dmi_table[] = {
1322         {
1323                 .matches = {
1324                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1325                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1326                 },
1327                 .driver_data = &i801_mux_config_asus_z8_d12,
1328         },
1329         {
1330                 .matches = {
1331                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1332                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1333                 },
1334                 .driver_data = &i801_mux_config_asus_z8_d12,
1335         },
1336         {
1337                 .matches = {
1338                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1339                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1340                 },
1341                 .driver_data = &i801_mux_config_asus_z8_d12,
1342         },
1343         {
1344                 .matches = {
1345                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1346                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1347                 },
1348                 .driver_data = &i801_mux_config_asus_z8_d12,
1349         },
1350         {
1351                 .matches = {
1352                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1353                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1354                 },
1355                 .driver_data = &i801_mux_config_asus_z8_d12,
1356         },
1357         {
1358                 .matches = {
1359                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1360                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1361                 },
1362                 .driver_data = &i801_mux_config_asus_z8_d12,
1363         },
1364         {
1365                 .matches = {
1366                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1367                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1368                 },
1369                 .driver_data = &i801_mux_config_asus_z8_d18,
1370         },
1371         {
1372                 .matches = {
1373                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1374                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1375                 },
1376                 .driver_data = &i801_mux_config_asus_z8_d18,
1377         },
1378         {
1379                 .matches = {
1380                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1381                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1382                 },
1383                 .driver_data = &i801_mux_config_asus_z8_d12,
1384         },
1385         { }
1386 };
1387
1388 /* Setup multiplexing if needed */
1389 static void i801_add_mux(struct i801_priv *priv)
1390 {
1391         struct device *dev = &priv->adapter.dev;
1392         const struct i801_mux_config *mux_config;
1393         struct i2c_mux_gpio_platform_data gpio_data;
1394         struct gpiod_lookup_table *lookup;
1395         int i;
1396
1397         if (!priv->mux_drvdata)
1398                 return;
1399         mux_config = priv->mux_drvdata;
1400
1401         /* Prepare the platform data */
1402         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1403         gpio_data.parent = priv->adapter.nr;
1404         gpio_data.values = mux_config->values;
1405         gpio_data.n_values = mux_config->n_values;
1406         gpio_data.classes = mux_config->classes;
1407         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1408
1409         /* Register GPIO descriptor lookup table */
1410         lookup = devm_kzalloc(dev,
1411                               struct_size(lookup, table, mux_config->n_gpios + 1),
1412                               GFP_KERNEL);
1413         if (!lookup)
1414                 return;
1415         lookup->dev_id = "i2c-mux-gpio";
1416         for (i = 0; i < mux_config->n_gpios; i++)
1417                 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip,
1418                                                mux_config->gpios[i], "mux", 0);
1419         gpiod_add_lookup_table(lookup);
1420         priv->lookup = lookup;
1421
1422         /*
1423          * Register the mux device, we use PLATFORM_DEVID_NONE here
1424          * because since we are referring to the GPIO chip by name we are
1425          * anyways in deep trouble if there is more than one of these
1426          * devices, and there should likely only be one platform controller
1427          * hub.
1428          */
1429         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1430                                 PLATFORM_DEVID_NONE, &gpio_data,
1431                                 sizeof(struct i2c_mux_gpio_platform_data));
1432         if (IS_ERR(priv->mux_pdev)) {
1433                 gpiod_remove_lookup_table(lookup);
1434                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1435         }
1436 }
1437
1438 static void i801_del_mux(struct i801_priv *priv)
1439 {
1440         platform_device_unregister(priv->mux_pdev);
1441         gpiod_remove_lookup_table(priv->lookup);
1442 }
1443
1444 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1445 {
1446         const struct dmi_system_id *id;
1447         const struct i801_mux_config *mux_config;
1448         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1449         int i;
1450
1451         id = dmi_first_match(mux_dmi_table);
1452         if (id) {
1453                 /* Remove branch classes from trunk */
1454                 mux_config = id->driver_data;
1455                 for (i = 0; i < mux_config->n_values; i++)
1456                         class &= ~mux_config->classes[i];
1457
1458                 /* Remember for later */
1459                 priv->mux_drvdata = mux_config;
1460         }
1461
1462         return class;
1463 }
1464 #else
1465 static inline void i801_add_mux(struct i801_priv *priv) { }
1466 static inline void i801_del_mux(struct i801_priv *priv) { }
1467
1468 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1469 {
1470         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1471 }
1472 #endif
1473
1474 static struct platform_device *
1475 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1476                  struct resource *tco_res)
1477 {
1478         static const struct itco_wdt_platform_data pldata = {
1479                 .name = "Intel PCH",
1480                 .version = 4,
1481         };
1482         struct resource *res;
1483         unsigned int devfn;
1484         u64 base64_addr;
1485         u32 base_addr;
1486         u8 hidden;
1487
1488         /*
1489          * We must access the NO_REBOOT bit over the Primary to Sideband
1490          * bridge (P2SB). The BIOS prevents the P2SB device from being
1491          * enumerated by the PCI subsystem, so we need to unhide/hide it
1492          * to lookup the P2SB BAR.
1493          */
1494         pci_lock_rescan_remove();
1495
1496         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1497
1498         /* Unhide the P2SB device, if it is hidden */
1499         pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1500         if (hidden)
1501                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1502
1503         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1504         base64_addr = base_addr & 0xfffffff0;
1505
1506         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1507         base64_addr |= (u64)base_addr << 32;
1508
1509         /* Hide the P2SB device, if it was hidden before */
1510         if (hidden)
1511                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1512         pci_unlock_rescan_remove();
1513
1514         res = &tco_res[1];
1515         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1516                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1517         else
1518                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1519
1520         res->end = res->start + 3;
1521         res->flags = IORESOURCE_MEM;
1522
1523         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1524                                         tco_res, 2, &pldata, sizeof(pldata));
1525 }
1526
1527 static struct platform_device *
1528 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1529                  struct resource *tco_res)
1530 {
1531         static const struct itco_wdt_platform_data pldata = {
1532                 .name = "Intel PCH",
1533                 .version = 6,
1534         };
1535
1536         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1537                                                  tco_res, 1, &pldata, sizeof(pldata));
1538 }
1539
1540 static void i801_add_tco(struct i801_priv *priv)
1541 {
1542         struct pci_dev *pci_dev = priv->pci_dev;
1543         struct resource tco_res[2], *res;
1544         u32 tco_base, tco_ctl;
1545
1546         /* If we have ACPI based watchdog use that instead */
1547         if (acpi_has_watchdog())
1548                 return;
1549
1550         if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1551                 return;
1552
1553         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1554         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1555         if (!(tco_ctl & TCOCTL_EN))
1556                 return;
1557
1558         memset(tco_res, 0, sizeof(tco_res));
1559         /*
1560          * Always populate the main iTCO IO resource here. The second entry
1561          * for NO_REBOOT MMIO is filled by the SPT specific function.
1562          */
1563         res = &tco_res[0];
1564         res->start = tco_base & ~1;
1565         res->end = res->start + 32 - 1;
1566         res->flags = IORESOURCE_IO;
1567
1568         if (priv->features & FEATURE_TCO_CNL)
1569                 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1570         else
1571                 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1572
1573         if (IS_ERR(priv->tco_pdev))
1574                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1575 }
1576
1577 #ifdef CONFIG_ACPI
1578 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1579                                       acpi_physical_address address)
1580 {
1581         return address >= priv->smba &&
1582                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1583 }
1584
1585 static acpi_status
1586 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1587                      u64 *value, void *handler_context, void *region_context)
1588 {
1589         struct i801_priv *priv = handler_context;
1590         struct pci_dev *pdev = priv->pci_dev;
1591         acpi_status status;
1592
1593         /*
1594          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1595          * further access from the driver itself. This device is now owned
1596          * by the system firmware.
1597          */
1598         mutex_lock(&priv->acpi_lock);
1599
1600         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1601                 priv->acpi_reserved = true;
1602
1603                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1604                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1605
1606                 /*
1607                  * BIOS is accessing the host controller so prevent it from
1608                  * suspending automatically from now on.
1609                  */
1610                 pm_runtime_get_sync(&pdev->dev);
1611         }
1612
1613         if ((function & ACPI_IO_MASK) == ACPI_READ)
1614                 status = acpi_os_read_port(address, (u32 *)value, bits);
1615         else
1616                 status = acpi_os_write_port(address, (u32)*value, bits);
1617
1618         mutex_unlock(&priv->acpi_lock);
1619
1620         return status;
1621 }
1622
1623 static int i801_acpi_probe(struct i801_priv *priv)
1624 {
1625         acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1626         acpi_status status;
1627
1628         status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO,
1629                                                     i801_acpi_io_handler, NULL, priv);
1630         if (ACPI_SUCCESS(status))
1631                 return 0;
1632
1633         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1634 }
1635
1636 static void i801_acpi_remove(struct i801_priv *priv)
1637 {
1638         acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1639
1640         acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1641 }
1642 #else
1643 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1644 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1645 #endif
1646
1647 static void i801_setup_hstcfg(struct i801_priv *priv)
1648 {
1649         unsigned char hstcfg = priv->original_hstcfg;
1650
1651         hstcfg &= ~SMBHSTCFG_I2C_EN;    /* SMBus timing */
1652         hstcfg |= SMBHSTCFG_HST_EN;
1653         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1654 }
1655
1656 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1657 {
1658         int err, i;
1659         struct i801_priv *priv;
1660
1661         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1662         if (!priv)
1663                 return -ENOMEM;
1664
1665         i2c_set_adapdata(&priv->adapter, priv);
1666         priv->adapter.owner = THIS_MODULE;
1667         priv->adapter.class = i801_get_adapter_class(priv);
1668         priv->adapter.algo = &smbus_algorithm;
1669         priv->adapter.dev.parent = &dev->dev;
1670         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1671         priv->adapter.retries = 3;
1672         mutex_init(&priv->acpi_lock);
1673
1674         priv->pci_dev = dev;
1675         priv->features = id->driver_data;
1676
1677         /* Disable features on user request */
1678         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1679                 if (priv->features & disable_features & (1 << i))
1680                         dev_notice(&dev->dev, "%s disabled by user\n",
1681                                    i801_feature_names[i]);
1682         }
1683         priv->features &= ~disable_features;
1684
1685         err = pcim_enable_device(dev);
1686         if (err) {
1687                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1688                         err);
1689                 return err;
1690         }
1691         pcim_pin_device(dev);
1692
1693         /* Determine the address of the SMBus area */
1694         priv->smba = pci_resource_start(dev, SMBBAR);
1695         if (!priv->smba) {
1696                 dev_err(&dev->dev,
1697                         "SMBus base address uninitialized, upgrade BIOS\n");
1698                 return -ENODEV;
1699         }
1700
1701         if (i801_acpi_probe(priv))
1702                 return -ENODEV;
1703
1704         err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME);
1705         if (err) {
1706                 dev_err(&dev->dev,
1707                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1708                         priv->smba,
1709                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1710                 i801_acpi_remove(priv);
1711                 return err;
1712         }
1713
1714         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1715         i801_setup_hstcfg(priv);
1716         if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1717                 dev_info(&dev->dev, "Enabling SMBus device\n");
1718
1719         if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1720                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1721                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1722                 priv->features &= ~FEATURE_IRQ;
1723         }
1724         if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1725                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1726
1727         /* Clear special mode bits */
1728         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1729                 outb_p(inb_p(SMBAUXCTL(priv)) &
1730                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1731
1732         /* Remember original Interrupt and Host Notify settings */
1733         priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL;
1734         if (priv->features & FEATURE_HOST_NOTIFY)
1735                 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1736
1737         /* Default timeout in interrupt mode: 200 ms */
1738         priv->adapter.timeout = HZ / 5;
1739
1740         if (dev->irq == IRQ_NOTCONNECTED)
1741                 priv->features &= ~FEATURE_IRQ;
1742
1743         if (priv->features & FEATURE_IRQ) {
1744                 u16 pcists;
1745
1746                 /* Complain if an interrupt is already pending */
1747                 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1748                 if (pcists & PCI_STATUS_INTERRUPT)
1749                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1750         }
1751
1752         if (priv->features & FEATURE_IRQ) {
1753                 init_completion(&priv->done);
1754
1755                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1756                                        IRQF_SHARED, DRV_NAME, priv);
1757                 if (err) {
1758                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1759                                 dev->irq, err);
1760                         priv->features &= ~FEATURE_IRQ;
1761                 }
1762         }
1763         dev_info(&dev->dev, "SMBus using %s\n",
1764                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1765
1766         i801_add_tco(priv);
1767
1768         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1769                 "SMBus I801 adapter at %04lx", priv->smba);
1770         err = i2c_add_adapter(&priv->adapter);
1771         if (err) {
1772                 i801_acpi_remove(priv);
1773                 return err;
1774         }
1775
1776         i801_enable_host_notify(&priv->adapter);
1777
1778         i801_probe_optional_slaves(priv);
1779         /* We ignore errors - multiplexing is optional */
1780         i801_add_mux(priv);
1781
1782         pci_set_drvdata(dev, priv);
1783
1784         dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1785         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1786         pm_runtime_use_autosuspend(&dev->dev);
1787         pm_runtime_put_autosuspend(&dev->dev);
1788         pm_runtime_allow(&dev->dev);
1789
1790         return 0;
1791 }
1792
1793 static void i801_remove(struct pci_dev *dev)
1794 {
1795         struct i801_priv *priv = pci_get_drvdata(dev);
1796
1797         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1798         i801_disable_host_notify(priv);
1799         i801_del_mux(priv);
1800         i2c_del_adapter(&priv->adapter);
1801         i801_acpi_remove(priv);
1802         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1803
1804         platform_device_unregister(priv->tco_pdev);
1805
1806         /* if acpi_reserved is set then usage_count is incremented already */
1807         if (!priv->acpi_reserved)
1808                 pm_runtime_get_noresume(&dev->dev);
1809
1810         /*
1811          * do not call pci_disable_device(dev) since it can cause hard hangs on
1812          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1813          */
1814 }
1815
1816 static void i801_shutdown(struct pci_dev *dev)
1817 {
1818         struct i801_priv *priv = pci_get_drvdata(dev);
1819
1820         /* Restore config registers to avoid hard hang on some systems */
1821         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1822         i801_disable_host_notify(priv);
1823         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1824 }
1825
1826 #ifdef CONFIG_PM_SLEEP
1827 static int i801_suspend(struct device *dev)
1828 {
1829         struct i801_priv *priv = dev_get_drvdata(dev);
1830
1831         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1832         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1833         return 0;
1834 }
1835
1836 static int i801_resume(struct device *dev)
1837 {
1838         struct i801_priv *priv = dev_get_drvdata(dev);
1839
1840         i801_setup_hstcfg(priv);
1841         i801_enable_host_notify(&priv->adapter);
1842
1843         return 0;
1844 }
1845 #endif
1846
1847 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1848
1849 static struct pci_driver i801_driver = {
1850         .name           = DRV_NAME,
1851         .id_table       = i801_ids,
1852         .probe          = i801_probe,
1853         .remove         = i801_remove,
1854         .shutdown       = i801_shutdown,
1855         .driver         = {
1856                 .pm     = &i801_pm_ops,
1857         },
1858 };
1859
1860 static int __init i2c_i801_init(void)
1861 {
1862         if (dmi_name_in_vendors("FUJITSU"))
1863                 input_apanel_init();
1864         return pci_register_driver(&i801_driver);
1865 }
1866
1867 static void __exit i2c_i801_exit(void)
1868 {
1869         pci_unregister_driver(&i801_driver);
1870 }
1871
1872 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1873 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1874 MODULE_DESCRIPTION("I801 SMBus driver");
1875 MODULE_LICENSE("GPL");
1876
1877 module_init(i2c_i801_init);
1878 module_exit(i2c_i801_exit);