drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2012  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21  * Supports the following Intel I/O Controller Hubs (ICH):
  22  *
  23  *                                      I/O                     Block   I2C
  24  *                                      region  SMBus   Block   proc.   block
  25  * Chip name                    PCI ID  size    PEC     buffer  call    read
  26  * ---------------------------------------------------------------------------
  27  * 82801AA (ICH)                0x2413  16      no      no      no      no
  28  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40  * ICH10                        0x3a30  32      hard    yes     yes     yes
  41  * ICH10                        0x3a60  32      hard    yes     yes     yes
  42  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61  *
  62  * Features supported by this driver:
  63  * Software PEC                         no
  64  * Hardware PEC                         yes
  65  * Block buffer                         yes
  66  * Block process call transaction       no
  67  * I2C block read transaction           yes (doesn't use the block buffer)
  68  * Slave mode                           no
  69  * Interrupt processing                 yes
  70  *
  71  * See the file Documentation/i2c/busses/i2c-i801 for details.
  72  */
  73
  74 #include <linux/interrupt.h>
  75 #include <linux/module.h>
  76 #include <linux/pci.h>
  77 #include <linux/kernel.h>
  78 #include <linux/stddef.h>
  79 #include <linux/delay.h>
  80 #include <linux/ioport.h>
  81 #include <linux/init.h>
  82 #include <linux/i2c.h>
  83 #include <linux/acpi.h>
  84 #include <linux/io.h>
  85 #include <linux/dmi.h>
  86 #include <linux/slab.h>
  87 #include <linux/wait.h>
  88 #include <linux/err.h>
  89
  90 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
  91                 defined CONFIG_DMI
  92 #include <linux/gpio.h>
  93 #include <linux/i2c-mux-gpio.h>
  94 #include <linux/platform_device.h>
  95 #endif
  96
  97 /* I801 SMBus address offsets */
  98 #define SMBHSTSTS(p)    (0 + (p)->smba)
  99 #define SMBHSTCNT(p)    (2 + (p)->smba)
 100 #define SMBHSTCMD(p)    (3 + (p)->smba)
 101 #define SMBHSTADD(p)    (4 + (p)->smba)
 102 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 103 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 104 #define SMBBLKDAT(p)    (7 + (p)->smba)
 105 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 106 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 107 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 108
 109 /* PCI Address Constants */
 110 #define SMBBAR          4
 111 #define SMBPCISTS       0x006
 112 #define SMBHSTCFG       0x040
 113
 114 /* Host status bits for SMBPCISTS */
 115 #define SMBPCISTS_INTS          0x08
 116
 117 /* Host configuration bits for SMBHSTCFG */
 118 #define SMBHSTCFG_HST_EN        1
 119 #define SMBHSTCFG_SMB_SMI_EN    2
 120 #define SMBHSTCFG_I2C_EN        4
 121
 122 /* Auxiliary control register bits, ICH4+ only */
 123 #define SMBAUXCTL_CRC           1
 124 #define SMBAUXCTL_E32B          2
 125
 126 /* Other settings */
 127 #define MAX_RETRIES             400
 128
 129 /* I801 command constants */
 130 #define I801_QUICK              0x00
 131 #define I801_BYTE               0x04
 132 #define I801_BYTE_DATA          0x08
 133 #define I801_WORD_DATA          0x0C
 134 #define I801_PROC_CALL          0x10    /* unimplemented */
 135 #define I801_BLOCK_DATA         0x14
 136 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 137
 138 /* I801 Host Control register bits */
 139 #define SMBHSTCNT_INTREN        0x01
 140 #define SMBHSTCNT_KILL          0x02
 141 #define SMBHSTCNT_LAST_BYTE     0x20
 142 #define SMBHSTCNT_START         0x40
 143 #define SMBHSTCNT_PEC_EN        0x80    /* ICH3 and later */
 144
 145 /* I801 Hosts Status register bits */
 146 #define SMBHSTSTS_BYTE_DONE     0x80
 147 #define SMBHSTSTS_INUSE_STS     0x40
 148 #define SMBHSTSTS_SMBALERT_STS  0x20
 149 #define SMBHSTSTS_FAILED        0x10
 150 #define SMBHSTSTS_BUS_ERR       0x08
 151 #define SMBHSTSTS_DEV_ERR       0x04
 152 #define SMBHSTSTS_INTR          0x02
 153 #define SMBHSTSTS_HOST_BUSY     0x01
 154
 155 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 156                                  SMBHSTSTS_DEV_ERR)
 157
 158 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 159                                  STATUS_ERROR_FLAGS)
 160
 161 /* Older devices have their ID defined in <linux/pci_ids.h> */
 162 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 163 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 164 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 165 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 166 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 167 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 168 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 169 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 170 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 171 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 172 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 173 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 174 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 175 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 176 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 177 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 178 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 179 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 180 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 181 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 182 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 183
 184 struct i801_mux_config {
 185         char *gpio_chip;
 186         unsigned values[3];
 187         int n_values;
 188         unsigned classes[3];
 189         unsigned gpios[2];              /* Relative to gpio_chip->base */
 190         int n_gpios;
 191 };
 192
 193 struct i801_priv {
 194         struct i2c_adapter adapter;
 195         unsigned long smba;
 196         unsigned char original_hstcfg;
 197         struct pci_dev *pci_dev;
 198         unsigned int features;
 199
 200         /* isr processing */
 201         wait_queue_head_t waitq;
 202         u8 status;
 203
 204         /* Command state used by isr for byte-by-byte block transactions */
 205         u8 cmd;
 206         bool is_read;
 207         int count;
 208         int len;
 209         u8 *data;
 210
 211 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 212                 defined CONFIG_DMI
 213         const struct i801_mux_config *mux_drvdata;
 214         struct platform_device *mux_pdev;
 215 #endif
 216 };
 217
 218 static struct pci_driver i801_driver;
 219
 220 #define FEATURE_SMBUS_PEC       (1 << 0)
 221 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 222 #define FEATURE_BLOCK_PROC      (1 << 2)
 223 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 224 #define FEATURE_IRQ             (1 << 4)
 225 /* Not really a feature, but it's convenient to handle it as such */
 226 #define FEATURE_IDF             (1 << 15)
 227
 228 static const char *i801_feature_names[] = {
 229         "SMBus PEC",
 230         "Block buffer",
 231         "Block process call",
 232         "I2C block read",
 233         "Interrupt",
 234 };
 235
 236 static unsigned int disable_features;
 237 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 238 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 239         "\t\t  0x01  disable SMBus PEC\n"
 240         "\t\t  0x02  disable the block buffer\n"
 241         "\t\t  0x08  disable the I2C block read functionality\n"
 242         "\t\t  0x10  don't use interrupts ");
 243
 244 /* Make sure the SMBus host is ready to start transmitting.
 245    Return 0 if it is, -EBUSY if it is not. */
 246 static int i801_check_pre(struct i801_priv *priv)
 247 {
 248         int status;
 249
 250         status = inb_p(SMBHSTSTS(priv));
 251         if (status & SMBHSTSTS_HOST_BUSY) {
 252                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 253                 return -EBUSY;
 254         }
 255
 256         status &= STATUS_FLAGS;
 257         if (status) {
 258                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 259                         status);
 260                 outb_p(status, SMBHSTSTS(priv));
 261                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 262                 if (status) {
 263                         dev_err(&priv->pci_dev->dev,
 264                                 "Failed clearing status flags (%02x)\n",
 265                                 status);
 266                         return -EBUSY;
 267                 }
 268         }
 269
 270         return 0;
 271 }
 272
 273 /*
 274  * Convert the status register to an error code, and clear it.
 275  * Note that status only contains the bits we want to clear, not the
 276  * actual register value.
 277  */
 278 static int i801_check_post(struct i801_priv *priv, int status)
 279 {
 280         int result = 0;
 281
 282         /*
 283          * If the SMBus is still busy, we give up
 284          * Note: This timeout condition only happens when using polling
 285          * transactions.  For interrupt operation, NAK/timeout is indicated by
 286          * DEV_ERR.
 287          */
 288         if (unlikely(status < 0)) {
 289                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 290                 /* try to stop the current command */
 291                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 292                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 293                        SMBHSTCNT(priv));
 294                 usleep_range(1000, 2000);
 295                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 296                        SMBHSTCNT(priv));
 297
 298                 /* Check if it worked */
 299                 status = inb_p(SMBHSTSTS(priv));
 300                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 301                     !(status & SMBHSTSTS_FAILED))
 302                         dev_err(&priv->pci_dev->dev,
 303                                 "Failed terminating the transaction\n");
 304                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 305                 return -ETIMEDOUT;
 306         }
 307
 308         if (status & SMBHSTSTS_FAILED) {
 309                 result = -EIO;
 310                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 311         }
 312         if (status & SMBHSTSTS_DEV_ERR) {
 313                 result = -ENXIO;
 314                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 315         }
 316         if (status & SMBHSTSTS_BUS_ERR) {
 317                 result = -EAGAIN;
 318                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 319         }
 320
 321         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 322         outb_p(status, SMBHSTSTS(priv));
 323
 324         return result;
 325 }
 326
 327 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 328 static int i801_wait_intr(struct i801_priv *priv)
 329 {
 330         int timeout = 0;
 331         int status;
 332
 333         /* We will always wait for a fraction of a second! */
 334         do {
 335                 usleep_range(250, 500);
 336                 status = inb_p(SMBHSTSTS(priv));
 337         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 338                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 339                  (timeout++ < MAX_RETRIES));
 340
 341         if (timeout > MAX_RETRIES) {
 342                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 343                 return -ETIMEDOUT;
 344         }
 345         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 346 }
 347
 348 /* Wait for either BYTE_DONE or an error flag being set */
 349 static int i801_wait_byte_done(struct i801_priv *priv)
 350 {
 351         int timeout = 0;
 352         int status;
 353
 354         /* We will always wait for a fraction of a second! */
 355         do {
 356                 usleep_range(250, 500);
 357                 status = inb_p(SMBHSTSTS(priv));
 358         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 359                  (timeout++ < MAX_RETRIES));
 360
 361         if (timeout > MAX_RETRIES) {
 362                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 363                 return -ETIMEDOUT;
 364         }
 365         return status & STATUS_ERROR_FLAGS;
 366 }
 367
 368 static int i801_transaction(struct i801_priv *priv, int xact)
 369 {
 370         int status;
 371         int result;
 372
 373         result = i801_check_pre(priv);
 374         if (result < 0)
 375                 return result;
 376
 377         if (priv->features & FEATURE_IRQ) {
 378                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 379                        SMBHSTCNT(priv));
 380                 wait_event(priv->waitq, (status = priv->status));
 381                 priv->status = 0;
 382                 return i801_check_post(priv, status);
 383         }
 384
 385         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 386          * SMBSCMD are passed in xact */
 387         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 388
 389         status = i801_wait_intr(priv);
 390         return i801_check_post(priv, status);
 391 }
 392
 393 static int i801_block_transaction_by_block(struct i801_priv *priv,
 394                                            union i2c_smbus_data *data,
 395                                            char read_write, int hwpec)
 396 {
 397         int i, len;
 398         int status;
 399
 400         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 401
 402         /* Use 32-byte buffer to process this transaction */
 403         if (read_write == I2C_SMBUS_WRITE) {
 404                 len = data->block[0];
 405                 outb_p(len, SMBHSTDAT0(priv));
 406                 for (i = 0; i < len; i++)
 407                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 408         }
 409
 410         status = i801_transaction(priv, I801_BLOCK_DATA |
 411                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 412         if (status)
 413                 return status;
 414
 415         if (read_write == I2C_SMBUS_READ) {
 416                 len = inb_p(SMBHSTDAT0(priv));
 417                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 418                         return -EPROTO;
 419
 420                 data->block[0] = len;
 421                 for (i = 0; i < len; i++)
 422                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 423         }
 424         return 0;
 425 }
 426
 427 static void i801_isr_byte_done(struct i801_priv *priv)
 428 {
 429         if (priv->is_read) {
 430                 /* For SMBus block reads, length is received with first byte */
 431                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 432                     (priv->count == 0)) {
 433                         priv->len = inb_p(SMBHSTDAT0(priv));
 434                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 435                                 dev_err(&priv->pci_dev->dev,
 436                                         "Illegal SMBus block read size %d\n",
 437                                         priv->len);
 438                                 /* FIXME: Recover */
 439                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 440                         } else {
 441                                 dev_dbg(&priv->pci_dev->dev,
 442                                         "SMBus block read size is %d\n",
 443                                         priv->len);
 444                         }
 445                         priv->data[-1] = priv->len;
 446                 }
 447
 448                 /* Read next byte */
 449                 if (priv->count < priv->len)
 450                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 451                 else
 452                         dev_dbg(&priv->pci_dev->dev,
 453                                 "Discarding extra byte on block read\n");
 454
 455                 /* Set LAST_BYTE for last byte of read transaction */
 456                 if (priv->count == priv->len - 1)
 457                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 458                                SMBHSTCNT(priv));
 459         } else if (priv->count < priv->len - 1) {
 460                 /* Write next byte, except for IRQ after last byte */
 461                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 462         }
 463
 464         /* Clear BYTE_DONE to continue with next byte */
 465         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 466 }
 467
 468 /*
 469  * There are two kinds of interrupts:
 470  *
 471  * 1) i801 signals transaction completion with one of these interrupts:
 472  *      INTR - Success
 473  *      DEV_ERR - Invalid command, NAK or communication timeout
 474  *      BUS_ERR - SMI# transaction collision
 475  *      FAILED - transaction was canceled due to a KILL request
 476  *    When any of these occur, update ->status and wake up the waitq.
 477  *    ->status must be cleared before kicking off the next transaction.
 478  *
 479  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 480  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 481  */
 482 static irqreturn_t i801_isr(int irq, void *dev_id)
 483 {
 484         struct i801_priv *priv = dev_id;
 485         u16 pcists;
 486         u8 status;
 487
 488         /* Confirm this is our interrupt */
 489         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 490         if (!(pcists & SMBPCISTS_INTS))
 491                 return IRQ_NONE;
 492
 493         status = inb_p(SMBHSTSTS(priv));
 494         if (status != 0x42)
 495                 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
 496
 497         if (status & SMBHSTSTS_BYTE_DONE)
 498                 i801_isr_byte_done(priv);
 499
 500         /*
 501          * Clear irq sources and report transaction result.
 502          * ->status must be cleared before the next transaction is started.
 503          */
 504         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 505         if (status) {
 506                 outb_p(status, SMBHSTSTS(priv));
 507                 priv->status |= status;
 508                 wake_up(&priv->waitq);
 509         }
 510
 511         return IRQ_HANDLED;
 512 }
 513
 514 /*
 515  * For "byte-by-byte" block transactions:
 516  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 517  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 518  */
 519 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 520                                                union i2c_smbus_data *data,
 521                                                char read_write, int command,
 522                                                int hwpec)
 523 {
 524         int i, len;
 525         int smbcmd;
 526         int status;
 527         int result;
 528
 529         result = i801_check_pre(priv);
 530         if (result < 0)
 531                 return result;
 532
 533         len = data->block[0];
 534
 535         if (read_write == I2C_SMBUS_WRITE) {
 536                 outb_p(len, SMBHSTDAT0(priv));
 537                 outb_p(data->block[1], SMBBLKDAT(priv));
 538         }
 539
 540         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 541             read_write == I2C_SMBUS_READ)
 542                 smbcmd = I801_I2C_BLOCK_DATA;
 543         else
 544                 smbcmd = I801_BLOCK_DATA;
 545
 546         if (priv->features & FEATURE_IRQ) {
 547                 priv->is_read = (read_write == I2C_SMBUS_READ);
 548                 if (len == 1 && priv->is_read)
 549                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 550                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 551                 priv->len = len;
 552                 priv->count = 0;
 553                 priv->data = &data->block[1];
 554
 555                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 556                 wait_event(priv->waitq, (status = priv->status));
 557                 priv->status = 0;
 558                 return i801_check_post(priv, status);
 559         }
 560
 561         for (i = 1; i <= len; i++) {
 562                 if (i == len && read_write == I2C_SMBUS_READ)
 563                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 564                 outb_p(smbcmd, SMBHSTCNT(priv));
 565
 566                 if (i == 1)
 567                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 568                                SMBHSTCNT(priv));
 569
 570                 status = i801_wait_byte_done(priv);
 571                 if (status)
 572                         goto exit;
 573
 574                 if (i == 1 && read_write == I2C_SMBUS_READ
 575                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 576                         len = inb_p(SMBHSTDAT0(priv));
 577                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 578                                 dev_err(&priv->pci_dev->dev,
 579                                         "Illegal SMBus block read size %d\n",
 580                                         len);
 581                                 /* Recover */
 582                                 while (inb_p(SMBHSTSTS(priv)) &
 583                                        SMBHSTSTS_HOST_BUSY)
 584                                         outb_p(SMBHSTSTS_BYTE_DONE,
 585                                                SMBHSTSTS(priv));
 586                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 587                                 return -EPROTO;
 588                         }
 589                         data->block[0] = len;
 590                 }
 591
 592                 /* Retrieve/store value in SMBBLKDAT */
 593                 if (read_write == I2C_SMBUS_READ)
 594                         data->block[i] = inb_p(SMBBLKDAT(priv));
 595                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 596                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 597
 598                 /* signals SMBBLKDAT ready */
 599                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 600         }
 601
 602         status = i801_wait_intr(priv);
 603 exit:
 604         return i801_check_post(priv, status);
 605 }
 606
 607 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 608 {
 609         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 610         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 611                 return -EIO;
 612         return 0;
 613 }
 614
 615 /* Block transaction function */
 616 static int i801_block_transaction(struct i801_priv *priv,
 617                                   union i2c_smbus_data *data, char read_write,
 618                                   int command, int hwpec)
 619 {
 620         int result = 0;
 621         unsigned char hostc;
 622
 623         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 624                 if (read_write == I2C_SMBUS_WRITE) {
 625                         /* set I2C_EN bit in configuration register */
 626                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 627                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 628                                               hostc | SMBHSTCFG_I2C_EN);
 629                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 630                         dev_err(&priv->pci_dev->dev,
 631                                 "I2C block read is unsupported!\n");
 632                         return -EOPNOTSUPP;
 633                 }
 634         }
 635
 636         if (read_write == I2C_SMBUS_WRITE
 637          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 638                 if (data->block[0] < 1)
 639                         data->block[0] = 1;
 640                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 641                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 642         } else {
 643                 data->block[0] = 32;    /* max for SMBus block reads */
 644         }
 645
 646         /* Experience has shown that the block buffer can only be used for
 647            SMBus (not I2C) block transactions, even though the datasheet
 648            doesn't mention this limitation. */
 649         if ((priv->features & FEATURE_BLOCK_BUFFER)
 650          && command != I2C_SMBUS_I2C_BLOCK_DATA
 651          && i801_set_block_buffer_mode(priv) == 0)
 652                 result = i801_block_transaction_by_block(priv, data,
 653                                                          read_write, hwpec);
 654         else
 655                 result = i801_block_transaction_byte_by_byte(priv, data,
 656                                                              read_write,
 657                                                              command, hwpec);
 658
 659         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 660          && read_write == I2C_SMBUS_WRITE) {
 661                 /* restore saved configuration register value */
 662                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 663         }
 664         return result;
 665 }
 666
 667 /* Return negative errno on error. */
 668 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 669                        unsigned short flags, char read_write, u8 command,
 670                        int size, union i2c_smbus_data *data)
 671 {
 672         int hwpec;
 673         int block = 0;
 674         int ret, xact = 0;
 675         struct i801_priv *priv = i2c_get_adapdata(adap);
 676
 677         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 678                 && size != I2C_SMBUS_QUICK
 679                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 680
 681         switch (size) {
 682         case I2C_SMBUS_QUICK:
 683                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 684                        SMBHSTADD(priv));
 685                 xact = I801_QUICK;
 686                 break;
 687         case I2C_SMBUS_BYTE:
 688                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 689                        SMBHSTADD(priv));
 690                 if (read_write == I2C_SMBUS_WRITE)
 691                         outb_p(command, SMBHSTCMD(priv));
 692                 xact = I801_BYTE;
 693                 break;
 694         case I2C_SMBUS_BYTE_DATA:
 695                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 696                        SMBHSTADD(priv));
 697                 outb_p(command, SMBHSTCMD(priv));
 698                 if (read_write == I2C_SMBUS_WRITE)
 699                         outb_p(data->byte, SMBHSTDAT0(priv));
 700                 xact = I801_BYTE_DATA;
 701                 break;
 702         case I2C_SMBUS_WORD_DATA:
 703                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 704                        SMBHSTADD(priv));
 705                 outb_p(command, SMBHSTCMD(priv));
 706                 if (read_write == I2C_SMBUS_WRITE) {
 707                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 708                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 709                 }
 710                 xact = I801_WORD_DATA;
 711                 break;
 712         case I2C_SMBUS_BLOCK_DATA:
 713                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 714                        SMBHSTADD(priv));
 715                 outb_p(command, SMBHSTCMD(priv));
 716                 block = 1;
 717                 break;
 718         case I2C_SMBUS_I2C_BLOCK_DATA:
 719                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 720                  * bit should be cleared here, even when reading */
 721                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 722                 if (read_write == I2C_SMBUS_READ) {
 723                         /* NB: page 240 of ICH5 datasheet also shows
 724                          * that DATA1 is the cmd field when reading */
 725                         outb_p(command, SMBHSTDAT1(priv));
 726                 } else
 727                         outb_p(command, SMBHSTCMD(priv));
 728                 block = 1;
 729                 break;
 730         default:
 731                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 732                         size);
 733                 return -EOPNOTSUPP;
 734         }
 735
 736         if (hwpec)      /* enable/disable hardware PEC */
 737                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 738         else
 739                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 740                        SMBAUXCTL(priv));
 741
 742         if (block)
 743                 ret = i801_block_transaction(priv, data, read_write, size,
 744                                              hwpec);
 745         else
 746                 ret = i801_transaction(priv, xact);
 747
 748         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 749            time, so we forcibly disable it after every transaction. Turn off
 750            E32B for the same reason. */
 751         if (hwpec || block)
 752                 outb_p(inb_p(SMBAUXCTL(priv)) &
 753                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 754
 755         if (block)
 756                 return ret;
 757         if (ret)
 758                 return ret;
 759         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 760                 return 0;
 761
 762         switch (xact & 0x7f) {
 763         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 764         case I801_BYTE_DATA:
 765                 data->byte = inb_p(SMBHSTDAT0(priv));
 766                 break;
 767         case I801_WORD_DATA:
 768                 data->word = inb_p(SMBHSTDAT0(priv)) +
 769                              (inb_p(SMBHSTDAT1(priv)) << 8);
 770                 break;
 771         }
 772         return 0;
 773 }
 774
 775
 776 static u32 i801_func(struct i2c_adapter *adapter)
 777 {
 778         struct i801_priv *priv = i2c_get_adapdata(adapter);
 779
 780         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 781                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 782                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 783                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 784                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 785                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 786 }
 787
 788 static const struct i2c_algorithm smbus_algorithm = {
 789         .smbus_xfer     = i801_access,
 790         .functionality  = i801_func,
 791 };
 792
 793 static const struct pci_device_id i801_ids[] = {
 794         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 795         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 796         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 797         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 798         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 799         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 800         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 801         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 802         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 803         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 804         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 805         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 806         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 807         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 808         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 809         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 810         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 811         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 812         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 813         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 814         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 815         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 816         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 817         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 818         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 819         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 820         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 821         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 822         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 823         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 824         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 825         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
 826         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
 827         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
 828         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
 829         { 0, }
 830 };
 831
 832 MODULE_DEVICE_TABLE(pci, i801_ids);
 833
 834 #if defined CONFIG_X86 && defined CONFIG_DMI
 835 static unsigned char apanel_addr;
 836
 837 /* Scan the system ROM for the signature "FJKEYINF" */
 838 static __init const void __iomem *bios_signature(const void __iomem *bios)
 839 {
 840         ssize_t offset;
 841         const unsigned char signature[] = "FJKEYINF";
 842
 843         for (offset = 0; offset < 0x10000; offset += 0x10) {
 844                 if (check_signature(bios + offset, signature,
 845                                     sizeof(signature)-1))
 846                         return bios + offset;
 847         }
 848         return NULL;
 849 }
 850
 851 static void __init input_apanel_init(void)
 852 {
 853         void __iomem *bios;
 854         const void __iomem *p;
 855
 856         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 857         p = bios_signature(bios);
 858         if (p) {
 859                 /* just use the first address */
 860                 apanel_addr = readb(p + 8 + 3) >> 1;
 861         }
 862         iounmap(bios);
 863 }
 864
 865 struct dmi_onboard_device_info {
 866         const char *name;
 867         u8 type;
 868         unsigned short i2c_addr;
 869         const char *i2c_type;
 870 };
 871
 872 static const struct dmi_onboard_device_info dmi_devices[] = {
 873         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 874         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 875         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 876 };
 877
 878 static void dmi_check_onboard_device(u8 type, const char *name,
 879                                      struct i2c_adapter *adap)
 880 {
 881         int i;
 882         struct i2c_board_info info;
 883
 884         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 885                 /* & ~0x80, ignore enabled/disabled bit */
 886                 if ((type & ~0x80) != dmi_devices[i].type)
 887                         continue;
 888                 if (strcasecmp(name, dmi_devices[i].name))
 889                         continue;
 890
 891                 memset(&info, 0, sizeof(struct i2c_board_info));
 892                 info.addr = dmi_devices[i].i2c_addr;
 893                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 894                 i2c_new_device(adap, &info);
 895                 break;
 896         }
 897 }
 898
 899 /* We use our own function to check for onboard devices instead of
 900    dmi_find_device() as some buggy BIOS's have the devices we are interested
 901    in marked as disabled */
 902 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
 903 {
 904         int i, count;
 905
 906         if (dm->type != 10)
 907                 return;
 908
 909         count = (dm->length - sizeof(struct dmi_header)) / 2;
 910         for (i = 0; i < count; i++) {
 911                 const u8 *d = (char *)(dm + 1) + (i * 2);
 912                 const char *name = ((char *) dm) + dm->length;
 913                 u8 type = d[0];
 914                 u8 s = d[1];
 915
 916                 if (!s)
 917                         continue;
 918                 s--;
 919                 while (s > 0 && name[0]) {
 920                         name += strlen(name) + 1;
 921                         s--;
 922                 }
 923                 if (name[0] == 0) /* Bogus string reference */
 924                         continue;
 925
 926                 dmi_check_onboard_device(type, name, adap);
 927         }
 928 }
 929
 930 /* Register optional slaves */
 931 static void i801_probe_optional_slaves(struct i801_priv *priv)
 932 {
 933         /* Only register slaves on main SMBus channel */
 934         if (priv->features & FEATURE_IDF)
 935                 return;
 936
 937         if (apanel_addr) {
 938                 struct i2c_board_info info;
 939
 940                 memset(&info, 0, sizeof(struct i2c_board_info));
 941                 info.addr = apanel_addr;
 942                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 943                 i2c_new_device(&priv->adapter, &info);
 944         }
 945
 946         if (dmi_name_in_vendors("FUJITSU"))
 947                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 948 }
 949 #else
 950 static void __init input_apanel_init(void) {}
 951 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
 952 #endif  /* CONFIG_X86 && CONFIG_DMI */
 953
 954 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 955                 defined CONFIG_DMI
 956 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
 957         .gpio_chip = "gpio_ich",
 958         .values = { 0x02, 0x03 },
 959         .n_values = 2,
 960         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
 961         .gpios = { 52, 53 },
 962         .n_gpios = 2,
 963 };
 964
 965 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
 966         .gpio_chip = "gpio_ich",
 967         .values = { 0x02, 0x03, 0x01 },
 968         .n_values = 3,
 969         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
 970         .gpios = { 52, 53 },
 971         .n_gpios = 2,
 972 };
 973
 974 static const struct dmi_system_id mux_dmi_table[] = {
 975         {
 976                 .matches = {
 977                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 978                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
 979                 },
 980                 .driver_data = &i801_mux_config_asus_z8_d12,
 981         },
 982         {
 983                 .matches = {
 984                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 985                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
 986                 },
 987                 .driver_data = &i801_mux_config_asus_z8_d12,
 988         },
 989         {
 990                 .matches = {
 991                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 992                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
 993                 },
 994                 .driver_data = &i801_mux_config_asus_z8_d12,
 995         },
 996         {
 997                 .matches = {
 998                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 999                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1000                 },
1001                 .driver_data = &i801_mux_config_asus_z8_d12,
1002         },
1003         {
1004                 .matches = {
1005                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1006                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1007                 },
1008                 .driver_data = &i801_mux_config_asus_z8_d12,
1009         },
1010         {
1011                 .matches = {
1012                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1013                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1014                 },
1015                 .driver_data = &i801_mux_config_asus_z8_d12,
1016         },
1017         {
1018                 .matches = {
1019                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1020                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1021                 },
1022                 .driver_data = &i801_mux_config_asus_z8_d18,
1023         },
1024         {
1025                 .matches = {
1026                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1027                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1028                 },
1029                 .driver_data = &i801_mux_config_asus_z8_d18,
1030         },
1031         {
1032                 .matches = {
1033                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1034                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1035                 },
1036                 .driver_data = &i801_mux_config_asus_z8_d12,
1037         },
1038         { }
1039 };
1040
1041 /* Setup multiplexing if needed */
1042 static int i801_add_mux(struct i801_priv *priv)
1043 {
1044         struct device *dev = &priv->adapter.dev;
1045         const struct i801_mux_config *mux_config;
1046         struct i2c_mux_gpio_platform_data gpio_data;
1047         int err;
1048
1049         if (!priv->mux_drvdata)
1050                 return 0;
1051         mux_config = priv->mux_drvdata;
1052
1053         /* Prepare the platform data */
1054         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1055         gpio_data.parent = priv->adapter.nr;
1056         gpio_data.values = mux_config->values;
1057         gpio_data.n_values = mux_config->n_values;
1058         gpio_data.classes = mux_config->classes;
1059         gpio_data.gpio_chip = mux_config->gpio_chip;
1060         gpio_data.gpios = mux_config->gpios;
1061         gpio_data.n_gpios = mux_config->n_gpios;
1062         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1063
1064         /* Register the mux device */
1065         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1066                                 PLATFORM_DEVID_AUTO, &gpio_data,
1067                                 sizeof(struct i2c_mux_gpio_platform_data));
1068         if (IS_ERR(priv->mux_pdev)) {
1069                 err = PTR_ERR(priv->mux_pdev);
1070                 priv->mux_pdev = NULL;
1071                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1072                 return err;
1073         }
1074
1075         return 0;
1076 }
1077
1078 static void i801_del_mux(struct i801_priv *priv)
1079 {
1080         if (priv->mux_pdev)
1081                 platform_device_unregister(priv->mux_pdev);
1082 }
1083
1084 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1085 {
1086         const struct dmi_system_id *id;
1087         const struct i801_mux_config *mux_config;
1088         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1089         int i;
1090
1091         id = dmi_first_match(mux_dmi_table);
1092         if (id) {
1093                 /* Remove branch classes from trunk */
1094                 mux_config = id->driver_data;
1095                 for (i = 0; i < mux_config->n_values; i++)
1096                         class &= ~mux_config->classes[i];
1097
1098                 /* Remember for later */
1099                 priv->mux_drvdata = mux_config;
1100         }
1101
1102         return class;
1103 }
1104 #else
1105 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1106 static inline void i801_del_mux(struct i801_priv *priv) { }
1107
1108 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1109 {
1110         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1111 }
1112 #endif
1113
1114 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1115 {
1116         unsigned char temp;
1117         int err, i;
1118         struct i801_priv *priv;
1119
1120         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1121         if (!priv)
1122                 return -ENOMEM;
1123
1124         i2c_set_adapdata(&priv->adapter, priv);
1125         priv->adapter.owner = THIS_MODULE;
1126         priv->adapter.class = i801_get_adapter_class(priv);
1127         priv->adapter.algo = &smbus_algorithm;
1128
1129         priv->pci_dev = dev;
1130         switch (dev->device) {
1131         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1132         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1133         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1134         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1135         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1136         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1137                 priv->features |= FEATURE_IDF;
1138                 /* fall through */
1139         default:
1140                 priv->features |= FEATURE_I2C_BLOCK_READ;
1141                 priv->features |= FEATURE_IRQ;
1142                 /* fall through */
1143         case PCI_DEVICE_ID_INTEL_82801DB_3:
1144                 priv->features |= FEATURE_SMBUS_PEC;
1145                 priv->features |= FEATURE_BLOCK_BUFFER;
1146                 /* fall through */
1147         case PCI_DEVICE_ID_INTEL_82801CA_3:
1148         case PCI_DEVICE_ID_INTEL_82801BA_2:
1149         case PCI_DEVICE_ID_INTEL_82801AB_3:
1150         case PCI_DEVICE_ID_INTEL_82801AA_3:
1151                 break;
1152         }
1153
1154         /* Disable features on user request */
1155         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1156                 if (priv->features & disable_features & (1 << i))
1157                         dev_notice(&dev->dev, "%s disabled by user\n",
1158                                    i801_feature_names[i]);
1159         }
1160         priv->features &= ~disable_features;
1161
1162         err = pci_enable_device(dev);
1163         if (err) {
1164                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1165                         err);
1166                 goto exit;
1167         }
1168
1169         /* Determine the address of the SMBus area */
1170         priv->smba = pci_resource_start(dev, SMBBAR);
1171         if (!priv->smba) {
1172                 dev_err(&dev->dev, "SMBus base address uninitialized, "
1173                         "upgrade BIOS\n");
1174                 err = -ENODEV;
1175                 goto exit;
1176         }
1177
1178         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1179         if (err) {
1180                 err = -ENODEV;
1181                 goto exit;
1182         }
1183
1184         err = pci_request_region(dev, SMBBAR, i801_driver.name);
1185         if (err) {
1186                 dev_err(&dev->dev, "Failed to request SMBus region "
1187                         "0x%lx-0x%Lx\n", priv->smba,
1188                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1189                 goto exit;
1190         }
1191
1192         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1193         priv->original_hstcfg = temp;
1194         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1195         if (!(temp & SMBHSTCFG_HST_EN)) {
1196                 dev_info(&dev->dev, "Enabling SMBus device\n");
1197                 temp |= SMBHSTCFG_HST_EN;
1198         }
1199         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1200
1201         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1202                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1203                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1204                 priv->features &= ~FEATURE_IRQ;
1205         }
1206
1207         /* Clear special mode bits */
1208         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1209                 outb_p(inb_p(SMBAUXCTL(priv)) &
1210                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1211
1212         if (priv->features & FEATURE_IRQ) {
1213                 init_waitqueue_head(&priv->waitq);
1214
1215                 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
1216                                   i801_driver.name, priv);
1217                 if (err) {
1218                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1219                                 dev->irq, err);
1220                         goto exit_release;
1221                 }
1222                 dev_info(&dev->dev, "SMBus using PCI Interrupt\n");
1223         }
1224
1225         /* set up the sysfs linkage to our parent device */
1226         priv->adapter.dev.parent = &dev->dev;
1227
1228         /* Retry up to 3 times on lost arbitration */
1229         priv->adapter.retries = 3;
1230
1231         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1232                 "SMBus I801 adapter at %04lx", priv->smba);
1233         err = i2c_add_adapter(&priv->adapter);
1234         if (err) {
1235                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1236                 goto exit_free_irq;
1237         }
1238
1239         i801_probe_optional_slaves(priv);
1240         /* We ignore errors - multiplexing is optional */
1241         i801_add_mux(priv);
1242
1243         pci_set_drvdata(dev, priv);
1244
1245         return 0;
1246
1247 exit_free_irq:
1248         if (priv->features & FEATURE_IRQ)
1249                 free_irq(dev->irq, priv);
1250 exit_release:
1251         pci_release_region(dev, SMBBAR);
1252 exit:
1253         kfree(priv);
1254         return err;
1255 }
1256
1257 static void i801_remove(struct pci_dev *dev)
1258 {
1259         struct i801_priv *priv = pci_get_drvdata(dev);
1260
1261         i801_del_mux(priv);
1262         i2c_del_adapter(&priv->adapter);
1263         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1264
1265         if (priv->features & FEATURE_IRQ)
1266                 free_irq(dev->irq, priv);
1267         pci_release_region(dev, SMBBAR);
1268
1269         kfree(priv);
1270         /*
1271          * do not call pci_disable_device(dev) since it can cause hard hangs on
1272          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1273          */
1274 }
1275
1276 #ifdef CONFIG_PM
1277 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1278 {
1279         struct i801_priv *priv = pci_get_drvdata(dev);
1280
1281         pci_save_state(dev);
1282         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1283         pci_set_power_state(dev, pci_choose_state(dev, mesg));
1284         return 0;
1285 }
1286
1287 static int i801_resume(struct pci_dev *dev)
1288 {
1289         pci_set_power_state(dev, PCI_D0);
1290         pci_restore_state(dev);
1291         return pci_enable_device(dev);
1292 }
1293 #else
1294 #define i801_suspend NULL
1295 #define i801_resume NULL
1296 #endif
1297
1298 static struct pci_driver i801_driver = {
1299         .name           = "i801_smbus",
1300         .id_table       = i801_ids,
1301         .probe          = i801_probe,
1302         .remove         = i801_remove,
1303         .suspend        = i801_suspend,
1304         .resume         = i801_resume,
1305 };
1306
1307 static int __init i2c_i801_init(void)
1308 {
1309         if (dmi_name_in_vendors("FUJITSU"))
1310                 input_apanel_init();
1311         return pci_register_driver(&i801_driver);
1312 }
1313
1314 static void __exit i2c_i801_exit(void)
1315 {
1316         pci_unregister_driver(&i801_driver);
1317 }
1318
1319 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1320 MODULE_DESCRIPTION("I801 SMBus driver");
1321 MODULE_LICENSE("GPL");
1322
1323 module_init(i2c_i801_init);
1324 module_exit(i2c_i801_exit);