2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Supports the following Intel I/O Controller Hubs (ICH):
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 Panther Point (PCH) 0x1e22 32 hard yes yes yes
54 Lynx Point (PCH) 0x8c22 32 hard yes yes yes
55 Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
56 Avoton (SOC) 0x1f3c 32 hard yes yes yes
57 Wellsburg (PCH) 0x8d22 32 hard yes yes yes
58 Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
59 Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
60 Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
61 Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
63 Features supported by this driver:
67 Block process call transaction no
68 I2C block read transaction yes (doesn't use the block buffer)
70 Interrupt processing yes
72 See the file Documentation/i2c/busses/i2c-i801 for details.
75 #include <linux/interrupt.h>
76 #include <linux/module.h>
77 #include <linux/pci.h>
78 #include <linux/kernel.h>
79 #include <linux/stddef.h>
80 #include <linux/delay.h>
81 #include <linux/ioport.h>
82 #include <linux/init.h>
83 #include <linux/i2c.h>
84 #include <linux/acpi.h>
86 #include <linux/dmi.h>
87 #include <linux/slab.h>
88 #include <linux/wait.h>
89 #include <linux/err.h>
91 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
93 #include <linux/gpio.h>
94 #include <linux/i2c-mux-gpio.h>
95 #include <linux/platform_device.h>
98 /* I801 SMBus address offsets */
99 #define SMBHSTSTS(p) (0 + (p)->smba)
100 #define SMBHSTCNT(p) (2 + (p)->smba)
101 #define SMBHSTCMD(p) (3 + (p)->smba)
102 #define SMBHSTADD(p) (4 + (p)->smba)
103 #define SMBHSTDAT0(p) (5 + (p)->smba)
104 #define SMBHSTDAT1(p) (6 + (p)->smba)
105 #define SMBBLKDAT(p) (7 + (p)->smba)
106 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
107 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
108 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
110 /* PCI Address Constants */
112 #define SMBPCISTS 0x006
113 #define SMBHSTCFG 0x040
115 /* Host status bits for SMBPCISTS */
116 #define SMBPCISTS_INTS 0x08
118 /* Host configuration bits for SMBHSTCFG */
119 #define SMBHSTCFG_HST_EN 1
120 #define SMBHSTCFG_SMB_SMI_EN 2
121 #define SMBHSTCFG_I2C_EN 4
123 /* Auxiliary control register bits, ICH4+ only */
124 #define SMBAUXCTL_CRC 1
125 #define SMBAUXCTL_E32B 2
128 #define MAX_RETRIES 400
130 /* I801 command constants */
131 #define I801_QUICK 0x00
132 #define I801_BYTE 0x04
133 #define I801_BYTE_DATA 0x08
134 #define I801_WORD_DATA 0x0C
135 #define I801_PROC_CALL 0x10 /* unimplemented */
136 #define I801_BLOCK_DATA 0x14
137 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
139 /* I801 Host Control register bits */
140 #define SMBHSTCNT_INTREN 0x01
141 #define SMBHSTCNT_KILL 0x02
142 #define SMBHSTCNT_LAST_BYTE 0x20
143 #define SMBHSTCNT_START 0x40
144 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
146 /* I801 Hosts Status register bits */
147 #define SMBHSTSTS_BYTE_DONE 0x80
148 #define SMBHSTSTS_INUSE_STS 0x40
149 #define SMBHSTSTS_SMBALERT_STS 0x20
150 #define SMBHSTSTS_FAILED 0x10
151 #define SMBHSTSTS_BUS_ERR 0x08
152 #define SMBHSTSTS_DEV_ERR 0x04
153 #define SMBHSTSTS_INTR 0x02
154 #define SMBHSTSTS_HOST_BUSY 0x01
156 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
159 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
162 /* Older devices have their ID defined in <linux/pci_ids.h> */
163 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
164 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
165 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
166 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
167 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
168 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
169 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
170 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
171 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
172 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
173 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
174 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
175 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
176 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
177 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
178 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
179 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
181 struct i801_mux_config {
186 unsigned gpios[2]; /* Relative to gpio_chip->base */
191 struct i2c_adapter adapter;
193 unsigned char original_hstcfg;
194 struct pci_dev *pci_dev;
195 unsigned int features;
198 wait_queue_head_t waitq;
201 /* Command state used by isr for byte-by-byte block transactions */
208 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
210 const struct i801_mux_config *mux_drvdata;
211 struct platform_device *mux_pdev;
215 static struct pci_driver i801_driver;
217 #define FEATURE_SMBUS_PEC (1 << 0)
218 #define FEATURE_BLOCK_BUFFER (1 << 1)
219 #define FEATURE_BLOCK_PROC (1 << 2)
220 #define FEATURE_I2C_BLOCK_READ (1 << 3)
221 #define FEATURE_IRQ (1 << 4)
222 /* Not really a feature, but it's convenient to handle it as such */
223 #define FEATURE_IDF (1 << 15)
225 static const char *i801_feature_names[] = {
228 "Block process call",
233 static unsigned int disable_features;
234 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
235 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
236 "\t\t 0x01 disable SMBus PEC\n"
237 "\t\t 0x02 disable the block buffer\n"
238 "\t\t 0x08 disable the I2C block read functionality\n"
239 "\t\t 0x10 don't use interrupts ");
241 /* Make sure the SMBus host is ready to start transmitting.
242 Return 0 if it is, -EBUSY if it is not. */
243 static int i801_check_pre(struct i801_priv *priv)
247 status = inb_p(SMBHSTSTS(priv));
248 if (status & SMBHSTSTS_HOST_BUSY) {
249 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
253 status &= STATUS_FLAGS;
255 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
257 outb_p(status, SMBHSTSTS(priv));
258 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
260 dev_err(&priv->pci_dev->dev,
261 "Failed clearing status flags (%02x)\n",
271 * Convert the status register to an error code, and clear it.
272 * Note that status only contains the bits we want to clear, not the
273 * actual register value.
275 static int i801_check_post(struct i801_priv *priv, int status)
280 * If the SMBus is still busy, we give up
281 * Note: This timeout condition only happens when using polling
282 * transactions. For interrupt operation, NAK/timeout is indicated by
285 if (unlikely(status < 0)) {
286 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
287 /* try to stop the current command */
288 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
289 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
291 usleep_range(1000, 2000);
292 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
295 /* Check if it worked */
296 status = inb_p(SMBHSTSTS(priv));
297 if ((status & SMBHSTSTS_HOST_BUSY) ||
298 !(status & SMBHSTSTS_FAILED))
299 dev_err(&priv->pci_dev->dev,
300 "Failed terminating the transaction\n");
301 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
305 if (status & SMBHSTSTS_FAILED) {
307 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
309 if (status & SMBHSTSTS_DEV_ERR) {
311 dev_dbg(&priv->pci_dev->dev, "No response\n");
313 if (status & SMBHSTSTS_BUS_ERR) {
315 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
318 /* Clear status flags except BYTE_DONE, to be cleared by caller */
319 outb_p(status, SMBHSTSTS(priv));
324 /* Wait for BUSY being cleared and either INTR or an error flag being set */
325 static int i801_wait_intr(struct i801_priv *priv)
330 /* We will always wait for a fraction of a second! */
332 usleep_range(250, 500);
333 status = inb_p(SMBHSTSTS(priv));
334 } while (((status & SMBHSTSTS_HOST_BUSY) ||
335 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
336 (timeout++ < MAX_RETRIES));
338 if (timeout > MAX_RETRIES) {
339 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
342 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
345 /* Wait for either BYTE_DONE or an error flag being set */
346 static int i801_wait_byte_done(struct i801_priv *priv)
351 /* We will always wait for a fraction of a second! */
353 usleep_range(250, 500);
354 status = inb_p(SMBHSTSTS(priv));
355 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
356 (timeout++ < MAX_RETRIES));
358 if (timeout > MAX_RETRIES) {
359 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
362 return status & STATUS_ERROR_FLAGS;
365 static int i801_transaction(struct i801_priv *priv, int xact)
370 result = i801_check_pre(priv);
374 if (priv->features & FEATURE_IRQ) {
375 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
377 wait_event(priv->waitq, (status = priv->status));
379 return i801_check_post(priv, status);
382 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
383 * SMBSCMD are passed in xact */
384 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
386 status = i801_wait_intr(priv);
387 return i801_check_post(priv, status);
390 static int i801_block_transaction_by_block(struct i801_priv *priv,
391 union i2c_smbus_data *data,
392 char read_write, int hwpec)
397 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
399 /* Use 32-byte buffer to process this transaction */
400 if (read_write == I2C_SMBUS_WRITE) {
401 len = data->block[0];
402 outb_p(len, SMBHSTDAT0(priv));
403 for (i = 0; i < len; i++)
404 outb_p(data->block[i+1], SMBBLKDAT(priv));
407 status = i801_transaction(priv, I801_BLOCK_DATA |
408 (hwpec ? SMBHSTCNT_PEC_EN : 0));
412 if (read_write == I2C_SMBUS_READ) {
413 len = inb_p(SMBHSTDAT0(priv));
414 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
417 data->block[0] = len;
418 for (i = 0; i < len; i++)
419 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
424 static void i801_isr_byte_done(struct i801_priv *priv)
427 /* For SMBus block reads, length is received with first byte */
428 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
429 (priv->count == 0)) {
430 priv->len = inb_p(SMBHSTDAT0(priv));
431 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
432 dev_err(&priv->pci_dev->dev,
433 "Illegal SMBus block read size %d\n",
436 priv->len = I2C_SMBUS_BLOCK_MAX;
438 dev_dbg(&priv->pci_dev->dev,
439 "SMBus block read size is %d\n",
442 priv->data[-1] = priv->len;
446 if (priv->count < priv->len)
447 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
449 dev_dbg(&priv->pci_dev->dev,
450 "Discarding extra byte on block read\n");
452 /* Set LAST_BYTE for last byte of read transaction */
453 if (priv->count == priv->len - 1)
454 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
456 } else if (priv->count < priv->len - 1) {
457 /* Write next byte, except for IRQ after last byte */
458 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
461 /* Clear BYTE_DONE to continue with next byte */
462 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
466 * There are two kinds of interrupts:
468 * 1) i801 signals transaction completion with one of these interrupts:
470 * DEV_ERR - Invalid command, NAK or communication timeout
471 * BUS_ERR - SMI# transaction collision
472 * FAILED - transaction was canceled due to a KILL request
473 * When any of these occur, update ->status and wake up the waitq.
474 * ->status must be cleared before kicking off the next transaction.
476 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
477 * occurs for each byte of a byte-by-byte to prepare the next byte.
479 static irqreturn_t i801_isr(int irq, void *dev_id)
481 struct i801_priv *priv = dev_id;
485 /* Confirm this is our interrupt */
486 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
487 if (!(pcists & SMBPCISTS_INTS))
490 status = inb_p(SMBHSTSTS(priv));
492 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
494 if (status & SMBHSTSTS_BYTE_DONE)
495 i801_isr_byte_done(priv);
498 * Clear irq sources and report transaction result.
499 * ->status must be cleared before the next transaction is started.
501 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
503 outb_p(status, SMBHSTSTS(priv));
504 priv->status |= status;
505 wake_up(&priv->waitq);
512 * For "byte-by-byte" block transactions:
513 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
514 * I2C read uses cmd=I801_I2C_BLOCK_DATA
516 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
517 union i2c_smbus_data *data,
518 char read_write, int command,
526 result = i801_check_pre(priv);
530 len = data->block[0];
532 if (read_write == I2C_SMBUS_WRITE) {
533 outb_p(len, SMBHSTDAT0(priv));
534 outb_p(data->block[1], SMBBLKDAT(priv));
537 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
538 read_write == I2C_SMBUS_READ)
539 smbcmd = I801_I2C_BLOCK_DATA;
541 smbcmd = I801_BLOCK_DATA;
543 if (priv->features & FEATURE_IRQ) {
544 priv->is_read = (read_write == I2C_SMBUS_READ);
545 if (len == 1 && priv->is_read)
546 smbcmd |= SMBHSTCNT_LAST_BYTE;
547 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
550 priv->data = &data->block[1];
552 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
553 wait_event(priv->waitq, (status = priv->status));
555 return i801_check_post(priv, status);
558 for (i = 1; i <= len; i++) {
559 if (i == len && read_write == I2C_SMBUS_READ)
560 smbcmd |= SMBHSTCNT_LAST_BYTE;
561 outb_p(smbcmd, SMBHSTCNT(priv));
564 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
567 status = i801_wait_byte_done(priv);
571 if (i == 1 && read_write == I2C_SMBUS_READ
572 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
573 len = inb_p(SMBHSTDAT0(priv));
574 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
575 dev_err(&priv->pci_dev->dev,
576 "Illegal SMBus block read size %d\n",
579 while (inb_p(SMBHSTSTS(priv)) &
581 outb_p(SMBHSTSTS_BYTE_DONE,
583 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
586 data->block[0] = len;
589 /* Retrieve/store value in SMBBLKDAT */
590 if (read_write == I2C_SMBUS_READ)
591 data->block[i] = inb_p(SMBBLKDAT(priv));
592 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
593 outb_p(data->block[i+1], SMBBLKDAT(priv));
595 /* signals SMBBLKDAT ready */
596 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
599 status = i801_wait_intr(priv);
601 return i801_check_post(priv, status);
604 static int i801_set_block_buffer_mode(struct i801_priv *priv)
606 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
607 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
612 /* Block transaction function */
613 static int i801_block_transaction(struct i801_priv *priv,
614 union i2c_smbus_data *data, char read_write,
615 int command, int hwpec)
620 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
621 if (read_write == I2C_SMBUS_WRITE) {
622 /* set I2C_EN bit in configuration register */
623 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
624 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
625 hostc | SMBHSTCFG_I2C_EN);
626 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
627 dev_err(&priv->pci_dev->dev,
628 "I2C block read is unsupported!\n");
633 if (read_write == I2C_SMBUS_WRITE
634 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
635 if (data->block[0] < 1)
637 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
638 data->block[0] = I2C_SMBUS_BLOCK_MAX;
640 data->block[0] = 32; /* max for SMBus block reads */
643 /* Experience has shown that the block buffer can only be used for
644 SMBus (not I2C) block transactions, even though the datasheet
645 doesn't mention this limitation. */
646 if ((priv->features & FEATURE_BLOCK_BUFFER)
647 && command != I2C_SMBUS_I2C_BLOCK_DATA
648 && i801_set_block_buffer_mode(priv) == 0)
649 result = i801_block_transaction_by_block(priv, data,
652 result = i801_block_transaction_byte_by_byte(priv, data,
656 if (command == I2C_SMBUS_I2C_BLOCK_DATA
657 && read_write == I2C_SMBUS_WRITE) {
658 /* restore saved configuration register value */
659 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
664 /* Return negative errno on error. */
665 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
666 unsigned short flags, char read_write, u8 command,
667 int size, union i2c_smbus_data *data)
672 struct i801_priv *priv = i2c_get_adapdata(adap);
674 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
675 && size != I2C_SMBUS_QUICK
676 && size != I2C_SMBUS_I2C_BLOCK_DATA;
679 case I2C_SMBUS_QUICK:
680 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
685 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
687 if (read_write == I2C_SMBUS_WRITE)
688 outb_p(command, SMBHSTCMD(priv));
691 case I2C_SMBUS_BYTE_DATA:
692 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
694 outb_p(command, SMBHSTCMD(priv));
695 if (read_write == I2C_SMBUS_WRITE)
696 outb_p(data->byte, SMBHSTDAT0(priv));
697 xact = I801_BYTE_DATA;
699 case I2C_SMBUS_WORD_DATA:
700 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
702 outb_p(command, SMBHSTCMD(priv));
703 if (read_write == I2C_SMBUS_WRITE) {
704 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
705 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
707 xact = I801_WORD_DATA;
709 case I2C_SMBUS_BLOCK_DATA:
710 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
712 outb_p(command, SMBHSTCMD(priv));
715 case I2C_SMBUS_I2C_BLOCK_DATA:
716 /* NB: page 240 of ICH5 datasheet shows that the R/#W
717 * bit should be cleared here, even when reading */
718 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
719 if (read_write == I2C_SMBUS_READ) {
720 /* NB: page 240 of ICH5 datasheet also shows
721 * that DATA1 is the cmd field when reading */
722 outb_p(command, SMBHSTDAT1(priv));
724 outb_p(command, SMBHSTCMD(priv));
728 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
733 if (hwpec) /* enable/disable hardware PEC */
734 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
736 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
740 ret = i801_block_transaction(priv, data, read_write, size,
743 ret = i801_transaction(priv, xact);
745 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
746 time, so we forcibly disable it after every transaction. Turn off
747 E32B for the same reason. */
749 outb_p(inb_p(SMBAUXCTL(priv)) &
750 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
756 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
759 switch (xact & 0x7f) {
760 case I801_BYTE: /* Result put in SMBHSTDAT0 */
762 data->byte = inb_p(SMBHSTDAT0(priv));
765 data->word = inb_p(SMBHSTDAT0(priv)) +
766 (inb_p(SMBHSTDAT1(priv)) << 8);
773 static u32 i801_func(struct i2c_adapter *adapter)
775 struct i801_priv *priv = i2c_get_adapdata(adapter);
777 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
778 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
779 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
780 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
781 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
782 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
785 static const struct i2c_algorithm smbus_algorithm = {
786 .smbus_xfer = i801_access,
787 .functionality = i801_func,
790 static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
791 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
792 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
793 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
794 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
795 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
796 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
797 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
798 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
799 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
800 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
801 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
802 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
803 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
804 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
805 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
806 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
807 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
808 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
809 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
810 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
811 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
812 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
813 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
814 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
815 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
816 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
817 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
818 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
819 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
820 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
821 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
825 MODULE_DEVICE_TABLE(pci, i801_ids);
827 #if defined CONFIG_X86 && defined CONFIG_DMI
828 static unsigned char apanel_addr;
830 /* Scan the system ROM for the signature "FJKEYINF" */
831 static __init const void __iomem *bios_signature(const void __iomem *bios)
834 const unsigned char signature[] = "FJKEYINF";
836 for (offset = 0; offset < 0x10000; offset += 0x10) {
837 if (check_signature(bios + offset, signature,
838 sizeof(signature)-1))
839 return bios + offset;
844 static void __init input_apanel_init(void)
847 const void __iomem *p;
849 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
850 p = bios_signature(bios);
852 /* just use the first address */
853 apanel_addr = readb(p + 8 + 3) >> 1;
858 struct dmi_onboard_device_info {
861 unsigned short i2c_addr;
862 const char *i2c_type;
865 static const struct dmi_onboard_device_info dmi_devices[] = {
866 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
867 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
868 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
871 static void dmi_check_onboard_device(u8 type, const char *name,
872 struct i2c_adapter *adap)
875 struct i2c_board_info info;
877 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
878 /* & ~0x80, ignore enabled/disabled bit */
879 if ((type & ~0x80) != dmi_devices[i].type)
881 if (strcasecmp(name, dmi_devices[i].name))
884 memset(&info, 0, sizeof(struct i2c_board_info));
885 info.addr = dmi_devices[i].i2c_addr;
886 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
887 i2c_new_device(adap, &info);
892 /* We use our own function to check for onboard devices instead of
893 dmi_find_device() as some buggy BIOS's have the devices we are interested
894 in marked as disabled */
895 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
902 count = (dm->length - sizeof(struct dmi_header)) / 2;
903 for (i = 0; i < count; i++) {
904 const u8 *d = (char *)(dm + 1) + (i * 2);
905 const char *name = ((char *) dm) + dm->length;
912 while (s > 0 && name[0]) {
913 name += strlen(name) + 1;
916 if (name[0] == 0) /* Bogus string reference */
919 dmi_check_onboard_device(type, name, adap);
923 /* Register optional slaves */
924 static void i801_probe_optional_slaves(struct i801_priv *priv)
926 /* Only register slaves on main SMBus channel */
927 if (priv->features & FEATURE_IDF)
931 struct i2c_board_info info;
933 memset(&info, 0, sizeof(struct i2c_board_info));
934 info.addr = apanel_addr;
935 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
936 i2c_new_device(&priv->adapter, &info);
939 if (dmi_name_in_vendors("FUJITSU"))
940 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
943 static void __init input_apanel_init(void) {}
944 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
945 #endif /* CONFIG_X86 && CONFIG_DMI */
947 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
949 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
950 .gpio_chip = "gpio_ich",
951 .values = { 0x02, 0x03 },
953 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
958 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
959 .gpio_chip = "gpio_ich",
960 .values = { 0x02, 0x03, 0x01 },
962 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
967 static const struct dmi_system_id mux_dmi_table[] = {
970 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
971 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
973 .driver_data = &i801_mux_config_asus_z8_d12,
977 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
978 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
980 .driver_data = &i801_mux_config_asus_z8_d12,
984 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
985 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
987 .driver_data = &i801_mux_config_asus_z8_d12,
991 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
992 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
994 .driver_data = &i801_mux_config_asus_z8_d12,
998 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
999 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1001 .driver_data = &i801_mux_config_asus_z8_d12,
1005 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1006 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1008 .driver_data = &i801_mux_config_asus_z8_d12,
1012 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1013 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1015 .driver_data = &i801_mux_config_asus_z8_d18,
1019 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1020 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1022 .driver_data = &i801_mux_config_asus_z8_d18,
1026 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1027 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1029 .driver_data = &i801_mux_config_asus_z8_d12,
1034 /* Setup multiplexing if needed */
1035 static int i801_add_mux(struct i801_priv *priv)
1037 struct device *dev = &priv->adapter.dev;
1038 const struct i801_mux_config *mux_config;
1039 struct i2c_mux_gpio_platform_data gpio_data;
1042 if (!priv->mux_drvdata)
1044 mux_config = priv->mux_drvdata;
1046 /* Prepare the platform data */
1047 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1048 gpio_data.parent = priv->adapter.nr;
1049 gpio_data.values = mux_config->values;
1050 gpio_data.n_values = mux_config->n_values;
1051 gpio_data.classes = mux_config->classes;
1052 gpio_data.gpio_chip = mux_config->gpio_chip;
1053 gpio_data.gpios = mux_config->gpios;
1054 gpio_data.n_gpios = mux_config->n_gpios;
1055 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1057 /* Register the mux device */
1058 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1059 PLATFORM_DEVID_AUTO, &gpio_data,
1060 sizeof(struct i2c_mux_gpio_platform_data));
1061 if (IS_ERR(priv->mux_pdev)) {
1062 err = PTR_ERR(priv->mux_pdev);
1063 priv->mux_pdev = NULL;
1064 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1071 static void i801_del_mux(struct i801_priv *priv)
1074 platform_device_unregister(priv->mux_pdev);
1077 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1079 const struct dmi_system_id *id;
1080 const struct i801_mux_config *mux_config;
1081 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1084 id = dmi_first_match(mux_dmi_table);
1086 /* Remove branch classes from trunk */
1087 mux_config = id->driver_data;
1088 for (i = 0; i < mux_config->n_values; i++)
1089 class &= ~mux_config->classes[i];
1091 /* Remember for later */
1092 priv->mux_drvdata = mux_config;
1098 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1099 static inline void i801_del_mux(struct i801_priv *priv) { }
1101 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1103 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1107 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1111 struct i801_priv *priv;
1113 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1117 i2c_set_adapdata(&priv->adapter, priv);
1118 priv->adapter.owner = THIS_MODULE;
1119 priv->adapter.class = i801_get_adapter_class(priv);
1120 priv->adapter.algo = &smbus_algorithm;
1122 priv->pci_dev = dev;
1123 switch (dev->device) {
1124 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1125 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1126 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1127 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1128 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1129 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1130 priv->features |= FEATURE_IDF;
1133 priv->features |= FEATURE_I2C_BLOCK_READ;
1134 priv->features |= FEATURE_IRQ;
1136 case PCI_DEVICE_ID_INTEL_82801DB_3:
1137 priv->features |= FEATURE_SMBUS_PEC;
1138 priv->features |= FEATURE_BLOCK_BUFFER;
1140 case PCI_DEVICE_ID_INTEL_82801CA_3:
1141 case PCI_DEVICE_ID_INTEL_82801BA_2:
1142 case PCI_DEVICE_ID_INTEL_82801AB_3:
1143 case PCI_DEVICE_ID_INTEL_82801AA_3:
1147 /* Disable features on user request */
1148 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1149 if (priv->features & disable_features & (1 << i))
1150 dev_notice(&dev->dev, "%s disabled by user\n",
1151 i801_feature_names[i]);
1153 priv->features &= ~disable_features;
1155 err = pci_enable_device(dev);
1157 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1162 /* Determine the address of the SMBus area */
1163 priv->smba = pci_resource_start(dev, SMBBAR);
1165 dev_err(&dev->dev, "SMBus base address uninitialized, "
1171 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1177 err = pci_request_region(dev, SMBBAR, i801_driver.name);
1179 dev_err(&dev->dev, "Failed to request SMBus region "
1180 "0x%lx-0x%Lx\n", priv->smba,
1181 (unsigned long long)pci_resource_end(dev, SMBBAR));
1185 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1186 priv->original_hstcfg = temp;
1187 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1188 if (!(temp & SMBHSTCFG_HST_EN)) {
1189 dev_info(&dev->dev, "Enabling SMBus device\n");
1190 temp |= SMBHSTCFG_HST_EN;
1192 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1194 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1195 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1196 /* Disable SMBus interrupt feature if SMBus using SMI# */
1197 priv->features &= ~FEATURE_IRQ;
1200 /* Clear special mode bits */
1201 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1202 outb_p(inb_p(SMBAUXCTL(priv)) &
1203 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1205 if (priv->features & FEATURE_IRQ) {
1206 init_waitqueue_head(&priv->waitq);
1208 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
1209 i801_driver.name, priv);
1211 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1215 dev_info(&dev->dev, "SMBus using PCI Interrupt\n");
1218 /* set up the sysfs linkage to our parent device */
1219 priv->adapter.dev.parent = &dev->dev;
1221 /* Retry up to 3 times on lost arbitration */
1222 priv->adapter.retries = 3;
1224 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1225 "SMBus I801 adapter at %04lx", priv->smba);
1226 err = i2c_add_adapter(&priv->adapter);
1228 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1232 i801_probe_optional_slaves(priv);
1233 /* We ignore errors - multiplexing is optional */
1236 pci_set_drvdata(dev, priv);
1241 if (priv->features & FEATURE_IRQ)
1242 free_irq(dev->irq, priv);
1244 pci_release_region(dev, SMBBAR);
1250 static void i801_remove(struct pci_dev *dev)
1252 struct i801_priv *priv = pci_get_drvdata(dev);
1255 i2c_del_adapter(&priv->adapter);
1256 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1258 if (priv->features & FEATURE_IRQ)
1259 free_irq(dev->irq, priv);
1260 pci_release_region(dev, SMBBAR);
1264 * do not call pci_disable_device(dev) since it can cause hard hangs on
1265 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1270 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1272 struct i801_priv *priv = pci_get_drvdata(dev);
1274 pci_save_state(dev);
1275 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1276 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1280 static int i801_resume(struct pci_dev *dev)
1282 pci_set_power_state(dev, PCI_D0);
1283 pci_restore_state(dev);
1284 return pci_enable_device(dev);
1287 #define i801_suspend NULL
1288 #define i801_resume NULL
1291 static struct pci_driver i801_driver = {
1292 .name = "i801_smbus",
1293 .id_table = i801_ids,
1294 .probe = i801_probe,
1295 .remove = i801_remove,
1296 .suspend = i801_suspend,
1297 .resume = i801_resume,
1300 static int __init i2c_i801_init(void)
1302 if (dmi_name_in_vendors("FUJITSU"))
1303 input_apanel_init();
1304 return pci_register_driver(&i801_driver);
1307 static void __exit i2c_i801_exit(void)
1309 pci_unregister_driver(&i801_driver);
1312 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
1313 "Jean Delvare <khali@linux-fr.org>");
1314 MODULE_DESCRIPTION("I801 SMBus driver");
1315 MODULE_LICENSE("GPL");
1317 module_init(i2c_i801_init);
1318 module_exit(i2c_i801_exit);