drivers/i2c/busses/i2c-i801.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   4     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   5     <mdsxyz123@yahoo.com>
   6     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   7     Copyright (C) 2010         Intel Corporation,
   8                                David Woodhouse <dwmw2@infradead.org>
   9
  10 */
  11
  12 /*
  13  * Supports the following Intel I/O Controller Hubs (ICH):
  14  *
  15  *                                      I/O                     Block   I2C
  16  *                                      region  SMBus   Block   proc.   block
  17  * Chip name                    PCI ID  size    PEC     buffer  call    read
  18  * ---------------------------------------------------------------------------
  19  * 82801AA (ICH)                0x2413  16      no      no      no      no
  20  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  21  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  22  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  23  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  24  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  25  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  26  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  27  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  28  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  29  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  30  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  31  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  32  * ICH10                        0x3a30  32      hard    yes     yes     yes
  33  * ICH10                        0x3a60  32      hard    yes     yes     yes
  34  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  35  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  36  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  37  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  38  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  39  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  40  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  41  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  42  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  43  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  44  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  45  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  46  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  47  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  48  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  49  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  50  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  51  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  52  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  53  * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  54  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  55  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  56  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  57  * Emmitsburg (PCH)             0x1bc9  32      hard    yes     yes     yes
  58  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  59  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  60  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  61  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  62  * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  63  * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  64  * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  65  * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  66  * Ice Lake-LP (PCH)            0x34a3  32      hard    yes     yes     yes
  67  * Ice Lake-N (PCH)             0x38a3  32      hard    yes     yes     yes
  68  * Comet Lake (PCH)             0x02a3  32      hard    yes     yes     yes
  69  * Comet Lake-H (PCH)           0x06a3  32      hard    yes     yes     yes
  70  * Elkhart Lake (PCH)           0x4b23  32      hard    yes     yes     yes
  71  * Tiger Lake-LP (PCH)          0xa0a3  32      hard    yes     yes     yes
  72  * Tiger Lake-H (PCH)           0x43a3  32      hard    yes     yes     yes
  73  * Jasper Lake (SOC)            0x4da3  32      hard    yes     yes     yes
  74  * Comet Lake-V (PCH)           0xa3a3  32      hard    yes     yes     yes
  75  * Alder Lake-S (PCH)           0x7aa3  32      hard    yes     yes     yes
  76  * Alder Lake-P (PCH)           0x51a3  32      hard    yes     yes     yes
  77  * Alder Lake-M (PCH)           0x54a3  32      hard    yes     yes     yes
  78  * Raptor Lake-S (PCH)          0x7a23  32      hard    yes     yes     yes
  79  * Meteor Lake-P (SOC)          0x7e22  32      hard    yes     yes     yes
  80  *
  81  * Features supported by this driver:
  82  * Software PEC                         no
  83  * Hardware PEC                         yes
  84  * Block buffer                         yes
  85  * Block process call transaction       yes
  86  * I2C block read transaction           yes (doesn't use the block buffer)
  87  * Slave mode                           no
  88  * SMBus Host Notify                    yes
  89  * Interrupt processing                 yes
  90  *
  91  * See the file Documentation/i2c/busses/i2c-i801.rst for details.
  92  */
  93
  94 #define DRV_NAME        "i801_smbus"
  95
  96 #include <linux/interrupt.h>
  97 #include <linux/module.h>
  98 #include <linux/pci.h>
  99 #include <linux/kernel.h>
 100 #include <linux/stddef.h>
 101 #include <linux/delay.h>
 102 #include <linux/ioport.h>
 103 #include <linux/init.h>
 104 #include <linux/i2c.h>
 105 #include <linux/i2c-smbus.h>
 106 #include <linux/acpi.h>
 107 #include <linux/io.h>
 108 #include <linux/dmi.h>
 109 #include <linux/slab.h>
 110 #include <linux/string.h>
 111 #include <linux/completion.h>
 112 #include <linux/err.h>
 113 #include <linux/platform_device.h>
 114 #include <linux/platform_data/itco_wdt.h>
 115 #include <linux/platform_data/x86/p2sb.h>
 116 #include <linux/pm_runtime.h>
 117 #include <linux/mutex.h>
 118
 119 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 120 #include <linux/gpio/machine.h>
 121 #include <linux/platform_data/i2c-mux-gpio.h>
 122 #endif
 123
 124 /* I801 SMBus address offsets */
 125 #define SMBHSTSTS(p)    (0 + (p)->smba)
 126 #define SMBHSTCNT(p)    (2 + (p)->smba)
 127 #define SMBHSTCMD(p)    (3 + (p)->smba)
 128 #define SMBHSTADD(p)    (4 + (p)->smba)
 129 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 130 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 131 #define SMBBLKDAT(p)    (7 + (p)->smba)
 132 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 133 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 134 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 135 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 136 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 137 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 138
 139 /* PCI Address Constants */
 140 #define SMBBAR          4
 141 #define SMBHSTCFG       0x040
 142 #define TCOBASE         0x050
 143 #define TCOCTL          0x054
 144
 145 #define SBREG_SMBCTRL           0xc6000c
 146 #define SBREG_SMBCTRL_DNV       0xcf000c
 147
 148 /* Host configuration bits for SMBHSTCFG */
 149 #define SMBHSTCFG_HST_EN        BIT(0)
 150 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 151 #define SMBHSTCFG_I2C_EN        BIT(2)
 152 #define SMBHSTCFG_SPD_WD        BIT(4)
 153
 154 /* TCO configuration bits for TCOCTL */
 155 #define TCOCTL_EN               BIT(8)
 156
 157 /* Auxiliary status register bits, ICH4+ only */
 158 #define SMBAUXSTS_CRCE          BIT(0)
 159 #define SMBAUXSTS_STCO          BIT(1)
 160
 161 /* Auxiliary control register bits, ICH4+ only */
 162 #define SMBAUXCTL_CRC           BIT(0)
 163 #define SMBAUXCTL_E32B          BIT(1)
 164
 165 /* I801 command constants */
 166 #define I801_QUICK              0x00
 167 #define I801_BYTE               0x04
 168 #define I801_BYTE_DATA          0x08
 169 #define I801_WORD_DATA          0x0C
 170 #define I801_PROC_CALL          0x10
 171 #define I801_BLOCK_DATA         0x14
 172 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 173 #define I801_BLOCK_PROC_CALL    0x1C
 174
 175 /* I801 Host Control register bits */
 176 #define SMBHSTCNT_INTREN        BIT(0)
 177 #define SMBHSTCNT_KILL          BIT(1)
 178 #define SMBHSTCNT_LAST_BYTE     BIT(5)
 179 #define SMBHSTCNT_START         BIT(6)
 180 #define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 181
 182 /* I801 Hosts Status register bits */
 183 #define SMBHSTSTS_BYTE_DONE     BIT(7)
 184 #define SMBHSTSTS_INUSE_STS     BIT(6)
 185 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
 186 #define SMBHSTSTS_FAILED        BIT(4)
 187 #define SMBHSTSTS_BUS_ERR       BIT(3)
 188 #define SMBHSTSTS_DEV_ERR       BIT(2)
 189 #define SMBHSTSTS_INTR          BIT(1)
 190 #define SMBHSTSTS_HOST_BUSY     BIT(0)
 191
 192 /* Host Notify Status register bits */
 193 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 194
 195 /* Host Notify Command register bits */
 196 #define SMBSLVCMD_SMBALERT_DISABLE      BIT(2)
 197 #define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 198
 199 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 200                                  SMBHSTSTS_DEV_ERR)
 201
 202 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 203                                  STATUS_ERROR_FLAGS)
 204
 205 /* Older devices have their ID defined in <linux/pci_ids.h> */
 206 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS             0x02a3
 207 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS           0x06a3
 208 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 209 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 210 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 211 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS                   0x1bc9
 212 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 214 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 218 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 219 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 220 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 221 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 222 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 223 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 224 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS            0x34a3
 225 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS             0x38a3
 226 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 227 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS           0x43a3
 228 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS          0x4b23
 229 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS           0x4da3
 230 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS          0x51a3
 231 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS          0x54a3
 232 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 233 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS         0x7a23
 234 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS          0x7aa3
 235 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS         0x7e22
 236 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 237 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 238 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 239 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 240 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 241 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 242 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 243 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 244 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 245 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 246 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS          0xa0a3
 247 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 248 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 249 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 250 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 251 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 252 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS           0xa3a3
 253
 254 struct i801_mux_config {
 255         char *gpio_chip;
 256         unsigned values[3];
 257         int n_values;
 258         unsigned classes[3];
 259         unsigned gpios[2];              /* Relative to gpio_chip->base */
 260         int n_gpios;
 261 };
 262
 263 struct i801_priv {
 264         struct i2c_adapter adapter;
 265         unsigned long smba;
 266         unsigned char original_hstcfg;
 267         unsigned char original_hstcnt;
 268         unsigned char original_slvcmd;
 269         struct pci_dev *pci_dev;
 270         unsigned int features;
 271
 272         /* isr processing */
 273         struct completion done;
 274         u8 status;
 275
 276         /* Command state used by isr for byte-by-byte block transactions */
 277         u8 cmd;
 278         bool is_read;
 279         int count;
 280         int len;
 281         u8 *data;
 282
 283 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 284         const struct i801_mux_config *mux_drvdata;
 285         struct platform_device *mux_pdev;
 286         struct gpiod_lookup_table *lookup;
 287 #endif
 288         struct platform_device *tco_pdev;
 289
 290         /*
 291          * If set to true the host controller registers are reserved for
 292          * ACPI AML use. Protected by acpi_lock.
 293          */
 294         bool acpi_reserved;
 295         struct mutex acpi_lock;
 296 };
 297
 298 #define FEATURE_SMBUS_PEC       BIT(0)
 299 #define FEATURE_BLOCK_BUFFER    BIT(1)
 300 #define FEATURE_BLOCK_PROC      BIT(2)
 301 #define FEATURE_I2C_BLOCK_READ  BIT(3)
 302 #define FEATURE_IRQ             BIT(4)
 303 #define FEATURE_HOST_NOTIFY     BIT(5)
 304 /* Not really a feature, but it's convenient to handle it as such */
 305 #define FEATURE_IDF             BIT(15)
 306 #define FEATURE_TCO_SPT         BIT(16)
 307 #define FEATURE_TCO_CNL         BIT(17)
 308
 309 static const char *i801_feature_names[] = {
 310         "SMBus PEC",
 311         "Block buffer",
 312         "Block process call",
 313         "I2C block read",
 314         "Interrupt",
 315         "SMBus Host Notify",
 316 };
 317
 318 static unsigned int disable_features;
 319 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 320 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 321         "\t\t  0x01  disable SMBus PEC\n"
 322         "\t\t  0x02  disable the block buffer\n"
 323         "\t\t  0x08  disable the I2C block read functionality\n"
 324         "\t\t  0x10  don't use interrupts\n"
 325         "\t\t  0x20  disable SMBus Host Notify ");
 326
 327 /* Make sure the SMBus host is ready to start transmitting.
 328    Return 0 if it is, -EBUSY if it is not. */
 329 static int i801_check_pre(struct i801_priv *priv)
 330 {
 331         int status;
 332
 333         status = inb_p(SMBHSTSTS(priv));
 334         if (status & SMBHSTSTS_HOST_BUSY) {
 335                 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n");
 336                 return -EBUSY;
 337         }
 338
 339         status &= STATUS_FLAGS;
 340         if (status) {
 341                 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status);
 342                 outb_p(status, SMBHSTSTS(priv));
 343         }
 344
 345         /*
 346          * Clear CRC status if needed.
 347          * During normal operation, i801_check_post() takes care
 348          * of it after every operation.  We do it here only in case
 349          * the hardware was already in this state when the driver
 350          * started.
 351          */
 352         if (priv->features & FEATURE_SMBUS_PEC) {
 353                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 354                 if (status) {
 355                         pci_dbg(priv->pci_dev, "Clearing aux status flags (%02x)\n", status);
 356                         outb_p(status, SMBAUXSTS(priv));
 357                 }
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int i801_check_post(struct i801_priv *priv, int status)
 364 {
 365         int result = 0;
 366
 367         /*
 368          * If the SMBus is still busy, we give up
 369          */
 370         if (unlikely(status < 0)) {
 371                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 372                 /* try to stop the current command */
 373                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 374                 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
 375                 usleep_range(1000, 2000);
 376                 outb_p(0, SMBHSTCNT(priv));
 377
 378                 /* Check if it worked */
 379                 status = inb_p(SMBHSTSTS(priv));
 380                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 381                     !(status & SMBHSTSTS_FAILED))
 382                         dev_err(&priv->pci_dev->dev,
 383                                 "Failed terminating the transaction\n");
 384                 return -ETIMEDOUT;
 385         }
 386
 387         if (status & SMBHSTSTS_FAILED) {
 388                 result = -EIO;
 389                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 390         }
 391         if (status & SMBHSTSTS_DEV_ERR) {
 392                 /*
 393                  * This may be a PEC error, check and clear it.
 394                  *
 395                  * AUXSTS is handled differently from HSTSTS.
 396                  * For HSTSTS, i801_isr() or i801_wait_intr()
 397                  * has already cleared the error bits in hardware,
 398                  * and we are passed a copy of the original value
 399                  * in "status".
 400                  * For AUXSTS, the hardware register is left
 401                  * for us to handle here.
 402                  * This is asymmetric, slightly iffy, but safe,
 403                  * since all this code is serialized and the CRCE
 404                  * bit is harmless as long as it's cleared before
 405                  * the next operation.
 406                  */
 407                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 408                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 409                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 410                         result = -EBADMSG;
 411                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 412                 } else {
 413                         result = -ENXIO;
 414                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 415                 }
 416         }
 417         if (status & SMBHSTSTS_BUS_ERR) {
 418                 result = -EAGAIN;
 419                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 420         }
 421
 422         return result;
 423 }
 424
 425 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 426 static int i801_wait_intr(struct i801_priv *priv)
 427 {
 428         unsigned long timeout = jiffies + priv->adapter.timeout;
 429         int status, busy;
 430
 431         do {
 432                 usleep_range(250, 500);
 433                 status = inb_p(SMBHSTSTS(priv));
 434                 busy = status & SMBHSTSTS_HOST_BUSY;
 435                 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
 436                 if (!busy && status)
 437                         return status;
 438         } while (time_is_after_eq_jiffies(timeout));
 439
 440         return -ETIMEDOUT;
 441 }
 442
 443 /* Wait for either BYTE_DONE or an error flag being set */
 444 static int i801_wait_byte_done(struct i801_priv *priv)
 445 {
 446         unsigned long timeout = jiffies + priv->adapter.timeout;
 447         int status;
 448
 449         do {
 450                 usleep_range(250, 500);
 451                 status = inb_p(SMBHSTSTS(priv));
 452                 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
 453                         return status & STATUS_ERROR_FLAGS;
 454         } while (time_is_after_eq_jiffies(timeout));
 455
 456         return -ETIMEDOUT;
 457 }
 458
 459 static int i801_transaction(struct i801_priv *priv, int xact)
 460 {
 461         int status;
 462         unsigned long result;
 463         const struct i2c_adapter *adap = &priv->adapter;
 464
 465         status = i801_check_pre(priv);
 466         if (status < 0)
 467                 return status;
 468
 469         if (priv->features & FEATURE_IRQ) {
 470                 reinit_completion(&priv->done);
 471                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 472                        SMBHSTCNT(priv));
 473                 result = wait_for_completion_timeout(&priv->done, adap->timeout);
 474                 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
 475         }
 476
 477         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 478
 479         status = i801_wait_intr(priv);
 480         return i801_check_post(priv, status);
 481 }
 482
 483 static int i801_block_transaction_by_block(struct i801_priv *priv,
 484                                            union i2c_smbus_data *data,
 485                                            char read_write, int command)
 486 {
 487         int i, len, status, xact;
 488
 489         switch (command) {
 490         case I2C_SMBUS_BLOCK_PROC_CALL:
 491                 xact = I801_BLOCK_PROC_CALL;
 492                 break;
 493         case I2C_SMBUS_BLOCK_DATA:
 494                 xact = I801_BLOCK_DATA;
 495                 break;
 496         default:
 497                 return -EOPNOTSUPP;
 498         }
 499
 500         /* Set block buffer mode */
 501         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 502
 503         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 504
 505         if (read_write == I2C_SMBUS_WRITE) {
 506                 len = data->block[0];
 507                 outb_p(len, SMBHSTDAT0(priv));
 508                 for (i = 0; i < len; i++)
 509                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 510         }
 511
 512         status = i801_transaction(priv, xact);
 513         if (status)
 514                 return status;
 515
 516         if (read_write == I2C_SMBUS_READ ||
 517             command == I2C_SMBUS_BLOCK_PROC_CALL) {
 518                 len = inb_p(SMBHSTDAT0(priv));
 519                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 520                         return -EPROTO;
 521
 522                 data->block[0] = len;
 523                 for (i = 0; i < len; i++)
 524                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 525         }
 526         return 0;
 527 }
 528
 529 static void i801_isr_byte_done(struct i801_priv *priv)
 530 {
 531         if (priv->is_read) {
 532                 /* For SMBus block reads, length is received with first byte */
 533                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 534                     (priv->count == 0)) {
 535                         priv->len = inb_p(SMBHSTDAT0(priv));
 536                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 537                                 dev_err(&priv->pci_dev->dev,
 538                                         "Illegal SMBus block read size %d\n",
 539                                         priv->len);
 540                                 /* FIXME: Recover */
 541                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 542                         }
 543                         priv->data[-1] = priv->len;
 544                 }
 545
 546                 /* Read next byte */
 547                 if (priv->count < priv->len)
 548                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 549                 else
 550                         dev_dbg(&priv->pci_dev->dev,
 551                                 "Discarding extra byte on block read\n");
 552
 553                 /* Set LAST_BYTE for last byte of read transaction */
 554                 if (priv->count == priv->len - 1)
 555                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 556                                SMBHSTCNT(priv));
 557         } else if (priv->count < priv->len - 1) {
 558                 /* Write next byte, except for IRQ after last byte */
 559                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 560         }
 561 }
 562
 563 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 564 {
 565         unsigned short addr;
 566
 567         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 568
 569         /*
 570          * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 571          * always returns 0. Our current implementation doesn't provide
 572          * data, so we just ignore it.
 573          */
 574         i2c_handle_smbus_host_notify(&priv->adapter, addr);
 575
 576         /* clear Host Notify bit and return */
 577         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 578         return IRQ_HANDLED;
 579 }
 580
 581 /*
 582  * There are three kinds of interrupts:
 583  *
 584  * 1) i801 signals transaction completion with one of these interrupts:
 585  *      INTR - Success
 586  *      DEV_ERR - Invalid command, NAK or communication timeout
 587  *      BUS_ERR - SMI# transaction collision
 588  *      FAILED - transaction was canceled due to a KILL request
 589  *    When any of these occur, update ->status and signal completion.
 590  *
 591  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 592  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 593  *
 594  * 3) Host Notify interrupts
 595  */
 596 static irqreturn_t i801_isr(int irq, void *dev_id)
 597 {
 598         struct i801_priv *priv = dev_id;
 599         u16 pcists;
 600         u8 status;
 601
 602         /* Confirm this is our interrupt */
 603         pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
 604         if (!(pcists & PCI_STATUS_INTERRUPT))
 605                 return IRQ_NONE;
 606
 607         if (priv->features & FEATURE_HOST_NOTIFY) {
 608                 status = inb_p(SMBSLVSTS(priv));
 609                 if (status & SMBSLVSTS_HST_NTFY_STS)
 610                         return i801_host_notify_isr(priv);
 611         }
 612
 613         status = inb_p(SMBHSTSTS(priv));
 614         if ((status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS)) == SMBHSTSTS_BYTE_DONE)
 615                 i801_isr_byte_done(priv);
 616
 617         /*
 618          * Clear IRQ sources: SMB_ALERT status is set after signal assertion
 619          * independently of the interrupt generation being blocked or not
 620          * so clear it always when the status is set.
 621          */
 622         status &= STATUS_FLAGS | SMBHSTSTS_SMBALERT_STS;
 623         outb_p(status, SMBHSTSTS(priv));
 624
 625         status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
 626         if (status) {
 627                 priv->status = status;
 628                 complete(&priv->done);
 629         }
 630
 631         return IRQ_HANDLED;
 632 }
 633
 634 /*
 635  * For "byte-by-byte" block transactions:
 636  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 637  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 638  */
 639 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 640                                                union i2c_smbus_data *data,
 641                                                char read_write, int command)
 642 {
 643         int i, len;
 644         int smbcmd;
 645         int status;
 646         unsigned long result;
 647         const struct i2c_adapter *adap = &priv->adapter;
 648
 649         if (command == I2C_SMBUS_BLOCK_PROC_CALL)
 650                 return -EOPNOTSUPP;
 651
 652         status = i801_check_pre(priv);
 653         if (status < 0)
 654                 return status;
 655
 656         len = data->block[0];
 657
 658         if (read_write == I2C_SMBUS_WRITE) {
 659                 outb_p(len, SMBHSTDAT0(priv));
 660                 outb_p(data->block[1], SMBBLKDAT(priv));
 661         }
 662
 663         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 664             read_write == I2C_SMBUS_READ)
 665                 smbcmd = I801_I2C_BLOCK_DATA;
 666         else
 667                 smbcmd = I801_BLOCK_DATA;
 668
 669         if (priv->features & FEATURE_IRQ) {
 670                 priv->is_read = (read_write == I2C_SMBUS_READ);
 671                 if (len == 1 && priv->is_read)
 672                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 673                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 674                 priv->len = len;
 675                 priv->count = 0;
 676                 priv->data = &data->block[1];
 677
 678                 reinit_completion(&priv->done);
 679                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 680                 result = wait_for_completion_timeout(&priv->done, adap->timeout);
 681                 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
 682         }
 683
 684         for (i = 1; i <= len; i++) {
 685                 if (i == len && read_write == I2C_SMBUS_READ)
 686                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 687                 outb_p(smbcmd, SMBHSTCNT(priv));
 688
 689                 if (i == 1)
 690                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 691                                SMBHSTCNT(priv));
 692
 693                 status = i801_wait_byte_done(priv);
 694                 if (status)
 695                         goto exit;
 696
 697                 if (i == 1 && read_write == I2C_SMBUS_READ
 698                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 699                         len = inb_p(SMBHSTDAT0(priv));
 700                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 701                                 dev_err(&priv->pci_dev->dev,
 702                                         "Illegal SMBus block read size %d\n",
 703                                         len);
 704                                 /* Recover */
 705                                 while (inb_p(SMBHSTSTS(priv)) &
 706                                        SMBHSTSTS_HOST_BUSY)
 707                                         outb_p(SMBHSTSTS_BYTE_DONE,
 708                                                SMBHSTSTS(priv));
 709                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 710                                 return -EPROTO;
 711                         }
 712                         data->block[0] = len;
 713                 }
 714
 715                 /* Retrieve/store value in SMBBLKDAT */
 716                 if (read_write == I2C_SMBUS_READ)
 717                         data->block[i] = inb_p(SMBBLKDAT(priv));
 718                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 719                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 720
 721                 /* signals SMBBLKDAT ready */
 722                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 723         }
 724
 725         status = i801_wait_intr(priv);
 726 exit:
 727         return i801_check_post(priv, status);
 728 }
 729
 730 /* Block transaction function */
 731 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
 732                                   char read_write, int command)
 733 {
 734         int result = 0;
 735         unsigned char hostc;
 736
 737         if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
 738                 data->block[0] = I2C_SMBUS_BLOCK_MAX;
 739         else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 740                 return -EPROTO;
 741
 742         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 743                 if (read_write == I2C_SMBUS_WRITE) {
 744                         /* set I2C_EN bit in configuration register */
 745                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 746                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 747                                               hostc | SMBHSTCFG_I2C_EN);
 748                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 749                         dev_err(&priv->pci_dev->dev,
 750                                 "I2C block read is unsupported!\n");
 751                         return -EOPNOTSUPP;
 752                 }
 753         }
 754
 755         /* Experience has shown that the block buffer can only be used for
 756            SMBus (not I2C) block transactions, even though the datasheet
 757            doesn't mention this limitation. */
 758         if ((priv->features & FEATURE_BLOCK_BUFFER) &&
 759             command != I2C_SMBUS_I2C_BLOCK_DATA)
 760                 result = i801_block_transaction_by_block(priv, data,
 761                                                          read_write,
 762                                                          command);
 763         else
 764                 result = i801_block_transaction_byte_by_byte(priv, data,
 765                                                              read_write,
 766                                                              command);
 767
 768         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 769          && read_write == I2C_SMBUS_WRITE) {
 770                 /* restore saved configuration register value */
 771                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 772         }
 773         return result;
 774 }
 775
 776 /* Return negative errno on error. */
 777 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 778                        unsigned short flags, char read_write, u8 command,
 779                        int size, union i2c_smbus_data *data)
 780 {
 781         int hwpec;
 782         int block = 0;
 783         int ret, xact;
 784         struct i801_priv *priv = i2c_get_adapdata(adap);
 785
 786         mutex_lock(&priv->acpi_lock);
 787         if (priv->acpi_reserved) {
 788                 mutex_unlock(&priv->acpi_lock);
 789                 return -EBUSY;
 790         }
 791
 792         pm_runtime_get_sync(&priv->pci_dev->dev);
 793
 794         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 795                 && size != I2C_SMBUS_QUICK
 796                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 797
 798         switch (size) {
 799         case I2C_SMBUS_QUICK:
 800                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 801                        SMBHSTADD(priv));
 802                 xact = I801_QUICK;
 803                 break;
 804         case I2C_SMBUS_BYTE:
 805                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 806                        SMBHSTADD(priv));
 807                 if (read_write == I2C_SMBUS_WRITE)
 808                         outb_p(command, SMBHSTCMD(priv));
 809                 xact = I801_BYTE;
 810                 break;
 811         case I2C_SMBUS_BYTE_DATA:
 812                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 813                        SMBHSTADD(priv));
 814                 outb_p(command, SMBHSTCMD(priv));
 815                 if (read_write == I2C_SMBUS_WRITE)
 816                         outb_p(data->byte, SMBHSTDAT0(priv));
 817                 xact = I801_BYTE_DATA;
 818                 break;
 819         case I2C_SMBUS_WORD_DATA:
 820                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 821                        SMBHSTADD(priv));
 822                 outb_p(command, SMBHSTCMD(priv));
 823                 if (read_write == I2C_SMBUS_WRITE) {
 824                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 825                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 826                 }
 827                 xact = I801_WORD_DATA;
 828                 break;
 829         case I2C_SMBUS_PROC_CALL:
 830                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 831                 outb_p(command, SMBHSTCMD(priv));
 832                 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 833                 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 834                 xact = I801_PROC_CALL;
 835                 read_write = I2C_SMBUS_READ;
 836                 break;
 837         case I2C_SMBUS_BLOCK_DATA:
 838                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 839                        SMBHSTADD(priv));
 840                 outb_p(command, SMBHSTCMD(priv));
 841                 block = 1;
 842                 break;
 843         case I2C_SMBUS_I2C_BLOCK_DATA:
 844                 /*
 845                  * NB: page 240 of ICH5 datasheet shows that the R/#W
 846                  * bit should be cleared here, even when reading.
 847                  * However if SPD Write Disable is set (Lynx Point and later),
 848                  * the read will fail if we don't set the R/#W bit.
 849                  */
 850                 outb_p(((addr & 0x7f) << 1) |
 851                        ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
 852                         (read_write & 0x01) : 0),
 853                        SMBHSTADD(priv));
 854                 if (read_write == I2C_SMBUS_READ) {
 855                         /* NB: page 240 of ICH5 datasheet also shows
 856                          * that DATA1 is the cmd field when reading */
 857                         outb_p(command, SMBHSTDAT1(priv));
 858                 } else
 859                         outb_p(command, SMBHSTCMD(priv));
 860                 block = 1;
 861                 break;
 862         case I2C_SMBUS_BLOCK_PROC_CALL:
 863                 /*
 864                  * Bit 0 of the slave address register always indicate a write
 865                  * command.
 866                  */
 867                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 868                 outb_p(command, SMBHSTCMD(priv));
 869                 block = 1;
 870                 break;
 871         default:
 872                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 873                         size);
 874                 ret = -EOPNOTSUPP;
 875                 goto out;
 876         }
 877
 878         if (hwpec)      /* enable/disable hardware PEC */
 879                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 880         else
 881                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 882                        SMBAUXCTL(priv));
 883
 884         if (block)
 885                 ret = i801_block_transaction(priv, data, read_write, size);
 886         else
 887                 ret = i801_transaction(priv, xact);
 888
 889         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 890            time, so we forcibly disable it after every transaction. Turn off
 891            E32B for the same reason. */
 892         if (hwpec || block)
 893                 outb_p(inb_p(SMBAUXCTL(priv)) &
 894                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 895
 896         if (block)
 897                 goto out;
 898         if (ret)
 899                 goto out;
 900         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 901                 goto out;
 902
 903         switch (xact) {
 904         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 905         case I801_BYTE_DATA:
 906                 data->byte = inb_p(SMBHSTDAT0(priv));
 907                 break;
 908         case I801_WORD_DATA:
 909         case I801_PROC_CALL:
 910                 data->word = inb_p(SMBHSTDAT0(priv)) +
 911                              (inb_p(SMBHSTDAT1(priv)) << 8);
 912                 break;
 913         }
 914
 915 out:
 916         /*
 917          * Unlock the SMBus device for use by BIOS/ACPI,
 918          * and clear status flags if not done already.
 919          */
 920         outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv));
 921
 922         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 923         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 924         mutex_unlock(&priv->acpi_lock);
 925         return ret;
 926 }
 927
 928
 929 static u32 i801_func(struct i2c_adapter *adapter)
 930 {
 931         struct i801_priv *priv = i2c_get_adapdata(adapter);
 932
 933         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 934                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 935                I2C_FUNC_SMBUS_PROC_CALL |
 936                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 937                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 938                ((priv->features & FEATURE_BLOCK_PROC) ?
 939                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
 940                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 941                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 942                ((priv->features & FEATURE_HOST_NOTIFY) ?
 943                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 944 }
 945
 946 static void i801_enable_host_notify(struct i2c_adapter *adapter)
 947 {
 948         struct i801_priv *priv = i2c_get_adapdata(adapter);
 949
 950         if (!(priv->features & FEATURE_HOST_NOTIFY))
 951                 return;
 952
 953         /*
 954          * Enable host notify interrupt and block the generation of interrupt
 955          * from the SMB_ALERT signal because the driver does not support
 956          * SMBus Alert.
 957          */
 958         outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE |
 959                priv->original_slvcmd, SMBSLVCMD(priv));
 960
 961         /* clear Host Notify bit to allow a new notification */
 962         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 963 }
 964
 965 static void i801_disable_host_notify(struct i801_priv *priv)
 966 {
 967         if (!(priv->features & FEATURE_HOST_NOTIFY))
 968                 return;
 969
 970         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
 971 }
 972
 973 static const struct i2c_algorithm smbus_algorithm = {
 974         .smbus_xfer     = i801_access,
 975         .functionality  = i801_func,
 976 };
 977
 978 #define FEATURES_ICH5   (FEATURE_BLOCK_PROC | FEATURE_I2C_BLOCK_READ    | \
 979                          FEATURE_IRQ | FEATURE_SMBUS_PEC                | \
 980                          FEATURE_BLOCK_BUFFER | FEATURE_HOST_NOTIFY)
 981 #define FEATURES_ICH4   (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \
 982                          FEATURE_HOST_NOTIFY)
 983
 984 static const struct pci_device_id i801_ids[] = {
 985         { PCI_DEVICE_DATA(INTEL, 82801AA_3,             0)                               },
 986         { PCI_DEVICE_DATA(INTEL, 82801AB_3,             0)                               },
 987         { PCI_DEVICE_DATA(INTEL, 82801BA_2,             0)                               },
 988         { PCI_DEVICE_DATA(INTEL, 82801CA_3,             FEATURE_HOST_NOTIFY)             },
 989         { PCI_DEVICE_DATA(INTEL, 82801DB_3,             FEATURES_ICH4)                   },
 990         { PCI_DEVICE_DATA(INTEL, 82801EB_3,             FEATURES_ICH5)                   },
 991         { PCI_DEVICE_DATA(INTEL, ESB_4,                 FEATURES_ICH5)                   },
 992         { PCI_DEVICE_DATA(INTEL, ICH6_16,               FEATURES_ICH5)                   },
 993         { PCI_DEVICE_DATA(INTEL, ICH7_17,               FEATURES_ICH5)                   },
 994         { PCI_DEVICE_DATA(INTEL, ESB2_17,               FEATURES_ICH5)                   },
 995         { PCI_DEVICE_DATA(INTEL, ICH8_5,                FEATURES_ICH5)                   },
 996         { PCI_DEVICE_DATA(INTEL, ICH9_6,                FEATURES_ICH5)                   },
 997         { PCI_DEVICE_DATA(INTEL, EP80579_1,             FEATURES_ICH5)                   },
 998         { PCI_DEVICE_DATA(INTEL, ICH10_4,               FEATURES_ICH5)                   },
 999         { PCI_DEVICE_DATA(INTEL, ICH10_5,               FEATURES_ICH5)                   },
1000         { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS,   FEATURES_ICH5)                   },
1001         { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS,     FEATURES_ICH5)                   },
1002         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS,        FEATURES_ICH5)                   },
1003         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0,   FEATURES_ICH5 | FEATURE_IDF)     },
1004         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1,   FEATURES_ICH5 | FEATURE_IDF)     },
1005         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2,   FEATURES_ICH5 | FEATURE_IDF)     },
1006         { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS,        FEATURES_ICH5)                   },
1007         { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS,    FEATURES_ICH5)                   },
1008         { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS,       FEATURES_ICH5)                   },
1009         { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS,    FEATURES_ICH5)                   },
1010         { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS,          FEATURES_ICH5)                   },
1011         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS,       FEATURES_ICH5)                   },
1012         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0,   FEATURES_ICH5 | FEATURE_IDF)     },
1013         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1,   FEATURES_ICH5 | FEATURE_IDF)     },
1014         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2,   FEATURES_ICH5 | FEATURE_IDF)     },
1015         { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS,     FEATURES_ICH5)                   },
1016         { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS,      FEATURES_ICH5)                   },
1017         { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS,    FEATURES_ICH5)                   },
1018         { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5)                   },
1019         { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS,        FEATURES_ICH5)                   },
1020         { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS,        FEATURES_ICH5)                   },
1021         { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1022         { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1023         { PCI_DEVICE_DATA(INTEL, CDF_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_CNL) },
1024         { PCI_DEVICE_DATA(INTEL, DNV_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_SPT) },
1025         { PCI_DEVICE_DATA(INTEL, EBG_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_CNL) },
1026         { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS,         FEATURES_ICH5)                   },
1027         { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_SPT) },
1028         { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1029         { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1030         { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1031         { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_CNL) },
1032         { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS,      FEATURES_ICH5 | FEATURE_TCO_CNL) },
1033         { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_CNL) },
1034         { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_CNL) },
1035         { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1036         { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_SPT) },
1037         { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1038         { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1039         { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1040         { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1041         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1042         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1043         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1044         { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_CNL) },
1045         { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_CNL) },
1046         { 0, }
1047 };
1048
1049 MODULE_DEVICE_TABLE(pci, i801_ids);
1050
1051 #if defined CONFIG_X86 && defined CONFIG_DMI
1052 static unsigned char apanel_addr;
1053
1054 /* Scan the system ROM for the signature "FJKEYINF" */
1055 static __init const void __iomem *bios_signature(const void __iomem *bios)
1056 {
1057         ssize_t offset;
1058         const unsigned char signature[] = "FJKEYINF";
1059
1060         for (offset = 0; offset < 0x10000; offset += 0x10) {
1061                 if (check_signature(bios + offset, signature,
1062                                     sizeof(signature)-1))
1063                         return bios + offset;
1064         }
1065         return NULL;
1066 }
1067
1068 static void __init input_apanel_init(void)
1069 {
1070         void __iomem *bios;
1071         const void __iomem *p;
1072
1073         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1074         p = bios_signature(bios);
1075         if (p) {
1076                 /* just use the first address */
1077                 apanel_addr = readb(p + 8 + 3) >> 1;
1078         }
1079         iounmap(bios);
1080 }
1081
1082 struct dmi_onboard_device_info {
1083         const char *name;
1084         u8 type;
1085         unsigned short i2c_addr;
1086         const char *i2c_type;
1087 };
1088
1089 static const struct dmi_onboard_device_info dmi_devices[] = {
1090         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1091         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1092         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1093 };
1094
1095 static void dmi_check_onboard_device(u8 type, const char *name,
1096                                      struct i2c_adapter *adap)
1097 {
1098         int i;
1099         struct i2c_board_info info;
1100
1101         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1102                 /* & ~0x80, ignore enabled/disabled bit */
1103                 if ((type & ~0x80) != dmi_devices[i].type)
1104                         continue;
1105                 if (strcasecmp(name, dmi_devices[i].name))
1106                         continue;
1107
1108                 memset(&info, 0, sizeof(struct i2c_board_info));
1109                 info.addr = dmi_devices[i].i2c_addr;
1110                 strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1111                 i2c_new_client_device(adap, &info);
1112                 break;
1113         }
1114 }
1115
1116 /* We use our own function to check for onboard devices instead of
1117    dmi_find_device() as some buggy BIOS's have the devices we are interested
1118    in marked as disabled */
1119 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1120 {
1121         int i, count;
1122
1123         if (dm->type != 10)
1124                 return;
1125
1126         count = (dm->length - sizeof(struct dmi_header)) / 2;
1127         for (i = 0; i < count; i++) {
1128                 const u8 *d = (char *)(dm + 1) + (i * 2);
1129                 const char *name = ((char *) dm) + dm->length;
1130                 u8 type = d[0];
1131                 u8 s = d[1];
1132
1133                 if (!s)
1134                         continue;
1135                 s--;
1136                 while (s > 0 && name[0]) {
1137                         name += strlen(name) + 1;
1138                         s--;
1139                 }
1140                 if (name[0] == 0) /* Bogus string reference */
1141                         continue;
1142
1143                 dmi_check_onboard_device(type, name, adap);
1144         }
1145 }
1146
1147 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1148 static const char *const acpi_smo8800_ids[] = {
1149         "SMO8800",
1150         "SMO8801",
1151         "SMO8810",
1152         "SMO8811",
1153         "SMO8820",
1154         "SMO8821",
1155         "SMO8830",
1156         "SMO8831",
1157 };
1158
1159 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1160                                              u32 nesting_level,
1161                                              void *context,
1162                                              void **return_value)
1163 {
1164         struct acpi_device_info *info;
1165         acpi_status status;
1166         char *hid;
1167         int i;
1168
1169         status = acpi_get_object_info(obj_handle, &info);
1170         if (ACPI_FAILURE(status))
1171                 return AE_OK;
1172
1173         if (!(info->valid & ACPI_VALID_HID))
1174                 goto smo88xx_not_found;
1175
1176         hid = info->hardware_id.string;
1177         if (!hid)
1178                 goto smo88xx_not_found;
1179
1180         i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1181         if (i < 0)
1182                 goto smo88xx_not_found;
1183
1184         kfree(info);
1185
1186         *return_value = NULL;
1187         return AE_CTRL_TERMINATE;
1188
1189 smo88xx_not_found:
1190         kfree(info);
1191         return AE_OK;
1192 }
1193
1194 static bool is_dell_system_with_lis3lv02d(void)
1195 {
1196         void *err = ERR_PTR(-ENOENT);
1197
1198         if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc."))
1199                 return false;
1200
1201         /*
1202          * Check that ACPI device SMO88xx is present and is functioning.
1203          * Function acpi_get_devices() already filters all ACPI devices
1204          * which are not present or are not functioning.
1205          * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1206          * accelerometer but unfortunately ACPI does not provide any other
1207          * information (like I2C address).
1208          */
1209         acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err);
1210
1211         return !IS_ERR(err);
1212 }
1213
1214 /*
1215  * Accelerometer's I2C address is not specified in DMI nor ACPI,
1216  * so it is needed to define mapping table based on DMI product names.
1217  */
1218 static const struct {
1219         const char *dmi_product_name;
1220         unsigned short i2c_addr;
1221 } dell_lis3lv02d_devices[] = {
1222         /*
1223          * Dell platform team told us that these Latitude devices have
1224          * ST microelectronics accelerometer at I2C address 0x29.
1225          */
1226         { "Latitude E5250",     0x29 },
1227         { "Latitude E5450",     0x29 },
1228         { "Latitude E5550",     0x29 },
1229         { "Latitude E6440",     0x29 },
1230         { "Latitude E6440 ATG", 0x29 },
1231         { "Latitude E6540",     0x29 },
1232         /*
1233          * Additional individual entries were added after verification.
1234          */
1235         { "Latitude 5480",      0x29 },
1236         { "Vostro V131",        0x1d },
1237         { "Vostro 5568",        0x29 },
1238 };
1239
1240 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1241 {
1242         struct i2c_board_info info;
1243         const char *dmi_product_name;
1244         int i;
1245
1246         dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1247         for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1248                 if (strcmp(dmi_product_name,
1249                            dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1250                         break;
1251         }
1252
1253         if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1254                 dev_warn(&priv->pci_dev->dev,
1255                          "Accelerometer lis3lv02d is present on SMBus but its"
1256                          " address is unknown, skipping registration\n");
1257                 return;
1258         }
1259
1260         memset(&info, 0, sizeof(struct i2c_board_info));
1261         info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1262         strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1263         i2c_new_client_device(&priv->adapter, &info);
1264 }
1265
1266 /* Register optional slaves */
1267 static void i801_probe_optional_slaves(struct i801_priv *priv)
1268 {
1269         /* Only register slaves on main SMBus channel */
1270         if (priv->features & FEATURE_IDF)
1271                 return;
1272
1273         if (apanel_addr) {
1274                 struct i2c_board_info info = {
1275                         .addr = apanel_addr,
1276                         .type = "fujitsu_apanel",
1277                 };
1278
1279                 i2c_new_client_device(&priv->adapter, &info);
1280         }
1281
1282         if (dmi_name_in_vendors("FUJITSU"))
1283                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1284
1285         if (is_dell_system_with_lis3lv02d())
1286                 register_dell_lis3lv02d_i2c_device(priv);
1287
1288         /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1289 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1290         if (!priv->mux_drvdata)
1291 #endif
1292                 i2c_register_spd(&priv->adapter);
1293 }
1294 #else
1295 static void __init input_apanel_init(void) {}
1296 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1297 #endif  /* CONFIG_X86 && CONFIG_DMI */
1298
1299 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1300 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1301         .gpio_chip = "gpio_ich",
1302         .values = { 0x02, 0x03 },
1303         .n_values = 2,
1304         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1305         .gpios = { 52, 53 },
1306         .n_gpios = 2,
1307 };
1308
1309 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1310         .gpio_chip = "gpio_ich",
1311         .values = { 0x02, 0x03, 0x01 },
1312         .n_values = 3,
1313         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1314         .gpios = { 52, 53 },
1315         .n_gpios = 2,
1316 };
1317
1318 static const struct dmi_system_id mux_dmi_table[] = {
1319         {
1320                 .matches = {
1321                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1322                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1323                 },
1324                 .driver_data = &i801_mux_config_asus_z8_d12,
1325         },
1326         {
1327                 .matches = {
1328                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1329                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1330                 },
1331                 .driver_data = &i801_mux_config_asus_z8_d12,
1332         },
1333         {
1334                 .matches = {
1335                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1336                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1337                 },
1338                 .driver_data = &i801_mux_config_asus_z8_d12,
1339         },
1340         {
1341                 .matches = {
1342                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1343                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1344                 },
1345                 .driver_data = &i801_mux_config_asus_z8_d12,
1346         },
1347         {
1348                 .matches = {
1349                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1350                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1351                 },
1352                 .driver_data = &i801_mux_config_asus_z8_d12,
1353         },
1354         {
1355                 .matches = {
1356                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1357                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1358                 },
1359                 .driver_data = &i801_mux_config_asus_z8_d12,
1360         },
1361         {
1362                 .matches = {
1363                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1364                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1365                 },
1366                 .driver_data = &i801_mux_config_asus_z8_d18,
1367         },
1368         {
1369                 .matches = {
1370                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1371                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1372                 },
1373                 .driver_data = &i801_mux_config_asus_z8_d18,
1374         },
1375         {
1376                 .matches = {
1377                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1378                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1379                 },
1380                 .driver_data = &i801_mux_config_asus_z8_d12,
1381         },
1382         { }
1383 };
1384
1385 /* Setup multiplexing if needed */
1386 static void i801_add_mux(struct i801_priv *priv)
1387 {
1388         struct device *dev = &priv->adapter.dev;
1389         const struct i801_mux_config *mux_config;
1390         struct i2c_mux_gpio_platform_data gpio_data;
1391         struct gpiod_lookup_table *lookup;
1392         int i;
1393
1394         if (!priv->mux_drvdata)
1395                 return;
1396         mux_config = priv->mux_drvdata;
1397
1398         /* Prepare the platform data */
1399         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1400         gpio_data.parent = priv->adapter.nr;
1401         gpio_data.values = mux_config->values;
1402         gpio_data.n_values = mux_config->n_values;
1403         gpio_data.classes = mux_config->classes;
1404         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1405
1406         /* Register GPIO descriptor lookup table */
1407         lookup = devm_kzalloc(dev,
1408                               struct_size(lookup, table, mux_config->n_gpios + 1),
1409                               GFP_KERNEL);
1410         if (!lookup)
1411                 return;
1412         lookup->dev_id = "i2c-mux-gpio";
1413         for (i = 0; i < mux_config->n_gpios; i++)
1414                 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip,
1415                                                mux_config->gpios[i], "mux", 0);
1416         gpiod_add_lookup_table(lookup);
1417         priv->lookup = lookup;
1418
1419         /*
1420          * Register the mux device, we use PLATFORM_DEVID_NONE here
1421          * because since we are referring to the GPIO chip by name we are
1422          * anyways in deep trouble if there is more than one of these
1423          * devices, and there should likely only be one platform controller
1424          * hub.
1425          */
1426         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1427                                 PLATFORM_DEVID_NONE, &gpio_data,
1428                                 sizeof(struct i2c_mux_gpio_platform_data));
1429         if (IS_ERR(priv->mux_pdev)) {
1430                 gpiod_remove_lookup_table(lookup);
1431                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1432         }
1433 }
1434
1435 static void i801_del_mux(struct i801_priv *priv)
1436 {
1437         platform_device_unregister(priv->mux_pdev);
1438         gpiod_remove_lookup_table(priv->lookup);
1439 }
1440
1441 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1442 {
1443         const struct dmi_system_id *id;
1444         const struct i801_mux_config *mux_config;
1445         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1446         int i;
1447
1448         id = dmi_first_match(mux_dmi_table);
1449         if (id) {
1450                 /* Remove branch classes from trunk */
1451                 mux_config = id->driver_data;
1452                 for (i = 0; i < mux_config->n_values; i++)
1453                         class &= ~mux_config->classes[i];
1454
1455                 /* Remember for later */
1456                 priv->mux_drvdata = mux_config;
1457         }
1458
1459         return class;
1460 }
1461 #else
1462 static inline void i801_add_mux(struct i801_priv *priv) { }
1463 static inline void i801_del_mux(struct i801_priv *priv) { }
1464
1465 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1466 {
1467         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1468 }
1469 #endif
1470
1471 static struct platform_device *
1472 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1473                  struct resource *tco_res)
1474 {
1475         static const struct itco_wdt_platform_data pldata = {
1476                 .name = "Intel PCH",
1477                 .version = 4,
1478         };
1479         struct resource *res;
1480         int ret;
1481
1482         /*
1483          * We must access the NO_REBOOT bit over the Primary to Sideband
1484          * (P2SB) bridge.
1485          */
1486
1487         res = &tco_res[1];
1488         ret = p2sb_bar(pci_dev->bus, 0, res);
1489         if (ret)
1490                 return ERR_PTR(ret);
1491
1492         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1493                 res->start += SBREG_SMBCTRL_DNV;
1494         else
1495                 res->start += SBREG_SMBCTRL;
1496
1497         res->end = res->start + 3;
1498
1499         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1500                                         tco_res, 2, &pldata, sizeof(pldata));
1501 }
1502
1503 static struct platform_device *
1504 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1505                  struct resource *tco_res)
1506 {
1507         static const struct itco_wdt_platform_data pldata = {
1508                 .name = "Intel PCH",
1509                 .version = 6,
1510         };
1511
1512         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1513                                                  tco_res, 1, &pldata, sizeof(pldata));
1514 }
1515
1516 static void i801_add_tco(struct i801_priv *priv)
1517 {
1518         struct pci_dev *pci_dev = priv->pci_dev;
1519         struct resource tco_res[2], *res;
1520         u32 tco_base, tco_ctl;
1521
1522         /* If we have ACPI based watchdog use that instead */
1523         if (acpi_has_watchdog())
1524                 return;
1525
1526         if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1527                 return;
1528
1529         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1530         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1531         if (!(tco_ctl & TCOCTL_EN))
1532                 return;
1533
1534         memset(tco_res, 0, sizeof(tco_res));
1535         /*
1536          * Always populate the main iTCO IO resource here. The second entry
1537          * for NO_REBOOT MMIO is filled by the SPT specific function.
1538          */
1539         res = &tco_res[0];
1540         res->start = tco_base & ~1;
1541         res->end = res->start + 32 - 1;
1542         res->flags = IORESOURCE_IO;
1543
1544         if (priv->features & FEATURE_TCO_CNL)
1545                 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1546         else
1547                 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1548
1549         if (IS_ERR(priv->tco_pdev))
1550                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1551 }
1552
1553 #ifdef CONFIG_ACPI
1554 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1555                                       acpi_physical_address address)
1556 {
1557         return address >= priv->smba &&
1558                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1559 }
1560
1561 static acpi_status
1562 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1563                      u64 *value, void *handler_context, void *region_context)
1564 {
1565         struct i801_priv *priv = handler_context;
1566         struct pci_dev *pdev = priv->pci_dev;
1567         acpi_status status;
1568
1569         /*
1570          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1571          * further access from the driver itself. This device is now owned
1572          * by the system firmware.
1573          */
1574         mutex_lock(&priv->acpi_lock);
1575
1576         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1577                 priv->acpi_reserved = true;
1578
1579                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1580                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1581
1582                 /*
1583                  * BIOS is accessing the host controller so prevent it from
1584                  * suspending automatically from now on.
1585                  */
1586                 pm_runtime_get_sync(&pdev->dev);
1587         }
1588
1589         if ((function & ACPI_IO_MASK) == ACPI_READ)
1590                 status = acpi_os_read_port(address, (u32 *)value, bits);
1591         else
1592                 status = acpi_os_write_port(address, (u32)*value, bits);
1593
1594         mutex_unlock(&priv->acpi_lock);
1595
1596         return status;
1597 }
1598
1599 static int i801_acpi_probe(struct i801_priv *priv)
1600 {
1601         acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1602         acpi_status status;
1603
1604         status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO,
1605                                                     i801_acpi_io_handler, NULL, priv);
1606         if (ACPI_SUCCESS(status))
1607                 return 0;
1608
1609         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1610 }
1611
1612 static void i801_acpi_remove(struct i801_priv *priv)
1613 {
1614         acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1615
1616         acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1617 }
1618 #else
1619 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1620 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1621 #endif
1622
1623 static void i801_setup_hstcfg(struct i801_priv *priv)
1624 {
1625         unsigned char hstcfg = priv->original_hstcfg;
1626
1627         hstcfg &= ~SMBHSTCFG_I2C_EN;    /* SMBus timing */
1628         hstcfg |= SMBHSTCFG_HST_EN;
1629         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1630 }
1631
1632 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1633 {
1634         int err, i;
1635         struct i801_priv *priv;
1636
1637         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1638         if (!priv)
1639                 return -ENOMEM;
1640
1641         i2c_set_adapdata(&priv->adapter, priv);
1642         priv->adapter.owner = THIS_MODULE;
1643         priv->adapter.class = i801_get_adapter_class(priv);
1644         priv->adapter.algo = &smbus_algorithm;
1645         priv->adapter.dev.parent = &dev->dev;
1646         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1647         priv->adapter.retries = 3;
1648         mutex_init(&priv->acpi_lock);
1649
1650         priv->pci_dev = dev;
1651         priv->features = id->driver_data;
1652
1653         /* Disable features on user request */
1654         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1655                 if (priv->features & disable_features & (1 << i))
1656                         dev_notice(&dev->dev, "%s disabled by user\n",
1657                                    i801_feature_names[i]);
1658         }
1659         priv->features &= ~disable_features;
1660
1661         /* The block process call uses block buffer mode */
1662         if (!(priv->features & FEATURE_BLOCK_BUFFER))
1663                 priv->features &= ~FEATURE_BLOCK_PROC;
1664
1665         err = pcim_enable_device(dev);
1666         if (err) {
1667                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1668                         err);
1669                 return err;
1670         }
1671         pcim_pin_device(dev);
1672
1673         /* Determine the address of the SMBus area */
1674         priv->smba = pci_resource_start(dev, SMBBAR);
1675         if (!priv->smba) {
1676                 dev_err(&dev->dev,
1677                         "SMBus base address uninitialized, upgrade BIOS\n");
1678                 return -ENODEV;
1679         }
1680
1681         if (i801_acpi_probe(priv))
1682                 return -ENODEV;
1683
1684         err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME);
1685         if (err) {
1686                 dev_err(&dev->dev,
1687                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1688                         priv->smba,
1689                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1690                 i801_acpi_remove(priv);
1691                 return err;
1692         }
1693
1694         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1695         i801_setup_hstcfg(priv);
1696         if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1697                 dev_info(&dev->dev, "Enabling SMBus device\n");
1698
1699         if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1700                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1701                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1702                 priv->features &= ~FEATURE_IRQ;
1703         }
1704         if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1705                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1706
1707         /* Clear special mode bits */
1708         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1709                 outb_p(inb_p(SMBAUXCTL(priv)) &
1710                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1711
1712         /* Default timeout in interrupt mode: 200 ms */
1713         priv->adapter.timeout = HZ / 5;
1714
1715         if (dev->irq == IRQ_NOTCONNECTED)
1716                 priv->features &= ~FEATURE_IRQ;
1717
1718         if (priv->features & FEATURE_IRQ) {
1719                 u16 pcists;
1720
1721                 /* Complain if an interrupt is already pending */
1722                 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1723                 if (pcists & PCI_STATUS_INTERRUPT)
1724                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1725         }
1726
1727         if (priv->features & FEATURE_IRQ) {
1728                 init_completion(&priv->done);
1729
1730                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1731                                        IRQF_SHARED, DRV_NAME, priv);
1732                 if (err) {
1733                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1734                                 dev->irq, err);
1735                         priv->features &= ~FEATURE_IRQ;
1736                 }
1737         }
1738         dev_info(&dev->dev, "SMBus using %s\n",
1739                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1740
1741         /* Host notification uses an interrupt */
1742         if (!(priv->features & FEATURE_IRQ))
1743                 priv->features &= ~FEATURE_HOST_NOTIFY;
1744
1745         /* Remember original Interrupt and Host Notify settings */
1746         priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL;
1747         if (priv->features & FEATURE_HOST_NOTIFY)
1748                 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1749
1750         i801_add_tco(priv);
1751
1752         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1753                 "SMBus I801 adapter at %04lx", priv->smba);
1754         err = i2c_add_adapter(&priv->adapter);
1755         if (err) {
1756                 i801_acpi_remove(priv);
1757                 return err;
1758         }
1759
1760         i801_enable_host_notify(&priv->adapter);
1761
1762         i801_probe_optional_slaves(priv);
1763         /* We ignore errors - multiplexing is optional */
1764         i801_add_mux(priv);
1765
1766         pci_set_drvdata(dev, priv);
1767
1768         dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1769         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1770         pm_runtime_use_autosuspend(&dev->dev);
1771         pm_runtime_put_autosuspend(&dev->dev);
1772         pm_runtime_allow(&dev->dev);
1773
1774         return 0;
1775 }
1776
1777 static void i801_remove(struct pci_dev *dev)
1778 {
1779         struct i801_priv *priv = pci_get_drvdata(dev);
1780
1781         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1782         i801_disable_host_notify(priv);
1783         i801_del_mux(priv);
1784         i2c_del_adapter(&priv->adapter);
1785         i801_acpi_remove(priv);
1786         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1787
1788         platform_device_unregister(priv->tco_pdev);
1789
1790         /* if acpi_reserved is set then usage_count is incremented already */
1791         if (!priv->acpi_reserved)
1792                 pm_runtime_get_noresume(&dev->dev);
1793
1794         /*
1795          * do not call pci_disable_device(dev) since it can cause hard hangs on
1796          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1797          */
1798 }
1799
1800 static void i801_shutdown(struct pci_dev *dev)
1801 {
1802         struct i801_priv *priv = pci_get_drvdata(dev);
1803
1804         /* Restore config registers to avoid hard hang on some systems */
1805         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1806         i801_disable_host_notify(priv);
1807         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1808 }
1809
1810 #ifdef CONFIG_PM_SLEEP
1811 static int i801_suspend(struct device *dev)
1812 {
1813         struct i801_priv *priv = dev_get_drvdata(dev);
1814
1815         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1816         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1817         return 0;
1818 }
1819
1820 static int i801_resume(struct device *dev)
1821 {
1822         struct i801_priv *priv = dev_get_drvdata(dev);
1823
1824         i801_setup_hstcfg(priv);
1825         i801_enable_host_notify(&priv->adapter);
1826
1827         return 0;
1828 }
1829 #endif
1830
1831 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1832
1833 static struct pci_driver i801_driver = {
1834         .name           = DRV_NAME,
1835         .id_table       = i801_ids,
1836         .probe          = i801_probe,
1837         .remove         = i801_remove,
1838         .shutdown       = i801_shutdown,
1839         .driver         = {
1840                 .pm     = &i801_pm_ops,
1841                 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1842         },
1843 };
1844
1845 static int __init i2c_i801_init(void)
1846 {
1847         if (dmi_name_in_vendors("FUJITSU"))
1848                 input_apanel_init();
1849         return pci_register_driver(&i801_driver);
1850 }
1851
1852 static void __exit i2c_i801_exit(void)
1853 {
1854         pci_unregister_driver(&i801_driver);
1855 }
1856
1857 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1858 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1859 MODULE_DESCRIPTION("I801 SMBus driver");
1860 MODULE_LICENSE("GPL");
1861
1862 module_init(i2c_i801_init);
1863 module_exit(i2c_i801_exit);