drivers/i2c/busses/i2c-i801.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   4     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   5     <mdsxyz123@yahoo.com>
   6     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   7     Copyright (C) 2010         Intel Corporation,
   8                                David Woodhouse <dwmw2@infradead.org>
   9
  10 */
  11
  12 /*
  13  * Supports the following Intel I/O Controller Hubs (ICH):
  14  *
  15  *                                      I/O                     Block   I2C
  16  *                                      region  SMBus   Block   proc.   block
  17  * Chip name                    PCI ID  size    PEC     buffer  call    read
  18  * ---------------------------------------------------------------------------
  19  * 82801AA (ICH)                0x2413  16      no      no      no      no
  20  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  21  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  22  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  23  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  24  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  25  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  26  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  27  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  28  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  29  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  30  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  31  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  32  * ICH10                        0x3a30  32      hard    yes     yes     yes
  33  * ICH10                        0x3a60  32      hard    yes     yes     yes
  34  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  35  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  36  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  37  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  38  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  39  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  40  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  41  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  42  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  43  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  44  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  45  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  46  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  47  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  48  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  49  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  50  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  51  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  52  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  53  * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  54  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  55  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  56  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  57  * Emmitsburg (PCH)             0x1bc9  32      hard    yes     yes     yes
  58  * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  59  * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  60  * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  61  * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  62  * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  63  * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  64  * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  65  * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  66  * Ice Lake-LP (PCH)            0x34a3  32      hard    yes     yes     yes
  67  * Ice Lake-N (PCH)             0x38a3  32      hard    yes     yes     yes
  68  * Comet Lake (PCH)             0x02a3  32      hard    yes     yes     yes
  69  * Comet Lake-H (PCH)           0x06a3  32      hard    yes     yes     yes
  70  * Elkhart Lake (PCH)           0x4b23  32      hard    yes     yes     yes
  71  * Tiger Lake-LP (PCH)          0xa0a3  32      hard    yes     yes     yes
  72  * Tiger Lake-H (PCH)           0x43a3  32      hard    yes     yes     yes
  73  * Jasper Lake (SOC)            0x4da3  32      hard    yes     yes     yes
  74  * Comet Lake-V (PCH)           0xa3a3  32      hard    yes     yes     yes
  75  * Alder Lake-S (PCH)           0x7aa3  32      hard    yes     yes     yes
  76  * Alder Lake-P (PCH)           0x51a3  32      hard    yes     yes     yes
  77  * Alder Lake-M (PCH)           0x54a3  32      hard    yes     yes     yes
  78  * Raptor Lake-S (PCH)          0x7a23  32      hard    yes     yes     yes
  79  *
  80  * Features supported by this driver:
  81  * Software PEC                         no
  82  * Hardware PEC                         yes
  83  * Block buffer                         yes
  84  * Block process call transaction       yes
  85  * I2C block read transaction           yes (doesn't use the block buffer)
  86  * Slave mode                           no
  87  * SMBus Host Notify                    yes
  88  * Interrupt processing                 yes
  89  *
  90  * See the file Documentation/i2c/busses/i2c-i801.rst for details.
  91  */
  92
  93 #define DRV_NAME        "i801_smbus"
  94
  95 #include <linux/interrupt.h>
  96 #include <linux/module.h>
  97 #include <linux/pci.h>
  98 #include <linux/kernel.h>
  99 #include <linux/stddef.h>
 100 #include <linux/delay.h>
 101 #include <linux/ioport.h>
 102 #include <linux/init.h>
 103 #include <linux/i2c.h>
 104 #include <linux/i2c-smbus.h>
 105 #include <linux/acpi.h>
 106 #include <linux/io.h>
 107 #include <linux/dmi.h>
 108 #include <linux/slab.h>
 109 #include <linux/string.h>
 110 #include <linux/completion.h>
 111 #include <linux/err.h>
 112 #include <linux/platform_device.h>
 113 #include <linux/platform_data/itco_wdt.h>
 114 #include <linux/pm_runtime.h>
 115 #include <linux/mutex.h>
 116
 117 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 118 #include <linux/gpio/machine.h>
 119 #include <linux/platform_data/i2c-mux-gpio.h>
 120 #endif
 121
 122 /* I801 SMBus address offsets */
 123 #define SMBHSTSTS(p)    (0 + (p)->smba)
 124 #define SMBHSTCNT(p)    (2 + (p)->smba)
 125 #define SMBHSTCMD(p)    (3 + (p)->smba)
 126 #define SMBHSTADD(p)    (4 + (p)->smba)
 127 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 128 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 129 #define SMBBLKDAT(p)    (7 + (p)->smba)
 130 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 131 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 132 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 133 #define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 134 #define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 135 #define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 136
 137 /* PCI Address Constants */
 138 #define SMBBAR          4
 139 #define SMBHSTCFG       0x040
 140 #define TCOBASE         0x050
 141 #define TCOCTL          0x054
 142
 143 #define SBREG_BAR               0x10
 144 #define SBREG_SMBCTRL           0xc6000c
 145 #define SBREG_SMBCTRL_DNV       0xcf000c
 146
 147 /* Host configuration bits for SMBHSTCFG */
 148 #define SMBHSTCFG_HST_EN        BIT(0)
 149 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 150 #define SMBHSTCFG_I2C_EN        BIT(2)
 151 #define SMBHSTCFG_SPD_WD        BIT(4)
 152
 153 /* TCO configuration bits for TCOCTL */
 154 #define TCOCTL_EN               BIT(8)
 155
 156 /* Auxiliary status register bits, ICH4+ only */
 157 #define SMBAUXSTS_CRCE          BIT(0)
 158 #define SMBAUXSTS_STCO          BIT(1)
 159
 160 /* Auxiliary control register bits, ICH4+ only */
 161 #define SMBAUXCTL_CRC           BIT(0)
 162 #define SMBAUXCTL_E32B          BIT(1)
 163
 164 /* I801 command constants */
 165 #define I801_QUICK              0x00
 166 #define I801_BYTE               0x04
 167 #define I801_BYTE_DATA          0x08
 168 #define I801_WORD_DATA          0x0C
 169 #define I801_PROC_CALL          0x10
 170 #define I801_BLOCK_DATA         0x14
 171 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 172 #define I801_BLOCK_PROC_CALL    0x1C
 173
 174 /* I801 Host Control register bits */
 175 #define SMBHSTCNT_INTREN        BIT(0)
 176 #define SMBHSTCNT_KILL          BIT(1)
 177 #define SMBHSTCNT_LAST_BYTE     BIT(5)
 178 #define SMBHSTCNT_START         BIT(6)
 179 #define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 180
 181 /* I801 Hosts Status register bits */
 182 #define SMBHSTSTS_BYTE_DONE     BIT(7)
 183 #define SMBHSTSTS_INUSE_STS     BIT(6)
 184 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
 185 #define SMBHSTSTS_FAILED        BIT(4)
 186 #define SMBHSTSTS_BUS_ERR       BIT(3)
 187 #define SMBHSTSTS_DEV_ERR       BIT(2)
 188 #define SMBHSTSTS_INTR          BIT(1)
 189 #define SMBHSTSTS_HOST_BUSY     BIT(0)
 190
 191 /* Host Notify Status register bits */
 192 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 193
 194 /* Host Notify Command register bits */
 195 #define SMBSLVCMD_SMBALERT_DISABLE      BIT(2)
 196 #define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 197
 198 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 199                                  SMBHSTSTS_DEV_ERR)
 200
 201 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 202                                  STATUS_ERROR_FLAGS)
 203
 204 /* Older devices have their ID defined in <linux/pci_ids.h> */
 205 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS             0x02a3
 206 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS           0x06a3
 207 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 208 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 209 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 210 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS                   0x1bc9
 211 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 212 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 213 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 214 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 217 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 218 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 219 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 220 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 221 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 222 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 223 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS            0x34a3
 224 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS             0x38a3
 225 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 226 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS           0x43a3
 227 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS          0x4b23
 228 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS           0x4da3
 229 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS          0x51a3
 230 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS          0x54a3
 231 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 232 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS         0x7a23
 233 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS          0x7aa3
 234 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 235 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 236 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 237 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 238 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 239 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 240 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 241 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 242 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 243 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 244 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS          0xa0a3
 245 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 246 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 247 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 248 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 249 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 250 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS           0xa3a3
 251
 252 struct i801_mux_config {
 253         char *gpio_chip;
 254         unsigned values[3];
 255         int n_values;
 256         unsigned classes[3];
 257         unsigned gpios[2];              /* Relative to gpio_chip->base */
 258         int n_gpios;
 259 };
 260
 261 struct i801_priv {
 262         struct i2c_adapter adapter;
 263         unsigned long smba;
 264         unsigned char original_hstcfg;
 265         unsigned char original_hstcnt;
 266         unsigned char original_slvcmd;
 267         struct pci_dev *pci_dev;
 268         unsigned int features;
 269
 270         /* isr processing */
 271         struct completion done;
 272         u8 status;
 273
 274         /* Command state used by isr for byte-by-byte block transactions */
 275         u8 cmd;
 276         bool is_read;
 277         int count;
 278         int len;
 279         u8 *data;
 280
 281 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 282         const struct i801_mux_config *mux_drvdata;
 283         struct platform_device *mux_pdev;
 284         struct gpiod_lookup_table *lookup;
 285 #endif
 286         struct platform_device *tco_pdev;
 287
 288         /*
 289          * If set to true the host controller registers are reserved for
 290          * ACPI AML use. Protected by acpi_lock.
 291          */
 292         bool acpi_reserved;
 293         struct mutex acpi_lock;
 294 };
 295
 296 #define FEATURE_SMBUS_PEC       BIT(0)
 297 #define FEATURE_BLOCK_BUFFER    BIT(1)
 298 #define FEATURE_BLOCK_PROC      BIT(2)
 299 #define FEATURE_I2C_BLOCK_READ  BIT(3)
 300 #define FEATURE_IRQ             BIT(4)
 301 #define FEATURE_HOST_NOTIFY     BIT(5)
 302 /* Not really a feature, but it's convenient to handle it as such */
 303 #define FEATURE_IDF             BIT(15)
 304 #define FEATURE_TCO_SPT         BIT(16)
 305 #define FEATURE_TCO_CNL         BIT(17)
 306
 307 static const char *i801_feature_names[] = {
 308         "SMBus PEC",
 309         "Block buffer",
 310         "Block process call",
 311         "I2C block read",
 312         "Interrupt",
 313         "SMBus Host Notify",
 314 };
 315
 316 static unsigned int disable_features;
 317 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 318 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 319         "\t\t  0x01  disable SMBus PEC\n"
 320         "\t\t  0x02  disable the block buffer\n"
 321         "\t\t  0x08  disable the I2C block read functionality\n"
 322         "\t\t  0x10  don't use interrupts\n"
 323         "\t\t  0x20  disable SMBus Host Notify ");
 324
 325 /* Make sure the SMBus host is ready to start transmitting.
 326    Return 0 if it is, -EBUSY if it is not. */
 327 static int i801_check_pre(struct i801_priv *priv)
 328 {
 329         int status;
 330
 331         status = inb_p(SMBHSTSTS(priv));
 332         if (status & SMBHSTSTS_HOST_BUSY) {
 333                 pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n");
 334                 return -EBUSY;
 335         }
 336
 337         status &= STATUS_FLAGS;
 338         if (status) {
 339                 pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status);
 340                 outb_p(status, SMBHSTSTS(priv));
 341         }
 342
 343         /*
 344          * Clear CRC status if needed.
 345          * During normal operation, i801_check_post() takes care
 346          * of it after every operation.  We do it here only in case
 347          * the hardware was already in this state when the driver
 348          * started.
 349          */
 350         if (priv->features & FEATURE_SMBUS_PEC) {
 351                 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 352                 if (status) {
 353                         pci_dbg(priv->pci_dev, "Clearing aux status flags (%02x)\n", status);
 354                         outb_p(status, SMBAUXSTS(priv));
 355                 }
 356         }
 357
 358         return 0;
 359 }
 360
 361 static int i801_check_post(struct i801_priv *priv, int status)
 362 {
 363         int result = 0;
 364
 365         /*
 366          * If the SMBus is still busy, we give up
 367          * Note: This timeout condition only happens when using polling
 368          * transactions.  For interrupt operation, NAK/timeout is indicated by
 369          * DEV_ERR.
 370          */
 371         if (unlikely(status < 0)) {
 372                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 373                 /* try to stop the current command */
 374                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 375                 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
 376                 usleep_range(1000, 2000);
 377                 outb_p(0, SMBHSTCNT(priv));
 378
 379                 /* Check if it worked */
 380                 status = inb_p(SMBHSTSTS(priv));
 381                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 382                     !(status & SMBHSTSTS_FAILED))
 383                         dev_err(&priv->pci_dev->dev,
 384                                 "Failed terminating the transaction\n");
 385                 return -ETIMEDOUT;
 386         }
 387
 388         if (status & SMBHSTSTS_FAILED) {
 389                 result = -EIO;
 390                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 391         }
 392         if (status & SMBHSTSTS_DEV_ERR) {
 393                 /*
 394                  * This may be a PEC error, check and clear it.
 395                  *
 396                  * AUXSTS is handled differently from HSTSTS.
 397                  * For HSTSTS, i801_isr() or i801_wait_intr()
 398                  * has already cleared the error bits in hardware,
 399                  * and we are passed a copy of the original value
 400                  * in "status".
 401                  * For AUXSTS, the hardware register is left
 402                  * for us to handle here.
 403                  * This is asymmetric, slightly iffy, but safe,
 404                  * since all this code is serialized and the CRCE
 405                  * bit is harmless as long as it's cleared before
 406                  * the next operation.
 407                  */
 408                 if ((priv->features & FEATURE_SMBUS_PEC) &&
 409                     (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 410                         outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 411                         result = -EBADMSG;
 412                         dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 413                 } else {
 414                         result = -ENXIO;
 415                         dev_dbg(&priv->pci_dev->dev, "No response\n");
 416                 }
 417         }
 418         if (status & SMBHSTSTS_BUS_ERR) {
 419                 result = -EAGAIN;
 420                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 421         }
 422
 423         return result;
 424 }
 425
 426 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 427 static int i801_wait_intr(struct i801_priv *priv)
 428 {
 429         unsigned long timeout = jiffies + priv->adapter.timeout;
 430         int status, busy;
 431
 432         do {
 433                 usleep_range(250, 500);
 434                 status = inb_p(SMBHSTSTS(priv));
 435                 busy = status & SMBHSTSTS_HOST_BUSY;
 436                 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
 437                 if (!busy && status)
 438                         return status;
 439         } while (time_is_after_eq_jiffies(timeout));
 440
 441         return -ETIMEDOUT;
 442 }
 443
 444 /* Wait for either BYTE_DONE or an error flag being set */
 445 static int i801_wait_byte_done(struct i801_priv *priv)
 446 {
 447         unsigned long timeout = jiffies + priv->adapter.timeout;
 448         int status;
 449
 450         do {
 451                 usleep_range(250, 500);
 452                 status = inb_p(SMBHSTSTS(priv));
 453                 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
 454                         return status & STATUS_ERROR_FLAGS;
 455         } while (time_is_after_eq_jiffies(timeout));
 456
 457         return -ETIMEDOUT;
 458 }
 459
 460 static int i801_transaction(struct i801_priv *priv, int xact)
 461 {
 462         int status;
 463         unsigned long result;
 464         const struct i2c_adapter *adap = &priv->adapter;
 465
 466         status = i801_check_pre(priv);
 467         if (status < 0)
 468                 return status;
 469
 470         if (priv->features & FEATURE_IRQ) {
 471                 reinit_completion(&priv->done);
 472                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 473                        SMBHSTCNT(priv));
 474                 result = wait_for_completion_timeout(&priv->done, adap->timeout);
 475                 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
 476         }
 477
 478         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 479          * SMBSCMD are passed in xact */
 480         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 481
 482         status = i801_wait_intr(priv);
 483         return i801_check_post(priv, status);
 484 }
 485
 486 static int i801_block_transaction_by_block(struct i801_priv *priv,
 487                                            union i2c_smbus_data *data,
 488                                            char read_write, int command)
 489 {
 490         int i, len, status, xact;
 491
 492         switch (command) {
 493         case I2C_SMBUS_BLOCK_PROC_CALL:
 494                 xact = I801_BLOCK_PROC_CALL;
 495                 break;
 496         case I2C_SMBUS_BLOCK_DATA:
 497                 xact = I801_BLOCK_DATA;
 498                 break;
 499         default:
 500                 return -EOPNOTSUPP;
 501         }
 502
 503         /* Set block buffer mode */
 504         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 505
 506         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 507
 508         if (read_write == I2C_SMBUS_WRITE) {
 509                 len = data->block[0];
 510                 outb_p(len, SMBHSTDAT0(priv));
 511                 for (i = 0; i < len; i++)
 512                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 513         }
 514
 515         status = i801_transaction(priv, xact);
 516         if (status)
 517                 return status;
 518
 519         if (read_write == I2C_SMBUS_READ ||
 520             command == I2C_SMBUS_BLOCK_PROC_CALL) {
 521                 len = inb_p(SMBHSTDAT0(priv));
 522                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 523                         return -EPROTO;
 524
 525                 data->block[0] = len;
 526                 for (i = 0; i < len; i++)
 527                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 528         }
 529         return 0;
 530 }
 531
 532 static void i801_isr_byte_done(struct i801_priv *priv)
 533 {
 534         if (priv->is_read) {
 535                 /* For SMBus block reads, length is received with first byte */
 536                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 537                     (priv->count == 0)) {
 538                         priv->len = inb_p(SMBHSTDAT0(priv));
 539                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 540                                 dev_err(&priv->pci_dev->dev,
 541                                         "Illegal SMBus block read size %d\n",
 542                                         priv->len);
 543                                 /* FIXME: Recover */
 544                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 545                         }
 546                         priv->data[-1] = priv->len;
 547                 }
 548
 549                 /* Read next byte */
 550                 if (priv->count < priv->len)
 551                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 552                 else
 553                         dev_dbg(&priv->pci_dev->dev,
 554                                 "Discarding extra byte on block read\n");
 555
 556                 /* Set LAST_BYTE for last byte of read transaction */
 557                 if (priv->count == priv->len - 1)
 558                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 559                                SMBHSTCNT(priv));
 560         } else if (priv->count < priv->len - 1) {
 561                 /* Write next byte, except for IRQ after last byte */
 562                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 563         }
 564
 565         /* Clear BYTE_DONE to continue with next byte */
 566         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 567 }
 568
 569 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 570 {
 571         unsigned short addr;
 572
 573         addr = inb_p(SMBNTFDADD(priv)) >> 1;
 574
 575         /*
 576          * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 577          * always returns 0. Our current implementation doesn't provide
 578          * data, so we just ignore it.
 579          */
 580         i2c_handle_smbus_host_notify(&priv->adapter, addr);
 581
 582         /* clear Host Notify bit and return */
 583         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 584         return IRQ_HANDLED;
 585 }
 586
 587 /*
 588  * There are three kinds of interrupts:
 589  *
 590  * 1) i801 signals transaction completion with one of these interrupts:
 591  *      INTR - Success
 592  *      DEV_ERR - Invalid command, NAK or communication timeout
 593  *      BUS_ERR - SMI# transaction collision
 594  *      FAILED - transaction was canceled due to a KILL request
 595  *    When any of these occur, update ->status and signal completion.
 596  *    ->status must be cleared before kicking off the next transaction.
 597  *
 598  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 599  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 600  *
 601  * 3) Host Notify interrupts
 602  */
 603 static irqreturn_t i801_isr(int irq, void *dev_id)
 604 {
 605         struct i801_priv *priv = dev_id;
 606         u16 pcists;
 607         u8 status;
 608
 609         /* Confirm this is our interrupt */
 610         pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
 611         if (!(pcists & PCI_STATUS_INTERRUPT))
 612                 return IRQ_NONE;
 613
 614         if (priv->features & FEATURE_HOST_NOTIFY) {
 615                 status = inb_p(SMBSLVSTS(priv));
 616                 if (status & SMBSLVSTS_HST_NTFY_STS)
 617                         return i801_host_notify_isr(priv);
 618         }
 619
 620         status = inb_p(SMBHSTSTS(priv));
 621         if (status & SMBHSTSTS_BYTE_DONE)
 622                 i801_isr_byte_done(priv);
 623
 624         /*
 625          * Clear remaining IRQ sources: Completion of last command, errors
 626          * and the SMB_ALERT signal. SMB_ALERT status is set after signal
 627          * assertion independently of the interrupt generation being blocked
 628          * or not so clear it always when the status is set.
 629          */
 630         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS | SMBHSTSTS_SMBALERT_STS;
 631         if (status)
 632                 outb_p(status, SMBHSTSTS(priv));
 633         status &= ~SMBHSTSTS_SMBALERT_STS; /* SMB_ALERT not reported */
 634         /*
 635          * Report transaction result.
 636          * ->status must be cleared before the next transaction is started.
 637          */
 638         if (status) {
 639                 priv->status = status;
 640                 complete(&priv->done);
 641         }
 642
 643         return IRQ_HANDLED;
 644 }
 645
 646 /*
 647  * For "byte-by-byte" block transactions:
 648  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 649  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 650  */
 651 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 652                                                union i2c_smbus_data *data,
 653                                                char read_write, int command)
 654 {
 655         int i, len;
 656         int smbcmd;
 657         int status;
 658         unsigned long result;
 659         const struct i2c_adapter *adap = &priv->adapter;
 660
 661         if (command == I2C_SMBUS_BLOCK_PROC_CALL)
 662                 return -EOPNOTSUPP;
 663
 664         status = i801_check_pre(priv);
 665         if (status < 0)
 666                 return status;
 667
 668         len = data->block[0];
 669
 670         if (read_write == I2C_SMBUS_WRITE) {
 671                 outb_p(len, SMBHSTDAT0(priv));
 672                 outb_p(data->block[1], SMBBLKDAT(priv));
 673         }
 674
 675         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 676             read_write == I2C_SMBUS_READ)
 677                 smbcmd = I801_I2C_BLOCK_DATA;
 678         else
 679                 smbcmd = I801_BLOCK_DATA;
 680
 681         if (priv->features & FEATURE_IRQ) {
 682                 priv->is_read = (read_write == I2C_SMBUS_READ);
 683                 if (len == 1 && priv->is_read)
 684                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 685                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 686                 priv->len = len;
 687                 priv->count = 0;
 688                 priv->data = &data->block[1];
 689
 690                 reinit_completion(&priv->done);
 691                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 692                 result = wait_for_completion_timeout(&priv->done, adap->timeout);
 693                 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
 694         }
 695
 696         for (i = 1; i <= len; i++) {
 697                 if (i == len && read_write == I2C_SMBUS_READ)
 698                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 699                 outb_p(smbcmd, SMBHSTCNT(priv));
 700
 701                 if (i == 1)
 702                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 703                                SMBHSTCNT(priv));
 704
 705                 status = i801_wait_byte_done(priv);
 706                 if (status)
 707                         goto exit;
 708
 709                 if (i == 1 && read_write == I2C_SMBUS_READ
 710                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 711                         len = inb_p(SMBHSTDAT0(priv));
 712                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 713                                 dev_err(&priv->pci_dev->dev,
 714                                         "Illegal SMBus block read size %d\n",
 715                                         len);
 716                                 /* Recover */
 717                                 while (inb_p(SMBHSTSTS(priv)) &
 718                                        SMBHSTSTS_HOST_BUSY)
 719                                         outb_p(SMBHSTSTS_BYTE_DONE,
 720                                                SMBHSTSTS(priv));
 721                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 722                                 return -EPROTO;
 723                         }
 724                         data->block[0] = len;
 725                 }
 726
 727                 /* Retrieve/store value in SMBBLKDAT */
 728                 if (read_write == I2C_SMBUS_READ)
 729                         data->block[i] = inb_p(SMBBLKDAT(priv));
 730                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 731                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 732
 733                 /* signals SMBBLKDAT ready */
 734                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 735         }
 736
 737         status = i801_wait_intr(priv);
 738 exit:
 739         return i801_check_post(priv, status);
 740 }
 741
 742 /* Block transaction function */
 743 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
 744                                   char read_write, int command)
 745 {
 746         int result = 0;
 747         unsigned char hostc;
 748
 749         if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
 750                 data->block[0] = I2C_SMBUS_BLOCK_MAX;
 751         else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 752                 return -EPROTO;
 753
 754         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 755                 if (read_write == I2C_SMBUS_WRITE) {
 756                         /* set I2C_EN bit in configuration register */
 757                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 758                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 759                                               hostc | SMBHSTCFG_I2C_EN);
 760                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 761                         dev_err(&priv->pci_dev->dev,
 762                                 "I2C block read is unsupported!\n");
 763                         return -EOPNOTSUPP;
 764                 }
 765         }
 766
 767         /* Experience has shown that the block buffer can only be used for
 768            SMBus (not I2C) block transactions, even though the datasheet
 769            doesn't mention this limitation. */
 770         if ((priv->features & FEATURE_BLOCK_BUFFER) &&
 771             command != I2C_SMBUS_I2C_BLOCK_DATA)
 772                 result = i801_block_transaction_by_block(priv, data,
 773                                                          read_write,
 774                                                          command);
 775         else
 776                 result = i801_block_transaction_byte_by_byte(priv, data,
 777                                                              read_write,
 778                                                              command);
 779
 780         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 781          && read_write == I2C_SMBUS_WRITE) {
 782                 /* restore saved configuration register value */
 783                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 784         }
 785         return result;
 786 }
 787
 788 /* Return negative errno on error. */
 789 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 790                        unsigned short flags, char read_write, u8 command,
 791                        int size, union i2c_smbus_data *data)
 792 {
 793         int hwpec;
 794         int block = 0;
 795         int ret, xact;
 796         struct i801_priv *priv = i2c_get_adapdata(adap);
 797
 798         mutex_lock(&priv->acpi_lock);
 799         if (priv->acpi_reserved) {
 800                 mutex_unlock(&priv->acpi_lock);
 801                 return -EBUSY;
 802         }
 803
 804         pm_runtime_get_sync(&priv->pci_dev->dev);
 805
 806         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 807                 && size != I2C_SMBUS_QUICK
 808                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 809
 810         switch (size) {
 811         case I2C_SMBUS_QUICK:
 812                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 813                        SMBHSTADD(priv));
 814                 xact = I801_QUICK;
 815                 break;
 816         case I2C_SMBUS_BYTE:
 817                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 818                        SMBHSTADD(priv));
 819                 if (read_write == I2C_SMBUS_WRITE)
 820                         outb_p(command, SMBHSTCMD(priv));
 821                 xact = I801_BYTE;
 822                 break;
 823         case I2C_SMBUS_BYTE_DATA:
 824                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 825                        SMBHSTADD(priv));
 826                 outb_p(command, SMBHSTCMD(priv));
 827                 if (read_write == I2C_SMBUS_WRITE)
 828                         outb_p(data->byte, SMBHSTDAT0(priv));
 829                 xact = I801_BYTE_DATA;
 830                 break;
 831         case I2C_SMBUS_WORD_DATA:
 832                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 833                        SMBHSTADD(priv));
 834                 outb_p(command, SMBHSTCMD(priv));
 835                 if (read_write == I2C_SMBUS_WRITE) {
 836                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 837                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 838                 }
 839                 xact = I801_WORD_DATA;
 840                 break;
 841         case I2C_SMBUS_PROC_CALL:
 842                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 843                 outb_p(command, SMBHSTCMD(priv));
 844                 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 845                 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 846                 xact = I801_PROC_CALL;
 847                 read_write = I2C_SMBUS_READ;
 848                 break;
 849         case I2C_SMBUS_BLOCK_DATA:
 850                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 851                        SMBHSTADD(priv));
 852                 outb_p(command, SMBHSTCMD(priv));
 853                 block = 1;
 854                 break;
 855         case I2C_SMBUS_I2C_BLOCK_DATA:
 856                 /*
 857                  * NB: page 240 of ICH5 datasheet shows that the R/#W
 858                  * bit should be cleared here, even when reading.
 859                  * However if SPD Write Disable is set (Lynx Point and later),
 860                  * the read will fail if we don't set the R/#W bit.
 861                  */
 862                 outb_p(((addr & 0x7f) << 1) |
 863                        ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
 864                         (read_write & 0x01) : 0),
 865                        SMBHSTADD(priv));
 866                 if (read_write == I2C_SMBUS_READ) {
 867                         /* NB: page 240 of ICH5 datasheet also shows
 868                          * that DATA1 is the cmd field when reading */
 869                         outb_p(command, SMBHSTDAT1(priv));
 870                 } else
 871                         outb_p(command, SMBHSTCMD(priv));
 872                 block = 1;
 873                 break;
 874         case I2C_SMBUS_BLOCK_PROC_CALL:
 875                 /*
 876                  * Bit 0 of the slave address register always indicate a write
 877                  * command.
 878                  */
 879                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 880                 outb_p(command, SMBHSTCMD(priv));
 881                 block = 1;
 882                 break;
 883         default:
 884                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 885                         size);
 886                 ret = -EOPNOTSUPP;
 887                 goto out;
 888         }
 889
 890         if (hwpec)      /* enable/disable hardware PEC */
 891                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 892         else
 893                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 894                        SMBAUXCTL(priv));
 895
 896         if (block)
 897                 ret = i801_block_transaction(priv, data, read_write, size);
 898         else
 899                 ret = i801_transaction(priv, xact);
 900
 901         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 902            time, so we forcibly disable it after every transaction. Turn off
 903            E32B for the same reason. */
 904         if (hwpec || block)
 905                 outb_p(inb_p(SMBAUXCTL(priv)) &
 906                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 907
 908         if (block)
 909                 goto out;
 910         if (ret)
 911                 goto out;
 912         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 913                 goto out;
 914
 915         switch (xact) {
 916         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 917         case I801_BYTE_DATA:
 918                 data->byte = inb_p(SMBHSTDAT0(priv));
 919                 break;
 920         case I801_WORD_DATA:
 921         case I801_PROC_CALL:
 922                 data->word = inb_p(SMBHSTDAT0(priv)) +
 923                              (inb_p(SMBHSTDAT1(priv)) << 8);
 924                 break;
 925         }
 926
 927 out:
 928         /*
 929          * Unlock the SMBus device for use by BIOS/ACPI,
 930          * and clear status flags if not done already.
 931          */
 932         outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv));
 933
 934         pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 935         pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 936         mutex_unlock(&priv->acpi_lock);
 937         return ret;
 938 }
 939
 940
 941 static u32 i801_func(struct i2c_adapter *adapter)
 942 {
 943         struct i801_priv *priv = i2c_get_adapdata(adapter);
 944
 945         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 946                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 947                I2C_FUNC_SMBUS_PROC_CALL |
 948                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 949                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 950                ((priv->features & FEATURE_BLOCK_PROC) ?
 951                 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
 952                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 953                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 954                ((priv->features & FEATURE_HOST_NOTIFY) ?
 955                 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 956 }
 957
 958 static void i801_enable_host_notify(struct i2c_adapter *adapter)
 959 {
 960         struct i801_priv *priv = i2c_get_adapdata(adapter);
 961
 962         if (!(priv->features & FEATURE_HOST_NOTIFY))
 963                 return;
 964
 965         /*
 966          * Enable host notify interrupt and block the generation of interrupt
 967          * from the SMB_ALERT signal because the driver does not support
 968          * SMBus Alert.
 969          */
 970         outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE |
 971                priv->original_slvcmd, SMBSLVCMD(priv));
 972
 973         /* clear Host Notify bit to allow a new notification */
 974         outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 975 }
 976
 977 static void i801_disable_host_notify(struct i801_priv *priv)
 978 {
 979         if (!(priv->features & FEATURE_HOST_NOTIFY))
 980                 return;
 981
 982         outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
 983 }
 984
 985 static const struct i2c_algorithm smbus_algorithm = {
 986         .smbus_xfer     = i801_access,
 987         .functionality  = i801_func,
 988 };
 989
 990 #define FEATURES_ICH5   (FEATURE_BLOCK_PROC | FEATURE_I2C_BLOCK_READ    | \
 991                          FEATURE_IRQ | FEATURE_SMBUS_PEC                | \
 992                          FEATURE_BLOCK_BUFFER | FEATURE_HOST_NOTIFY)
 993 #define FEATURES_ICH4   (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \
 994                          FEATURE_HOST_NOTIFY)
 995
 996 static const struct pci_device_id i801_ids[] = {
 997         { PCI_DEVICE_DATA(INTEL, 82801AA_3,             0)                               },
 998         { PCI_DEVICE_DATA(INTEL, 82801AB_3,             0)                               },
 999         { PCI_DEVICE_DATA(INTEL, 82801BA_2,             0)                               },
1000         { PCI_DEVICE_DATA(INTEL, 82801CA_3,             FEATURE_HOST_NOTIFY)             },
1001         { PCI_DEVICE_DATA(INTEL, 82801DB_3,             FEATURES_ICH4)                   },
1002         { PCI_DEVICE_DATA(INTEL, 82801EB_3,             FEATURES_ICH5)                   },
1003         { PCI_DEVICE_DATA(INTEL, ESB_4,                 FEATURES_ICH5)                   },
1004         { PCI_DEVICE_DATA(INTEL, ICH6_16,               FEATURES_ICH5)                   },
1005         { PCI_DEVICE_DATA(INTEL, ICH7_17,               FEATURES_ICH5)                   },
1006         { PCI_DEVICE_DATA(INTEL, ESB2_17,               FEATURES_ICH5)                   },
1007         { PCI_DEVICE_DATA(INTEL, ICH8_5,                FEATURES_ICH5)                   },
1008         { PCI_DEVICE_DATA(INTEL, ICH9_6,                FEATURES_ICH5)                   },
1009         { PCI_DEVICE_DATA(INTEL, EP80579_1,             FEATURES_ICH5)                   },
1010         { PCI_DEVICE_DATA(INTEL, ICH10_4,               FEATURES_ICH5)                   },
1011         { PCI_DEVICE_DATA(INTEL, ICH10_5,               FEATURES_ICH5)                   },
1012         { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS,   FEATURES_ICH5)                   },
1013         { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS,     FEATURES_ICH5)                   },
1014         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS,        FEATURES_ICH5)                   },
1015         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0,   FEATURES_ICH5 | FEATURE_IDF)     },
1016         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1,   FEATURES_ICH5 | FEATURE_IDF)     },
1017         { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2,   FEATURES_ICH5 | FEATURE_IDF)     },
1018         { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS,        FEATURES_ICH5)                   },
1019         { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS,    FEATURES_ICH5)                   },
1020         { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS,       FEATURES_ICH5)                   },
1021         { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS,    FEATURES_ICH5)                   },
1022         { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS,          FEATURES_ICH5)                   },
1023         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS,       FEATURES_ICH5)                   },
1024         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0,   FEATURES_ICH5 | FEATURE_IDF)     },
1025         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1,   FEATURES_ICH5 | FEATURE_IDF)     },
1026         { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2,   FEATURES_ICH5 | FEATURE_IDF)     },
1027         { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS,     FEATURES_ICH5)                   },
1028         { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS,      FEATURES_ICH5)                   },
1029         { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS,    FEATURES_ICH5)                   },
1030         { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5)                   },
1031         { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS,        FEATURES_ICH5)                   },
1032         { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS,        FEATURES_ICH5)                   },
1033         { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1034         { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1035         { PCI_DEVICE_DATA(INTEL, CDF_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_CNL) },
1036         { PCI_DEVICE_DATA(INTEL, DNV_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_SPT) },
1037         { PCI_DEVICE_DATA(INTEL, EBG_SMBUS,             FEATURES_ICH5 | FEATURE_TCO_CNL) },
1038         { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS,         FEATURES_ICH5)                   },
1039         { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_SPT) },
1040         { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1041         { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1042         { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1043         { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_CNL) },
1044         { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS,      FEATURES_ICH5 | FEATURE_TCO_CNL) },
1045         { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_CNL) },
1046         { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS,       FEATURES_ICH5 | FEATURE_TCO_CNL) },
1047         { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1048         { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_SPT) },
1049         { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1050         { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1051         { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1052         { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1053         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1054         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1055         { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1056         { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_CNL) },
1057         { 0, }
1058 };
1059
1060 MODULE_DEVICE_TABLE(pci, i801_ids);
1061
1062 #if defined CONFIG_X86 && defined CONFIG_DMI
1063 static unsigned char apanel_addr;
1064
1065 /* Scan the system ROM for the signature "FJKEYINF" */
1066 static __init const void __iomem *bios_signature(const void __iomem *bios)
1067 {
1068         ssize_t offset;
1069         const unsigned char signature[] = "FJKEYINF";
1070
1071         for (offset = 0; offset < 0x10000; offset += 0x10) {
1072                 if (check_signature(bios + offset, signature,
1073                                     sizeof(signature)-1))
1074                         return bios + offset;
1075         }
1076         return NULL;
1077 }
1078
1079 static void __init input_apanel_init(void)
1080 {
1081         void __iomem *bios;
1082         const void __iomem *p;
1083
1084         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1085         p = bios_signature(bios);
1086         if (p) {
1087                 /* just use the first address */
1088                 apanel_addr = readb(p + 8 + 3) >> 1;
1089         }
1090         iounmap(bios);
1091 }
1092
1093 struct dmi_onboard_device_info {
1094         const char *name;
1095         u8 type;
1096         unsigned short i2c_addr;
1097         const char *i2c_type;
1098 };
1099
1100 static const struct dmi_onboard_device_info dmi_devices[] = {
1101         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1102         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1103         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1104 };
1105
1106 static void dmi_check_onboard_device(u8 type, const char *name,
1107                                      struct i2c_adapter *adap)
1108 {
1109         int i;
1110         struct i2c_board_info info;
1111
1112         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1113                 /* & ~0x80, ignore enabled/disabled bit */
1114                 if ((type & ~0x80) != dmi_devices[i].type)
1115                         continue;
1116                 if (strcasecmp(name, dmi_devices[i].name))
1117                         continue;
1118
1119                 memset(&info, 0, sizeof(struct i2c_board_info));
1120                 info.addr = dmi_devices[i].i2c_addr;
1121                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1122                 i2c_new_client_device(adap, &info);
1123                 break;
1124         }
1125 }
1126
1127 /* We use our own function to check for onboard devices instead of
1128    dmi_find_device() as some buggy BIOS's have the devices we are interested
1129    in marked as disabled */
1130 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1131 {
1132         int i, count;
1133
1134         if (dm->type != 10)
1135                 return;
1136
1137         count = (dm->length - sizeof(struct dmi_header)) / 2;
1138         for (i = 0; i < count; i++) {
1139                 const u8 *d = (char *)(dm + 1) + (i * 2);
1140                 const char *name = ((char *) dm) + dm->length;
1141                 u8 type = d[0];
1142                 u8 s = d[1];
1143
1144                 if (!s)
1145                         continue;
1146                 s--;
1147                 while (s > 0 && name[0]) {
1148                         name += strlen(name) + 1;
1149                         s--;
1150                 }
1151                 if (name[0] == 0) /* Bogus string reference */
1152                         continue;
1153
1154                 dmi_check_onboard_device(type, name, adap);
1155         }
1156 }
1157
1158 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1159 static const char *const acpi_smo8800_ids[] = {
1160         "SMO8800",
1161         "SMO8801",
1162         "SMO8810",
1163         "SMO8811",
1164         "SMO8820",
1165         "SMO8821",
1166         "SMO8830",
1167         "SMO8831",
1168 };
1169
1170 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1171                                              u32 nesting_level,
1172                                              void *context,
1173                                              void **return_value)
1174 {
1175         struct acpi_device_info *info;
1176         acpi_status status;
1177         char *hid;
1178         int i;
1179
1180         status = acpi_get_object_info(obj_handle, &info);
1181         if (ACPI_FAILURE(status))
1182                 return AE_OK;
1183
1184         if (!(info->valid & ACPI_VALID_HID))
1185                 goto smo88xx_not_found;
1186
1187         hid = info->hardware_id.string;
1188         if (!hid)
1189                 goto smo88xx_not_found;
1190
1191         i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1192         if (i < 0)
1193                 goto smo88xx_not_found;
1194
1195         kfree(info);
1196
1197         *return_value = NULL;
1198         return AE_CTRL_TERMINATE;
1199
1200 smo88xx_not_found:
1201         kfree(info);
1202         return AE_OK;
1203 }
1204
1205 static bool is_dell_system_with_lis3lv02d(void)
1206 {
1207         void *err = ERR_PTR(-ENOENT);
1208
1209         if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc."))
1210                 return false;
1211
1212         /*
1213          * Check that ACPI device SMO88xx is present and is functioning.
1214          * Function acpi_get_devices() already filters all ACPI devices
1215          * which are not present or are not functioning.
1216          * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1217          * accelerometer but unfortunately ACPI does not provide any other
1218          * information (like I2C address).
1219          */
1220         acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err);
1221
1222         return !IS_ERR(err);
1223 }
1224
1225 /*
1226  * Accelerometer's I2C address is not specified in DMI nor ACPI,
1227  * so it is needed to define mapping table based on DMI product names.
1228  */
1229 static const struct {
1230         const char *dmi_product_name;
1231         unsigned short i2c_addr;
1232 } dell_lis3lv02d_devices[] = {
1233         /*
1234          * Dell platform team told us that these Latitude devices have
1235          * ST microelectronics accelerometer at I2C address 0x29.
1236          */
1237         { "Latitude E5250",     0x29 },
1238         { "Latitude E5450",     0x29 },
1239         { "Latitude E5550",     0x29 },
1240         { "Latitude E6440",     0x29 },
1241         { "Latitude E6440 ATG", 0x29 },
1242         { "Latitude E6540",     0x29 },
1243         /*
1244          * Additional individual entries were added after verification.
1245          */
1246         { "Latitude 5480",      0x29 },
1247         { "Vostro V131",        0x1d },
1248 };
1249
1250 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1251 {
1252         struct i2c_board_info info;
1253         const char *dmi_product_name;
1254         int i;
1255
1256         dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1257         for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1258                 if (strcmp(dmi_product_name,
1259                            dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1260                         break;
1261         }
1262
1263         if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1264                 dev_warn(&priv->pci_dev->dev,
1265                          "Accelerometer lis3lv02d is present on SMBus but its"
1266                          " address is unknown, skipping registration\n");
1267                 return;
1268         }
1269
1270         memset(&info, 0, sizeof(struct i2c_board_info));
1271         info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1272         strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1273         i2c_new_client_device(&priv->adapter, &info);
1274 }
1275
1276 /* Register optional slaves */
1277 static void i801_probe_optional_slaves(struct i801_priv *priv)
1278 {
1279         /* Only register slaves on main SMBus channel */
1280         if (priv->features & FEATURE_IDF)
1281                 return;
1282
1283         if (apanel_addr) {
1284                 struct i2c_board_info info = {
1285                         .addr = apanel_addr,
1286                         .type = "fujitsu_apanel",
1287                 };
1288
1289                 i2c_new_client_device(&priv->adapter, &info);
1290         }
1291
1292         if (dmi_name_in_vendors("FUJITSU"))
1293                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1294
1295         if (is_dell_system_with_lis3lv02d())
1296                 register_dell_lis3lv02d_i2c_device(priv);
1297
1298         /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1299 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1300         if (!priv->mux_drvdata)
1301 #endif
1302                 i2c_register_spd(&priv->adapter);
1303 }
1304 #else
1305 static void __init input_apanel_init(void) {}
1306 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1307 #endif  /* CONFIG_X86 && CONFIG_DMI */
1308
1309 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1310 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1311         .gpio_chip = "gpio_ich",
1312         .values = { 0x02, 0x03 },
1313         .n_values = 2,
1314         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1315         .gpios = { 52, 53 },
1316         .n_gpios = 2,
1317 };
1318
1319 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1320         .gpio_chip = "gpio_ich",
1321         .values = { 0x02, 0x03, 0x01 },
1322         .n_values = 3,
1323         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1324         .gpios = { 52, 53 },
1325         .n_gpios = 2,
1326 };
1327
1328 static const struct dmi_system_id mux_dmi_table[] = {
1329         {
1330                 .matches = {
1331                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1332                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1333                 },
1334                 .driver_data = &i801_mux_config_asus_z8_d12,
1335         },
1336         {
1337                 .matches = {
1338                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1339                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1340                 },
1341                 .driver_data = &i801_mux_config_asus_z8_d12,
1342         },
1343         {
1344                 .matches = {
1345                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1346                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1347                 },
1348                 .driver_data = &i801_mux_config_asus_z8_d12,
1349         },
1350         {
1351                 .matches = {
1352                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1353                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1354                 },
1355                 .driver_data = &i801_mux_config_asus_z8_d12,
1356         },
1357         {
1358                 .matches = {
1359                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1360                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1361                 },
1362                 .driver_data = &i801_mux_config_asus_z8_d12,
1363         },
1364         {
1365                 .matches = {
1366                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1367                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1368                 },
1369                 .driver_data = &i801_mux_config_asus_z8_d12,
1370         },
1371         {
1372                 .matches = {
1373                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1374                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1375                 },
1376                 .driver_data = &i801_mux_config_asus_z8_d18,
1377         },
1378         {
1379                 .matches = {
1380                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1381                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1382                 },
1383                 .driver_data = &i801_mux_config_asus_z8_d18,
1384         },
1385         {
1386                 .matches = {
1387                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1388                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1389                 },
1390                 .driver_data = &i801_mux_config_asus_z8_d12,
1391         },
1392         { }
1393 };
1394
1395 /* Setup multiplexing if needed */
1396 static void i801_add_mux(struct i801_priv *priv)
1397 {
1398         struct device *dev = &priv->adapter.dev;
1399         const struct i801_mux_config *mux_config;
1400         struct i2c_mux_gpio_platform_data gpio_data;
1401         struct gpiod_lookup_table *lookup;
1402         int i;
1403
1404         if (!priv->mux_drvdata)
1405                 return;
1406         mux_config = priv->mux_drvdata;
1407
1408         /* Prepare the platform data */
1409         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1410         gpio_data.parent = priv->adapter.nr;
1411         gpio_data.values = mux_config->values;
1412         gpio_data.n_values = mux_config->n_values;
1413         gpio_data.classes = mux_config->classes;
1414         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1415
1416         /* Register GPIO descriptor lookup table */
1417         lookup = devm_kzalloc(dev,
1418                               struct_size(lookup, table, mux_config->n_gpios + 1),
1419                               GFP_KERNEL);
1420         if (!lookup)
1421                 return;
1422         lookup->dev_id = "i2c-mux-gpio";
1423         for (i = 0; i < mux_config->n_gpios; i++)
1424                 lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip,
1425                                                mux_config->gpios[i], "mux", 0);
1426         gpiod_add_lookup_table(lookup);
1427         priv->lookup = lookup;
1428
1429         /*
1430          * Register the mux device, we use PLATFORM_DEVID_NONE here
1431          * because since we are referring to the GPIO chip by name we are
1432          * anyways in deep trouble if there is more than one of these
1433          * devices, and there should likely only be one platform controller
1434          * hub.
1435          */
1436         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1437                                 PLATFORM_DEVID_NONE, &gpio_data,
1438                                 sizeof(struct i2c_mux_gpio_platform_data));
1439         if (IS_ERR(priv->mux_pdev)) {
1440                 gpiod_remove_lookup_table(lookup);
1441                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1442         }
1443 }
1444
1445 static void i801_del_mux(struct i801_priv *priv)
1446 {
1447         platform_device_unregister(priv->mux_pdev);
1448         gpiod_remove_lookup_table(priv->lookup);
1449 }
1450
1451 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1452 {
1453         const struct dmi_system_id *id;
1454         const struct i801_mux_config *mux_config;
1455         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1456         int i;
1457
1458         id = dmi_first_match(mux_dmi_table);
1459         if (id) {
1460                 /* Remove branch classes from trunk */
1461                 mux_config = id->driver_data;
1462                 for (i = 0; i < mux_config->n_values; i++)
1463                         class &= ~mux_config->classes[i];
1464
1465                 /* Remember for later */
1466                 priv->mux_drvdata = mux_config;
1467         }
1468
1469         return class;
1470 }
1471 #else
1472 static inline void i801_add_mux(struct i801_priv *priv) { }
1473 static inline void i801_del_mux(struct i801_priv *priv) { }
1474
1475 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1476 {
1477         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1478 }
1479 #endif
1480
1481 static struct platform_device *
1482 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1483                  struct resource *tco_res)
1484 {
1485         static const struct itco_wdt_platform_data pldata = {
1486                 .name = "Intel PCH",
1487                 .version = 4,
1488         };
1489         struct resource *res;
1490         unsigned int devfn;
1491         u64 base64_addr;
1492         u32 base_addr;
1493         u8 hidden;
1494
1495         /*
1496          * We must access the NO_REBOOT bit over the Primary to Sideband
1497          * bridge (P2SB). The BIOS prevents the P2SB device from being
1498          * enumerated by the PCI subsystem, so we need to unhide/hide it
1499          * to lookup the P2SB BAR.
1500          */
1501         pci_lock_rescan_remove();
1502
1503         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1504
1505         /* Unhide the P2SB device, if it is hidden */
1506         pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1507         if (hidden)
1508                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1509
1510         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1511         base64_addr = base_addr & 0xfffffff0;
1512
1513         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1514         base64_addr |= (u64)base_addr << 32;
1515
1516         /* Hide the P2SB device, if it was hidden before */
1517         if (hidden)
1518                 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1519         pci_unlock_rescan_remove();
1520
1521         res = &tco_res[1];
1522         if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1523                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1524         else
1525                 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1526
1527         res->end = res->start + 3;
1528         res->flags = IORESOURCE_MEM;
1529
1530         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1531                                         tco_res, 2, &pldata, sizeof(pldata));
1532 }
1533
1534 static struct platform_device *
1535 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1536                  struct resource *tco_res)
1537 {
1538         static const struct itco_wdt_platform_data pldata = {
1539                 .name = "Intel PCH",
1540                 .version = 6,
1541         };
1542
1543         return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1544                                                  tco_res, 1, &pldata, sizeof(pldata));
1545 }
1546
1547 static void i801_add_tco(struct i801_priv *priv)
1548 {
1549         struct pci_dev *pci_dev = priv->pci_dev;
1550         struct resource tco_res[2], *res;
1551         u32 tco_base, tco_ctl;
1552
1553         /* If we have ACPI based watchdog use that instead */
1554         if (acpi_has_watchdog())
1555                 return;
1556
1557         if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1558                 return;
1559
1560         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1561         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1562         if (!(tco_ctl & TCOCTL_EN))
1563                 return;
1564
1565         memset(tco_res, 0, sizeof(tco_res));
1566         /*
1567          * Always populate the main iTCO IO resource here. The second entry
1568          * for NO_REBOOT MMIO is filled by the SPT specific function.
1569          */
1570         res = &tco_res[0];
1571         res->start = tco_base & ~1;
1572         res->end = res->start + 32 - 1;
1573         res->flags = IORESOURCE_IO;
1574
1575         if (priv->features & FEATURE_TCO_CNL)
1576                 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1577         else
1578                 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1579
1580         if (IS_ERR(priv->tco_pdev))
1581                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1582 }
1583
1584 #ifdef CONFIG_ACPI
1585 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1586                                       acpi_physical_address address)
1587 {
1588         return address >= priv->smba &&
1589                address <= pci_resource_end(priv->pci_dev, SMBBAR);
1590 }
1591
1592 static acpi_status
1593 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1594                      u64 *value, void *handler_context, void *region_context)
1595 {
1596         struct i801_priv *priv = handler_context;
1597         struct pci_dev *pdev = priv->pci_dev;
1598         acpi_status status;
1599
1600         /*
1601          * Once BIOS AML code touches the OpRegion we warn and inhibit any
1602          * further access from the driver itself. This device is now owned
1603          * by the system firmware.
1604          */
1605         mutex_lock(&priv->acpi_lock);
1606
1607         if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1608                 priv->acpi_reserved = true;
1609
1610                 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1611                 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1612
1613                 /*
1614                  * BIOS is accessing the host controller so prevent it from
1615                  * suspending automatically from now on.
1616                  */
1617                 pm_runtime_get_sync(&pdev->dev);
1618         }
1619
1620         if ((function & ACPI_IO_MASK) == ACPI_READ)
1621                 status = acpi_os_read_port(address, (u32 *)value, bits);
1622         else
1623                 status = acpi_os_write_port(address, (u32)*value, bits);
1624
1625         mutex_unlock(&priv->acpi_lock);
1626
1627         return status;
1628 }
1629
1630 static int i801_acpi_probe(struct i801_priv *priv)
1631 {
1632         acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1633         acpi_status status;
1634
1635         status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO,
1636                                                     i801_acpi_io_handler, NULL, priv);
1637         if (ACPI_SUCCESS(status))
1638                 return 0;
1639
1640         return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1641 }
1642
1643 static void i801_acpi_remove(struct i801_priv *priv)
1644 {
1645         acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1646
1647         acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1648 }
1649 #else
1650 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1651 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1652 #endif
1653
1654 static void i801_setup_hstcfg(struct i801_priv *priv)
1655 {
1656         unsigned char hstcfg = priv->original_hstcfg;
1657
1658         hstcfg &= ~SMBHSTCFG_I2C_EN;    /* SMBus timing */
1659         hstcfg |= SMBHSTCFG_HST_EN;
1660         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1661 }
1662
1663 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1664 {
1665         int err, i;
1666         struct i801_priv *priv;
1667
1668         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1669         if (!priv)
1670                 return -ENOMEM;
1671
1672         i2c_set_adapdata(&priv->adapter, priv);
1673         priv->adapter.owner = THIS_MODULE;
1674         priv->adapter.class = i801_get_adapter_class(priv);
1675         priv->adapter.algo = &smbus_algorithm;
1676         priv->adapter.dev.parent = &dev->dev;
1677         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1678         priv->adapter.retries = 3;
1679         mutex_init(&priv->acpi_lock);
1680
1681         priv->pci_dev = dev;
1682         priv->features = id->driver_data;
1683
1684         /* Disable features on user request */
1685         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1686                 if (priv->features & disable_features & (1 << i))
1687                         dev_notice(&dev->dev, "%s disabled by user\n",
1688                                    i801_feature_names[i]);
1689         }
1690         priv->features &= ~disable_features;
1691
1692         err = pcim_enable_device(dev);
1693         if (err) {
1694                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1695                         err);
1696                 return err;
1697         }
1698         pcim_pin_device(dev);
1699
1700         /* Determine the address of the SMBus area */
1701         priv->smba = pci_resource_start(dev, SMBBAR);
1702         if (!priv->smba) {
1703                 dev_err(&dev->dev,
1704                         "SMBus base address uninitialized, upgrade BIOS\n");
1705                 return -ENODEV;
1706         }
1707
1708         if (i801_acpi_probe(priv))
1709                 return -ENODEV;
1710
1711         err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME);
1712         if (err) {
1713                 dev_err(&dev->dev,
1714                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1715                         priv->smba,
1716                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1717                 i801_acpi_remove(priv);
1718                 return err;
1719         }
1720
1721         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1722         i801_setup_hstcfg(priv);
1723         if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1724                 dev_info(&dev->dev, "Enabling SMBus device\n");
1725
1726         if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1727                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1728                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1729                 priv->features &= ~FEATURE_IRQ;
1730         }
1731         if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1732                 dev_info(&dev->dev, "SPD Write Disable is set\n");
1733
1734         /* Clear special mode bits */
1735         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1736                 outb_p(inb_p(SMBAUXCTL(priv)) &
1737                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1738
1739         /* Remember original Interrupt and Host Notify settings */
1740         priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL;
1741         if (priv->features & FEATURE_HOST_NOTIFY)
1742                 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1743
1744         /* Default timeout in interrupt mode: 200 ms */
1745         priv->adapter.timeout = HZ / 5;
1746
1747         if (dev->irq == IRQ_NOTCONNECTED)
1748                 priv->features &= ~FEATURE_IRQ;
1749
1750         if (priv->features & FEATURE_IRQ) {
1751                 u16 pcists;
1752
1753                 /* Complain if an interrupt is already pending */
1754                 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1755                 if (pcists & PCI_STATUS_INTERRUPT)
1756                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1757         }
1758
1759         if (priv->features & FEATURE_IRQ) {
1760                 init_completion(&priv->done);
1761
1762                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1763                                        IRQF_SHARED, DRV_NAME, priv);
1764                 if (err) {
1765                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1766                                 dev->irq, err);
1767                         priv->features &= ~FEATURE_IRQ;
1768                 }
1769         }
1770         dev_info(&dev->dev, "SMBus using %s\n",
1771                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1772
1773         i801_add_tco(priv);
1774
1775         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1776                 "SMBus I801 adapter at %04lx", priv->smba);
1777         err = i2c_add_adapter(&priv->adapter);
1778         if (err) {
1779                 i801_acpi_remove(priv);
1780                 return err;
1781         }
1782
1783         i801_enable_host_notify(&priv->adapter);
1784
1785         i801_probe_optional_slaves(priv);
1786         /* We ignore errors - multiplexing is optional */
1787         i801_add_mux(priv);
1788
1789         pci_set_drvdata(dev, priv);
1790
1791         dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1792         pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1793         pm_runtime_use_autosuspend(&dev->dev);
1794         pm_runtime_put_autosuspend(&dev->dev);
1795         pm_runtime_allow(&dev->dev);
1796
1797         return 0;
1798 }
1799
1800 static void i801_remove(struct pci_dev *dev)
1801 {
1802         struct i801_priv *priv = pci_get_drvdata(dev);
1803
1804         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1805         i801_disable_host_notify(priv);
1806         i801_del_mux(priv);
1807         i2c_del_adapter(&priv->adapter);
1808         i801_acpi_remove(priv);
1809         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1810
1811         platform_device_unregister(priv->tco_pdev);
1812
1813         /* if acpi_reserved is set then usage_count is incremented already */
1814         if (!priv->acpi_reserved)
1815                 pm_runtime_get_noresume(&dev->dev);
1816
1817         /*
1818          * do not call pci_disable_device(dev) since it can cause hard hangs on
1819          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1820          */
1821 }
1822
1823 static void i801_shutdown(struct pci_dev *dev)
1824 {
1825         struct i801_priv *priv = pci_get_drvdata(dev);
1826
1827         /* Restore config registers to avoid hard hang on some systems */
1828         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1829         i801_disable_host_notify(priv);
1830         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1831 }
1832
1833 #ifdef CONFIG_PM_SLEEP
1834 static int i801_suspend(struct device *dev)
1835 {
1836         struct i801_priv *priv = dev_get_drvdata(dev);
1837
1838         outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1839         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1840         return 0;
1841 }
1842
1843 static int i801_resume(struct device *dev)
1844 {
1845         struct i801_priv *priv = dev_get_drvdata(dev);
1846
1847         i801_setup_hstcfg(priv);
1848         i801_enable_host_notify(&priv->adapter);
1849
1850         return 0;
1851 }
1852 #endif
1853
1854 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1855
1856 static struct pci_driver i801_driver = {
1857         .name           = DRV_NAME,
1858         .id_table       = i801_ids,
1859         .probe          = i801_probe,
1860         .remove         = i801_remove,
1861         .shutdown       = i801_shutdown,
1862         .driver         = {
1863                 .pm     = &i801_pm_ops,
1864         },
1865 };
1866
1867 static int __init i2c_i801_init(void)
1868 {
1869         if (dmi_name_in_vendors("FUJITSU"))
1870                 input_apanel_init();
1871         return pci_register_driver(&i801_driver);
1872 }
1873
1874 static void __exit i2c_i801_exit(void)
1875 {
1876         pci_unregister_driver(&i801_driver);
1877 }
1878
1879 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1880 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1881 MODULE_DESCRIPTION("I801 SMBus driver");
1882 MODULE_LICENSE("GPL");
1883
1884 module_init(i2c_i801_init);
1885 module_exit(i2c_i801_exit);