drivers/i2c/busses/i2c-gxp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */
   3
   4 #include <linux/err.h>
   5 #include <linux/io.h>
   6 #include <linux/i2c.h>
   7 #include <linux/module.h>
   8 #include <linux/of_device.h>
   9 #include <linux/regmap.h>
  10 #include <linux/mfd/syscon.h>
  11
  12 #define GXP_MAX_I2C_ENGINE 10
  13 static const char * const gxp_i2c_name[] = {
  14         "gxp-i2c0", "gxp-i2c1", "gxp-i2c2", "gxp-i2c3",
  15         "gxp-i2c4", "gxp-i2c5", "gxp-i2c6", "gxp-i2c7",
  16         "gxp-i2c8", "gxp-i2c9" };
  17
  18 /* GXP I2C Global interrupt status/enable register*/
  19 #define GXP_I2CINTSTAT          0x00
  20 #define GXP_I2CINTEN            0x04
  21
  22 /* GXP I2C registers */
  23 #define GXP_I2CSTAT             0x00
  24 #define MASK_STOP_EVENT         0x20
  25 #define MASK_ACK                0x08
  26 #define MASK_RW                 0x04
  27 #define GXP_I2CEVTERR           0x01
  28 #define MASK_SLAVE_CMD_EVENT    0x01
  29 #define MASK_SLAVE_DATA_EVENT   0x02
  30 #define MASK_MASTER_EVENT       0x10
  31 #define GXP_I2CSNPDAT           0x02
  32 #define GXP_I2CMCMD             0x04
  33 #define GXP_I2CSCMD             0x06
  34 #define GXP_I2CSNPAA            0x09
  35 #define GXP_I2CADVFEAT          0x0A
  36 #define GXP_I2COWNADR           0x0B
  37 #define GXP_I2CFREQDIV          0x0C
  38 #define GXP_I2CFLTFAIR          0x0D
  39 #define GXP_I2CTMOEDG           0x0E
  40 #define GXP_I2CCYCTIM           0x0F
  41
  42 /* I2CSCMD Bits */
  43 #define SNOOP_EVT_CLR           0x80
  44 #define SLAVE_EVT_CLR           0x40
  45 #define SNOOP_EVT_MASK          0x20
  46 #define SLAVE_EVT_MASK          0x10
  47 #define SLAVE_ACK_ENAB          0x08
  48 #define SLAVE_EVT_STALL         0x01
  49
  50 /* I2CMCMD Bits */
  51 #define MASTER_EVT_CLR          0x80
  52 #define MASTER_ACK_ENAB         0x08
  53 #define RW_CMD                  0x04
  54 #define STOP_CMD                0x02
  55 #define START_CMD               0x01
  56
  57 /* I2CTMOEDG value */
  58 #define GXP_DATA_EDGE_RST_CTRL  0x0a /* 30ns */
  59
  60 /* I2CFLTFAIR Bits */
  61 #define FILTER_CNT              0x30
  62 #define FAIRNESS_CNT            0x02
  63
  64 enum {
  65         GXP_I2C_IDLE = 0,
  66         GXP_I2C_ADDR_PHASE,
  67         GXP_I2C_RDATA_PHASE,
  68         GXP_I2C_WDATA_PHASE,
  69         GXP_I2C_ADDR_NACK,
  70         GXP_I2C_DATA_NACK,
  71         GXP_I2C_ERROR,
  72         GXP_I2C_COMP
  73 };
  74
  75 struct gxp_i2c_drvdata {
  76         struct device *dev;
  77         void __iomem *base;
  78         struct i2c_timings t;
  79         u32 engine;
  80         int irq;
  81         struct completion completion;
  82         struct i2c_adapter adapter;
  83         struct i2c_msg *curr_msg;
  84         int msgs_remaining;
  85         int msgs_num;
  86         u8 *buf;
  87         size_t buf_remaining;
  88         unsigned char state;
  89         struct i2c_client *slave;
  90         unsigned char stopped;
  91 };
  92
  93 static struct regmap *i2cg_map;
  94
  95 static void gxp_i2c_start(struct gxp_i2c_drvdata *drvdata)
  96 {
  97         u16 value;
  98
  99         drvdata->buf = drvdata->curr_msg->buf;
 100         drvdata->buf_remaining = drvdata->curr_msg->len;
 101
 102         /* Note: Address in struct i2c_msg is 7 bits */
 103         value = drvdata->curr_msg->addr << 9;
 104
 105         /* Read or Write */
 106         value |= drvdata->curr_msg->flags & I2C_M_RD ? RW_CMD | START_CMD : START_CMD;
 107
 108         drvdata->state = GXP_I2C_ADDR_PHASE;
 109         writew(value, drvdata->base + GXP_I2CMCMD);
 110 }
 111
 112 static int gxp_i2c_master_xfer(struct i2c_adapter *adapter,
 113                                struct i2c_msg *msgs, int num)
 114 {
 115         int ret;
 116         struct gxp_i2c_drvdata *drvdata = i2c_get_adapdata(adapter);
 117         unsigned long time_left;
 118
 119         drvdata->msgs_remaining = num;
 120         drvdata->curr_msg = msgs;
 121         drvdata->msgs_num = num;
 122         reinit_completion(&drvdata->completion);
 123
 124         gxp_i2c_start(drvdata);
 125
 126         time_left = wait_for_completion_timeout(&drvdata->completion,
 127                                                 adapter->timeout);
 128         ret = num - drvdata->msgs_remaining;
 129         if (time_left == 0)
 130                 return -ETIMEDOUT;
 131
 132         if (drvdata->state == GXP_I2C_ADDR_NACK)
 133                 return -ENXIO;
 134
 135         if (drvdata->state == GXP_I2C_DATA_NACK)
 136                 return -EIO;
 137
 138         return ret;
 139 }
 140
 141 static u32 gxp_i2c_func(struct i2c_adapter *adap)
 142 {
 143         if (IS_ENABLED(CONFIG_I2C_SLAVE))
 144                 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SLAVE;
 145
 146         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 147 }
 148
 149 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 150 static int gxp_i2c_reg_slave(struct i2c_client *slave)
 151 {
 152         struct gxp_i2c_drvdata *drvdata = i2c_get_adapdata(slave->adapter);
 153
 154         if (drvdata->slave)
 155                 return -EBUSY;
 156
 157         if (slave->flags & I2C_CLIENT_TEN)
 158                 return -EAFNOSUPPORT;
 159
 160         drvdata->slave = slave;
 161
 162         writeb(slave->addr << 1, drvdata->base + GXP_I2COWNADR);
 163         writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK | SLAVE_ACK_ENAB |
 164                SLAVE_EVT_STALL, drvdata->base + GXP_I2CSCMD);
 165
 166         return 0;
 167 }
 168
 169 static int gxp_i2c_unreg_slave(struct i2c_client *slave)
 170 {
 171         struct gxp_i2c_drvdata *drvdata = i2c_get_adapdata(slave->adapter);
 172
 173         WARN_ON(!drvdata->slave);
 174
 175         writeb(0x00, drvdata->base + GXP_I2COWNADR);
 176         writeb(SNOOP_EVT_CLR | SLAVE_EVT_CLR | SNOOP_EVT_MASK |
 177                SLAVE_EVT_MASK, drvdata->base + GXP_I2CSCMD);
 178
 179         drvdata->slave = NULL;
 180
 181         return 0;
 182 }
 183 #endif
 184
 185 static const struct i2c_algorithm gxp_i2c_algo = {
 186         .master_xfer   = gxp_i2c_master_xfer,
 187         .functionality = gxp_i2c_func,
 188 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 189         .reg_slave     = gxp_i2c_reg_slave,
 190         .unreg_slave   = gxp_i2c_unreg_slave,
 191 #endif
 192 };
 193
 194 static void gxp_i2c_stop(struct gxp_i2c_drvdata *drvdata)
 195 {
 196         /* Clear event and send stop */
 197         writeb(MASTER_EVT_CLR | STOP_CMD, drvdata->base + GXP_I2CMCMD);
 198
 199         complete(&drvdata->completion);
 200 }
 201
 202 static void gxp_i2c_restart(struct gxp_i2c_drvdata *drvdata)
 203 {
 204         u16 value;
 205
 206         drvdata->buf = drvdata->curr_msg->buf;
 207         drvdata->buf_remaining = drvdata->curr_msg->len;
 208
 209         value = drvdata->curr_msg->addr << 9;
 210
 211         if (drvdata->curr_msg->flags & I2C_M_RD) {
 212                 /* Read and clear master event */
 213                 value |= MASTER_EVT_CLR | RW_CMD | START_CMD;
 214         } else {
 215                 /* Write and clear master event */
 216                 value |= MASTER_EVT_CLR | START_CMD;
 217         }
 218
 219         drvdata->state = GXP_I2C_ADDR_PHASE;
 220
 221         writew(value, drvdata->base + GXP_I2CMCMD);
 222 }
 223
 224 static void gxp_i2c_chk_addr_ack(struct gxp_i2c_drvdata *drvdata)
 225 {
 226         u16 value;
 227
 228         value = readb(drvdata->base + GXP_I2CSTAT);
 229         if (!(value & MASK_ACK)) {
 230                 /* Got no ack, stop */
 231                 drvdata->state = GXP_I2C_ADDR_NACK;
 232                 gxp_i2c_stop(drvdata);
 233                 return;
 234         }
 235
 236         if (drvdata->curr_msg->flags & I2C_M_RD) {
 237                 /* Start to read data from slave */
 238                 if (drvdata->buf_remaining == 0) {
 239                         /* No more data to read, stop */
 240                         drvdata->msgs_remaining--;
 241                         drvdata->state = GXP_I2C_COMP;
 242                         gxp_i2c_stop(drvdata);
 243                         return;
 244                 }
 245                 drvdata->state = GXP_I2C_RDATA_PHASE;
 246
 247                 if (drvdata->buf_remaining == 1) {
 248                         /* The last data, do not ack */
 249                         writeb(MASTER_EVT_CLR | RW_CMD,
 250                                drvdata->base + GXP_I2CMCMD);
 251                 } else {
 252                         /* Read data and ack it */
 253                         writeb(MASTER_EVT_CLR | MASTER_ACK_ENAB |
 254                                RW_CMD, drvdata->base + GXP_I2CMCMD);
 255                 }
 256         } else {
 257                 /* Start to write first data to slave */
 258                 if (drvdata->buf_remaining == 0) {
 259                         /* No more data to write, stop */
 260                         drvdata->msgs_remaining--;
 261                         drvdata->state = GXP_I2C_COMP;
 262                         gxp_i2c_stop(drvdata);
 263                         return;
 264                 }
 265                 value = *drvdata->buf;
 266                 value = value << 8;
 267                 /* Clear master event */
 268                 value |= MASTER_EVT_CLR;
 269                 drvdata->buf++;
 270                 drvdata->buf_remaining--;
 271                 drvdata->state = GXP_I2C_WDATA_PHASE;
 272                 writew(value, drvdata->base + GXP_I2CMCMD);
 273         }
 274 }
 275
 276 static void gxp_i2c_ack_data(struct gxp_i2c_drvdata *drvdata)
 277 {
 278         u8 value;
 279
 280         /* Store the data returned */
 281         value = readb(drvdata->base + GXP_I2CSNPDAT);
 282         *drvdata->buf = value;
 283         drvdata->buf++;
 284         drvdata->buf_remaining--;
 285
 286         if (drvdata->buf_remaining == 0) {
 287                 /* No more data, this message is completed. */
 288                 drvdata->msgs_remaining--;
 289
 290                 if (drvdata->msgs_remaining == 0) {
 291                         /* No more messages, stop */
 292                         drvdata->state = GXP_I2C_COMP;
 293                         gxp_i2c_stop(drvdata);
 294                         return;
 295                 }
 296                 /* Move to next message and start transfer */
 297                 drvdata->curr_msg++;
 298                 gxp_i2c_restart(drvdata);
 299                 return;
 300         }
 301
 302         /* Ack the slave to make it send next byte */
 303         drvdata->state = GXP_I2C_RDATA_PHASE;
 304         if (drvdata->buf_remaining == 1) {
 305                 /* The last data, do not ack */
 306                 writeb(MASTER_EVT_CLR | RW_CMD,
 307                        drvdata->base + GXP_I2CMCMD);
 308         } else {
 309                 /* Read data and ack it */
 310                 writeb(MASTER_EVT_CLR | MASTER_ACK_ENAB |
 311                        RW_CMD, drvdata->base + GXP_I2CMCMD);
 312         }
 313 }
 314
 315 static void gxp_i2c_chk_data_ack(struct gxp_i2c_drvdata *drvdata)
 316 {
 317         u16 value;
 318
 319         value = readb(drvdata->base + GXP_I2CSTAT);
 320         if (!(value & MASK_ACK)) {
 321                 /* Received No ack, stop */
 322                 drvdata->state = GXP_I2C_DATA_NACK;
 323                 gxp_i2c_stop(drvdata);
 324                 return;
 325         }
 326
 327         /* Got ack, check if there is more data to write */
 328         if (drvdata->buf_remaining == 0) {
 329                 /* No more data, this message is completed */
 330                 drvdata->msgs_remaining--;
 331
 332                 if (drvdata->msgs_remaining == 0) {
 333                         /* No more messages, stop */
 334                         drvdata->state = GXP_I2C_COMP;
 335                         gxp_i2c_stop(drvdata);
 336                         return;
 337                 }
 338                 /* Move to next message and start transfer */
 339                 drvdata->curr_msg++;
 340                 gxp_i2c_restart(drvdata);
 341                 return;
 342         }
 343
 344         /* Write data to slave */
 345         value = *drvdata->buf;
 346         value = value << 8;
 347
 348         /* Clear master event */
 349         value |= MASTER_EVT_CLR;
 350         drvdata->buf++;
 351         drvdata->buf_remaining--;
 352         drvdata->state = GXP_I2C_WDATA_PHASE;
 353         writew(value, drvdata->base + GXP_I2CMCMD);
 354 }
 355
 356 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 357 static bool gxp_i2c_slave_irq_handler(struct gxp_i2c_drvdata *drvdata)
 358 {
 359         u8 value;
 360         u8 buf;
 361         int ret;
 362
 363         value = readb(drvdata->base + GXP_I2CEVTERR);
 364
 365         /* Received start or stop event */
 366         if (value & MASK_SLAVE_CMD_EVENT) {
 367                 value = readb(drvdata->base + GXP_I2CSTAT);
 368                 /* Master sent stop */
 369                 if (value & MASK_STOP_EVENT) {
 370                         if (drvdata->stopped == 0)
 371                                 i2c_slave_event(drvdata->slave, I2C_SLAVE_STOP, &buf);
 372                         writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK |
 373                                SLAVE_ACK_ENAB | SLAVE_EVT_STALL, drvdata->base + GXP_I2CSCMD);
 374                         drvdata->stopped = 1;
 375                 } else {
 376                         /* Master sent start and  wants to read */
 377                         drvdata->stopped = 0;
 378                         if (value & MASK_RW) {
 379                                 i2c_slave_event(drvdata->slave,
 380                                                 I2C_SLAVE_READ_REQUESTED, &buf);
 381                                 value = buf << 8 | (SLAVE_EVT_CLR | SNOOP_EVT_MASK |
 382                                                     SLAVE_EVT_STALL);
 383                                 writew(value, drvdata->base + GXP_I2CSCMD);
 384                         } else {
 385                                 /* Master wants to write to us */
 386                                 ret = i2c_slave_event(drvdata->slave,
 387                                                       I2C_SLAVE_WRITE_REQUESTED, &buf);
 388                                 if (!ret) {
 389                                         /* Ack next byte from master */
 390                                         writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK |
 391                                                SLAVE_ACK_ENAB | SLAVE_EVT_STALL,
 392                                                drvdata->base + GXP_I2CSCMD);
 393                                 } else {
 394                                         /* Nack next byte from master */
 395                                         writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK |
 396                                                SLAVE_EVT_STALL, drvdata->base + GXP_I2CSCMD);
 397                                 }
 398                         }
 399                 }
 400         } else if (value & MASK_SLAVE_DATA_EVENT) {
 401                 value = readb(drvdata->base + GXP_I2CSTAT);
 402                 /* Master wants to read */
 403                 if (value & MASK_RW) {
 404                         /* Master wants another byte */
 405                         if (value & MASK_ACK) {
 406                                 i2c_slave_event(drvdata->slave,
 407                                                 I2C_SLAVE_READ_PROCESSED, &buf);
 408                                 value = buf << 8 | (SLAVE_EVT_CLR | SNOOP_EVT_MASK |
 409                                                     SLAVE_EVT_STALL);
 410                                 writew(value, drvdata->base + GXP_I2CSCMD);
 411                         } else {
 412                                 /* No more bytes needed */
 413                                 writew(SLAVE_EVT_CLR | SNOOP_EVT_MASK |
 414                                        SLAVE_ACK_ENAB | SLAVE_EVT_STALL,
 415                                        drvdata->base + GXP_I2CSCMD);
 416                         }
 417                 } else {
 418                         /* Master wants to write to us */
 419                         value = readb(drvdata->base + GXP_I2CSNPDAT);
 420                         buf = (uint8_t)value;
 421                         ret = i2c_slave_event(drvdata->slave,
 422                                               I2C_SLAVE_WRITE_RECEIVED, &buf);
 423                         if (!ret) {
 424                                 /* Ack next byte from master */
 425                                 writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK |
 426                                        SLAVE_ACK_ENAB | SLAVE_EVT_STALL,
 427                                        drvdata->base + GXP_I2CSCMD);
 428                         } else {
 429                                 /* Nack next byte from master */
 430                                 writeb(SLAVE_EVT_CLR | SNOOP_EVT_MASK |
 431                                        SLAVE_EVT_STALL, drvdata->base + GXP_I2CSCMD);
 432                         }
 433                 }
 434         } else {
 435                 return false;
 436         }
 437
 438         return true;
 439 }
 440 #endif
 441
 442 static irqreturn_t gxp_i2c_irq_handler(int irq, void *_drvdata)
 443 {
 444         struct gxp_i2c_drvdata *drvdata = (struct gxp_i2c_drvdata *)_drvdata;
 445         u32 value;
 446
 447         /* Check if the interrupt is for the current engine */
 448         regmap_read(i2cg_map, GXP_I2CINTSTAT, &value);
 449         if (!(value & BIT(drvdata->engine)))
 450                 return IRQ_NONE;
 451
 452         value = readb(drvdata->base + GXP_I2CEVTERR);
 453
 454         /* Error */
 455         if (value & ~(MASK_MASTER_EVENT | MASK_SLAVE_CMD_EVENT |
 456                                 MASK_SLAVE_DATA_EVENT)) {
 457                 /* Clear all events */
 458                 writeb(0x00, drvdata->base + GXP_I2CEVTERR);
 459                 drvdata->state = GXP_I2C_ERROR;
 460                 gxp_i2c_stop(drvdata);
 461                 return IRQ_HANDLED;
 462         }
 463
 464         if (IS_ENABLED(CONFIG_I2C_SLAVE)) {
 465                 /* Slave mode */
 466                 if (value & (MASK_SLAVE_CMD_EVENT | MASK_SLAVE_DATA_EVENT)) {
 467                         if (gxp_i2c_slave_irq_handler(drvdata))
 468                                 return IRQ_HANDLED;
 469                         return IRQ_NONE;
 470                 }
 471         }
 472
 473         /*  Master mode */
 474         switch (drvdata->state) {
 475         case GXP_I2C_ADDR_PHASE:
 476                 gxp_i2c_chk_addr_ack(drvdata);
 477                 break;
 478
 479         case GXP_I2C_RDATA_PHASE:
 480                 gxp_i2c_ack_data(drvdata);
 481                 break;
 482
 483         case GXP_I2C_WDATA_PHASE:
 484                 gxp_i2c_chk_data_ack(drvdata);
 485                 break;
 486         }
 487
 488         return IRQ_HANDLED;
 489 }
 490
 491 static void gxp_i2c_init(struct gxp_i2c_drvdata *drvdata)
 492 {
 493         drvdata->state = GXP_I2C_IDLE;
 494         writeb(2000000 / drvdata->t.bus_freq_hz,
 495                drvdata->base + GXP_I2CFREQDIV);
 496         writeb(FILTER_CNT | FAIRNESS_CNT,
 497                drvdata->base + GXP_I2CFLTFAIR);
 498         writeb(GXP_DATA_EDGE_RST_CTRL, drvdata->base + GXP_I2CTMOEDG);
 499         writeb(0x00, drvdata->base + GXP_I2CCYCTIM);
 500         writeb(0x00, drvdata->base + GXP_I2CSNPAA);
 501         writeb(0x00, drvdata->base + GXP_I2CADVFEAT);
 502         writeb(SNOOP_EVT_CLR | SLAVE_EVT_CLR | SNOOP_EVT_MASK |
 503                SLAVE_EVT_MASK, drvdata->base + GXP_I2CSCMD);
 504         writeb(MASTER_EVT_CLR, drvdata->base + GXP_I2CMCMD);
 505         writeb(0x00, drvdata->base + GXP_I2CEVTERR);
 506         writeb(0x00, drvdata->base + GXP_I2COWNADR);
 507 }
 508
 509 static int gxp_i2c_probe(struct platform_device *pdev)
 510 {
 511         struct gxp_i2c_drvdata *drvdata;
 512         int rc;
 513         struct i2c_adapter *adapter;
 514
 515         if (!i2cg_map) {
 516                 i2cg_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 517                                                            "hpe,sysreg");
 518                 if (IS_ERR(i2cg_map)) {
 519                         return dev_err_probe(&pdev->dev, PTR_ERR(i2cg_map),
 520                                              "failed to map i2cg_handle\n");
 521                 }
 522
 523                 /* Disable interrupt */
 524                 regmap_update_bits(i2cg_map, GXP_I2CINTEN, 0x00000FFF, 0);
 525         }
 526
 527         drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata),
 528                                GFP_KERNEL);
 529         if (!drvdata)
 530                 return -ENOMEM;
 531
 532         platform_set_drvdata(pdev, drvdata);
 533         drvdata->dev = &pdev->dev;
 534         init_completion(&drvdata->completion);
 535
 536         drvdata->base = devm_platform_ioremap_resource(pdev, 0);
 537         if (IS_ERR(drvdata->base))
 538                 return PTR_ERR(drvdata->base);
 539
 540         /* Use physical memory address to determine which I2C engine this is. */
 541         drvdata->engine = ((size_t)drvdata->base & 0xf00) >> 8;
 542
 543         if (drvdata->engine >= GXP_MAX_I2C_ENGINE) {
 544                 return dev_err_probe(&pdev->dev, -EINVAL, "i2c engine% is unsupported\n",
 545                         drvdata->engine);
 546         }
 547
 548         rc = platform_get_irq(pdev, 0);
 549         if (rc < 0)
 550                 return rc;
 551
 552         drvdata->irq = rc;
 553         rc = devm_request_irq(&pdev->dev, drvdata->irq, gxp_i2c_irq_handler,
 554                               IRQF_SHARED, gxp_i2c_name[drvdata->engine], drvdata);
 555         if (rc < 0)
 556                 return dev_err_probe(&pdev->dev, rc, "irq request failed\n");
 557
 558         i2c_parse_fw_timings(&pdev->dev, &drvdata->t, true);
 559
 560         gxp_i2c_init(drvdata);
 561
 562         /* Enable interrupt */
 563         regmap_update_bits(i2cg_map, GXP_I2CINTEN, BIT(drvdata->engine),
 564                            BIT(drvdata->engine));
 565
 566         adapter = &drvdata->adapter;
 567         i2c_set_adapdata(adapter, drvdata);
 568
 569         adapter->owner = THIS_MODULE;
 570         strscpy(adapter->name, "HPE GXP I2C adapter", sizeof(adapter->name));
 571         adapter->algo = &gxp_i2c_algo;
 572         adapter->dev.parent = &pdev->dev;
 573         adapter->dev.of_node = pdev->dev.of_node;
 574
 575         rc = i2c_add_adapter(adapter);
 576         if (rc)
 577                 return dev_err_probe(&pdev->dev, rc, "i2c add adapter failed\n");
 578
 579         return 0;
 580 }
 581
 582 static int gxp_i2c_remove(struct platform_device *pdev)
 583 {
 584         struct gxp_i2c_drvdata *drvdata = platform_get_drvdata(pdev);
 585
 586         /* Disable interrupt */
 587         regmap_update_bits(i2cg_map, GXP_I2CINTEN, BIT(drvdata->engine), 0);
 588         i2c_del_adapter(&drvdata->adapter);
 589
 590         return 0;
 591 }
 592
 593 static const struct of_device_id gxp_i2c_of_match[] = {
 594         { .compatible = "hpe,gxp-i2c" },
 595         {},
 596 };
 597 MODULE_DEVICE_TABLE(of, gxp_i2c_of_match);
 598
 599 static struct platform_driver gxp_i2c_driver = {
 600         .probe  = gxp_i2c_probe,
 601         .remove = gxp_i2c_remove,
 602         .driver = {
 603                 .name = "gxp-i2c",
 604                 .of_match_table = gxp_i2c_of_match,
 605         },
 606 };
 607 module_platform_driver(gxp_i2c_driver);
 608
 609 MODULE_AUTHOR("Nick Hawkins <nick.hawkins@hpe.com>");
 610 MODULE_DESCRIPTION("HPE GXP I2C bus driver");
 611 MODULE_LICENSE("GPL");