2 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
14 #include <linux/i2c.h>
15 #include <linux/time.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/slab.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/spinlock.h>
29 * HSI2C controller from Samsung supports 2 modes of operation
30 * 1. Auto mode: Where in master automatically controls the whole transaction
31 * 2. Manual mode: Software controls the transaction by issuing commands
32 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
34 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
36 * Special bits are available for both modes of operation to set commands
37 * and for checking transfer status
41 #define HSI2C_CTL 0x00
42 #define HSI2C_FIFO_CTL 0x04
43 #define HSI2C_TRAILIG_CTL 0x08
44 #define HSI2C_CLK_CTL 0x0C
45 #define HSI2C_CLK_SLOT 0x10
46 #define HSI2C_INT_ENABLE 0x20
47 #define HSI2C_INT_STATUS 0x24
48 #define HSI2C_ERR_STATUS 0x2C
49 #define HSI2C_FIFO_STATUS 0x30
50 #define HSI2C_TX_DATA 0x34
51 #define HSI2C_RX_DATA 0x38
52 #define HSI2C_CONF 0x40
53 #define HSI2C_AUTO_CONF 0x44
54 #define HSI2C_TIMEOUT 0x48
55 #define HSI2C_MANUAL_CMD 0x4C
56 #define HSI2C_TRANS_STATUS 0x50
57 #define HSI2C_TIMING_HS1 0x54
58 #define HSI2C_TIMING_HS2 0x58
59 #define HSI2C_TIMING_HS3 0x5C
60 #define HSI2C_TIMING_FS1 0x60
61 #define HSI2C_TIMING_FS2 0x64
62 #define HSI2C_TIMING_FS3 0x68
63 #define HSI2C_TIMING_SLA 0x6C
64 #define HSI2C_ADDR 0x70
66 /* I2C_CTL Register bits */
67 #define HSI2C_FUNC_MODE_I2C (1u << 0)
68 #define HSI2C_MASTER (1u << 3)
69 #define HSI2C_RXCHON (1u << 6)
70 #define HSI2C_TXCHON (1u << 7)
71 #define HSI2C_SW_RST (1u << 31)
73 /* I2C_FIFO_CTL Register bits */
74 #define HSI2C_RXFIFO_EN (1u << 0)
75 #define HSI2C_TXFIFO_EN (1u << 1)
76 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4)
77 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16)
79 /* I2C_TRAILING_CTL Register bits */
80 #define HSI2C_TRAILING_COUNT (0xf)
82 /* I2C_INT_EN Register bits */
83 #define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)
84 #define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)
85 #define HSI2C_INT_TRAILING_EN (1u << 6)
87 /* I2C_INT_STAT Register bits */
88 #define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0)
89 #define HSI2C_INT_RX_ALMOSTFULL (1u << 1)
90 #define HSI2C_INT_TX_UNDERRUN (1u << 2)
91 #define HSI2C_INT_TX_OVERRUN (1u << 3)
92 #define HSI2C_INT_RX_UNDERRUN (1u << 4)
93 #define HSI2C_INT_RX_OVERRUN (1u << 5)
94 #define HSI2C_INT_TRAILING (1u << 6)
95 #define HSI2C_INT_I2C (1u << 9)
97 #define HSI2C_INT_TRANS_DONE (1u << 7)
98 #define HSI2C_INT_TRANS_ABORT (1u << 8)
99 #define HSI2C_INT_NO_DEV_ACK (1u << 9)
100 #define HSI2C_INT_NO_DEV (1u << 10)
101 #define HSI2C_INT_TIMEOUT (1u << 11)
102 #define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \
103 HSI2C_INT_TRANS_ABORT | \
104 HSI2C_INT_NO_DEV_ACK | \
108 /* I2C_FIFO_STAT Register bits */
109 #define HSI2C_RX_FIFO_EMPTY (1u << 24)
110 #define HSI2C_RX_FIFO_FULL (1u << 23)
111 #define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f)
112 #define HSI2C_TX_FIFO_EMPTY (1u << 8)
113 #define HSI2C_TX_FIFO_FULL (1u << 7)
114 #define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f)
116 /* I2C_CONF Register bits */
117 #define HSI2C_AUTO_MODE (1u << 31)
118 #define HSI2C_10BIT_ADDR_MODE (1u << 30)
119 #define HSI2C_HS_MODE (1u << 29)
121 /* I2C_AUTO_CONF Register bits */
122 #define HSI2C_READ_WRITE (1u << 16)
123 #define HSI2C_STOP_AFTER_TRANS (1u << 17)
124 #define HSI2C_MASTER_RUN (1u << 31)
126 /* I2C_TIMEOUT Register bits */
127 #define HSI2C_TIMEOUT_EN (1u << 31)
128 #define HSI2C_TIMEOUT_MASK 0xff
130 /* I2C_TRANS_STATUS register bits */
131 #define HSI2C_MASTER_BUSY (1u << 17)
132 #define HSI2C_SLAVE_BUSY (1u << 16)
134 /* I2C_TRANS_STATUS register bits for Exynos5 variant */
135 #define HSI2C_TIMEOUT_AUTO (1u << 4)
136 #define HSI2C_NO_DEV (1u << 3)
137 #define HSI2C_NO_DEV_ACK (1u << 2)
138 #define HSI2C_TRANS_ABORT (1u << 1)
139 #define HSI2C_TRANS_DONE (1u << 0)
141 /* I2C_TRANS_STATUS register bits for Exynos7 variant */
142 #define HSI2C_MASTER_ST_MASK 0xf
143 #define HSI2C_MASTER_ST_IDLE 0x0
144 #define HSI2C_MASTER_ST_START 0x1
145 #define HSI2C_MASTER_ST_RESTART 0x2
146 #define HSI2C_MASTER_ST_STOP 0x3
147 #define HSI2C_MASTER_ST_MASTER_ID 0x4
148 #define HSI2C_MASTER_ST_ADDR0 0x5
149 #define HSI2C_MASTER_ST_ADDR1 0x6
150 #define HSI2C_MASTER_ST_ADDR2 0x7
151 #define HSI2C_MASTER_ST_ADDR_SR 0x8
152 #define HSI2C_MASTER_ST_READ 0x9
153 #define HSI2C_MASTER_ST_WRITE 0xa
154 #define HSI2C_MASTER_ST_NO_ACK 0xb
155 #define HSI2C_MASTER_ST_LOSE 0xc
156 #define HSI2C_MASTER_ST_WAIT 0xd
157 #define HSI2C_MASTER_ST_WAIT_CMD 0xe
159 /* I2C_ADDR register bits */
160 #define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)
161 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
162 #define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)
163 #define MASTER_ID(x) ((x & 0x7) + 0x08)
166 * Controller operating frequency, timing values for operation
167 * are calculated against this frequency
169 #define HSI2C_HS_TX_CLOCK 1000000
170 #define HSI2C_FS_TX_CLOCK 100000
172 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
174 #define HSI2C_EXYNOS7 BIT(0)
177 struct i2c_adapter adap;
178 unsigned int suspended:1;
181 struct completion msg_complete;
182 unsigned int msg_ptr;
191 spinlock_t lock; /* IRQ synchronization */
194 * Since the TRANS_DONE bit is cleared on read, and we may read it
195 * either during an IRQ or after a transaction, keep track of its
200 /* Controller operating frequency */
201 unsigned int op_clock;
203 /* Version of HS-I2C Hardware */
204 struct exynos_hsi2c_variant *variant;
208 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
209 * @fifo_depth: the fifo depth supported by the HSI2C module
211 * Specifies platform specific configuration of HSI2C module.
212 * Note: A structure for driver specific platform data is used for future
213 * expansion of its usage.
215 struct exynos_hsi2c_variant {
216 unsigned int fifo_depth;
220 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
224 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
228 static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
233 static const struct of_device_id exynos5_i2c_match[] = {
235 .compatible = "samsung,exynos5-hsi2c",
236 .data = &exynos5250_hsi2c_data
238 .compatible = "samsung,exynos5250-hsi2c",
239 .data = &exynos5250_hsi2c_data
241 .compatible = "samsung,exynos5260-hsi2c",
242 .data = &exynos5260_hsi2c_data
244 .compatible = "samsung,exynos7-hsi2c",
245 .data = &exynos7_hsi2c_data
248 MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
250 static inline struct exynos_hsi2c_variant *exynos5_i2c_get_variant
251 (struct platform_device *pdev)
253 const struct of_device_id *match;
255 match = of_match_node(exynos5_i2c_match, pdev->dev.of_node);
256 return (struct exynos_hsi2c_variant *)match->data;
259 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
261 writel(readl(i2c->regs + HSI2C_INT_STATUS),
262 i2c->regs + HSI2C_INT_STATUS);
266 * exynos5_i2c_set_timing: updates the registers with appropriate
267 * timing values calculated
269 * Returns 0 on success, -EINVAL if the cycle length cannot
272 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
278 unsigned int t_start_su, t_start_hd;
279 unsigned int t_stop_su;
280 unsigned int t_data_su, t_data_hd;
281 unsigned int t_scl_l, t_scl_h;
282 unsigned int t_sr_release;
283 unsigned int t_ftl_cycle;
284 unsigned int clkin = clk_get_rate(i2c->clk);
285 unsigned int op_clk = hs_timings ? i2c->op_clock :
286 (i2c->op_clock >= HSI2C_HS_TX_CLOCK) ? HSI2C_FS_TX_CLOCK :
288 int div, clk_cycle, temp;
291 * In case of HSI2C controller in Exynos5 series
293 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
295 * In case of HSI2C controllers in Exynos7 series
297 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
299 * clk_cycle := TSCLK_L + TSCLK_H
300 * temp := (CLK_DIV + 1) * (clk_cycle + 2)
302 * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510
305 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
306 temp = clkin / op_clk - 8 - t_ftl_cycle;
307 if (i2c->variant->hw != HSI2C_EXYNOS7)
310 clk_cycle = temp / (div + 1) - 2;
311 if (temp < 4 || div >= 256 || clk_cycle < 2) {
312 dev_warn(i2c->dev, "Failed to calculate divisor");
316 t_scl_l = clk_cycle / 2;
317 t_scl_h = clk_cycle / 2;
318 t_start_su = t_scl_l;
319 t_start_hd = t_scl_l;
321 t_data_su = t_scl_l / 2;
322 t_data_hd = t_scl_l / 2;
323 t_sr_release = clk_cycle;
325 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
326 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
327 i2c_timing_s3 = div << 16 | t_sr_release << 0;
328 i2c_timing_sla = t_data_hd << 0;
330 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
331 t_start_su, t_start_hd, t_stop_su);
332 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
333 t_data_su, t_scl_l, t_scl_h);
334 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
336 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
339 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
340 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
341 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
343 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
344 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
345 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
347 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
352 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
355 * Configure the Fast speed timing values
356 * Even the High Speed mode initially starts with Fast mode
358 if (exynos5_i2c_set_timing(i2c, false)) {
359 dev_err(i2c->dev, "HSI2C FS Clock set up failed\n");
363 /* configure the High speed timing values */
364 if (i2c->op_clock >= HSI2C_HS_TX_CLOCK) {
365 if (exynos5_i2c_set_timing(i2c, true)) {
366 dev_err(i2c->dev, "HSI2C HS Clock set up failed\n");
375 * exynos5_i2c_init: configures the controller for I2C functionality
376 * Programs I2C controller for Master mode operation
378 static void exynos5_i2c_init(struct exynos5_i2c *i2c)
380 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
381 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
383 /* Clear to disable Timeout */
384 i2c_timeout &= ~HSI2C_TIMEOUT_EN;
385 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
387 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
388 i2c->regs + HSI2C_CTL);
389 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
391 if (i2c->op_clock >= HSI2C_HS_TX_CLOCK) {
392 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
393 i2c->regs + HSI2C_ADDR);
394 i2c_conf |= HSI2C_HS_MODE;
397 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
400 static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
404 /* Set and clear the bit for reset */
405 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
406 i2c_ctl |= HSI2C_SW_RST;
407 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
409 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
410 i2c_ctl &= ~HSI2C_SW_RST;
411 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
413 /* We don't expect calculations to fail during the run */
414 exynos5_hsi2c_clock_setup(i2c);
415 /* Initialize the configure registers */
416 exynos5_i2c_init(i2c);
420 * exynos5_i2c_irq: top level IRQ servicing routine
422 * INT_STATUS registers gives the interrupt details. Further,
423 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
426 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
428 struct exynos5_i2c *i2c = dev_id;
429 u32 fifo_level, int_status, fifo_status, trans_status;
433 i2c->state = -EINVAL;
435 spin_lock(&i2c->lock);
437 int_status = readl(i2c->regs + HSI2C_INT_STATUS);
438 writel(int_status, i2c->regs + HSI2C_INT_STATUS);
440 /* handle interrupt related to the transfer status */
441 if (i2c->variant->hw == HSI2C_EXYNOS7) {
442 if (int_status & HSI2C_INT_TRANS_DONE) {
445 } else if (int_status & HSI2C_INT_TRANS_ABORT) {
446 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
447 i2c->state = -EAGAIN;
449 } else if (int_status & HSI2C_INT_NO_DEV_ACK) {
450 dev_dbg(i2c->dev, "No ACK from device\n");
453 } else if (int_status & HSI2C_INT_NO_DEV) {
454 dev_dbg(i2c->dev, "No device\n");
457 } else if (int_status & HSI2C_INT_TIMEOUT) {
458 dev_dbg(i2c->dev, "Accessing device timed out\n");
459 i2c->state = -ETIMEDOUT;
463 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
464 if ((trans_status & HSI2C_MASTER_ST_MASK) == HSI2C_MASTER_ST_LOSE) {
465 i2c->state = -EAGAIN;
468 } else if (int_status & HSI2C_INT_I2C) {
469 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
470 if (trans_status & HSI2C_NO_DEV_ACK) {
471 dev_dbg(i2c->dev, "No ACK from device\n");
474 } else if (trans_status & HSI2C_NO_DEV) {
475 dev_dbg(i2c->dev, "No device\n");
478 } else if (trans_status & HSI2C_TRANS_ABORT) {
479 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
480 i2c->state = -EAGAIN;
482 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
483 dev_dbg(i2c->dev, "Accessing device timed out\n");
484 i2c->state = -ETIMEDOUT;
486 } else if (trans_status & HSI2C_TRANS_DONE) {
492 if ((i2c->msg->flags & I2C_M_RD) && (int_status &
493 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
494 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
495 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
496 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
499 byte = (unsigned char)
500 readl(i2c->regs + HSI2C_RX_DATA);
501 i2c->msg->buf[i2c->msg_ptr++] = byte;
505 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
506 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
507 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
509 len = i2c->variant->fifo_depth - fifo_level;
510 if (len > (i2c->msg->len - i2c->msg_ptr)) {
511 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
513 int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN;
514 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
515 len = i2c->msg->len - i2c->msg_ptr;
519 byte = i2c->msg->buf[i2c->msg_ptr++];
520 writel(byte, i2c->regs + HSI2C_TX_DATA);
527 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
529 writel(0, i2c->regs + HSI2C_INT_ENABLE);
530 exynos5_i2c_clr_pend_irq(i2c);
531 complete(&i2c->msg_complete);
534 spin_unlock(&i2c->lock);
540 * exynos5_i2c_wait_bus_idle
542 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
545 * Returns -EBUSY if the bus cannot be bought to idle
547 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
549 unsigned long stop_time;
552 /* wait for 100 milli seconds for the bus to be idle */
553 stop_time = jiffies + msecs_to_jiffies(100) + 1;
555 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
556 if (!(trans_status & HSI2C_MASTER_BUSY))
559 usleep_range(50, 200);
560 } while (time_before(jiffies, stop_time));
566 * exynos5_i2c_message_start: Configures the bus and starts the xfer
567 * i2c: struct exynos5_i2c pointer for the current bus
568 * stop: Enables stop after transfer if set. Set for last transfer of
569 * in the list of messages.
571 * Configures the bus for read/write function
572 * Sets chip address to talk to, message length to be sent.
573 * Enables appropriate interrupts and sends start xfer command.
575 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
579 u32 i2c_auto_conf = 0;
582 unsigned short trig_lvl;
584 if (i2c->variant->hw == HSI2C_EXYNOS7)
585 int_en |= HSI2C_INT_I2C_TRANS;
587 int_en |= HSI2C_INT_I2C;
589 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
590 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
591 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
593 if (i2c->msg->flags & I2C_M_RD) {
594 i2c_ctl |= HSI2C_RXCHON;
596 i2c_auto_conf |= HSI2C_READ_WRITE;
598 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
599 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
600 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
602 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
603 HSI2C_INT_TRAILING_EN);
605 i2c_ctl |= HSI2C_TXCHON;
607 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
608 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
609 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
611 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
614 writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR);
616 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
617 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
620 * Enable interrupts before starting the transfer so that we don't
621 * miss any INT_I2C interrupts.
623 spin_lock_irqsave(&i2c->lock, flags);
624 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
627 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
628 i2c_auto_conf |= i2c->msg->len;
629 i2c_auto_conf |= HSI2C_MASTER_RUN;
630 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
631 spin_unlock_irqrestore(&i2c->lock, flags);
634 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
635 struct i2c_msg *msgs, int stop)
637 unsigned long timeout;
644 reinit_completion(&i2c->msg_complete);
646 exynos5_i2c_message_start(i2c, stop);
648 timeout = wait_for_completion_timeout(&i2c->msg_complete,
649 EXYNOS5_I2C_TIMEOUT);
656 * If this is the last message to be transfered (stop == 1)
657 * Then check if the bus can be brought back to idle.
659 if (ret == 0 && stop)
660 ret = exynos5_i2c_wait_bus_idle(i2c);
663 exynos5_i2c_reset(i2c);
664 if (ret == -ETIMEDOUT)
665 dev_warn(i2c->dev, "%s timeout\n",
666 (msgs->flags & I2C_M_RD) ? "rx" : "tx");
669 /* Return the state as in interrupt routine */
673 static int exynos5_i2c_xfer(struct i2c_adapter *adap,
674 struct i2c_msg *msgs, int num)
676 struct exynos5_i2c *i2c = adap->algo_data;
677 int i = 0, ret = 0, stop = 0;
679 if (i2c->suspended) {
680 dev_err(i2c->dev, "HS-I2C is not initialized.\n");
684 ret = clk_enable(i2c->clk);
688 for (i = 0; i < num; i++, msgs++) {
689 stop = (i == num - 1);
691 ret = exynos5_i2c_xfer_msg(i2c, msgs, stop);
700 /* Only one message, cannot access the device */
706 dev_warn(i2c->dev, "xfer message failed\n");
710 clk_disable(i2c->clk);
714 static u32 exynos5_i2c_func(struct i2c_adapter *adap)
716 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
719 static const struct i2c_algorithm exynos5_i2c_algorithm = {
720 .master_xfer = exynos5_i2c_xfer,
721 .functionality = exynos5_i2c_func,
724 static int exynos5_i2c_probe(struct platform_device *pdev)
726 struct device_node *np = pdev->dev.of_node;
727 struct exynos5_i2c *i2c;
728 struct resource *mem;
731 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
735 if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
736 i2c->op_clock = HSI2C_FS_TX_CLOCK;
738 strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
739 i2c->adap.owner = THIS_MODULE;
740 i2c->adap.algo = &exynos5_i2c_algorithm;
741 i2c->adap.retries = 3;
743 i2c->dev = &pdev->dev;
744 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
745 if (IS_ERR(i2c->clk)) {
746 dev_err(&pdev->dev, "cannot get clock\n");
750 ret = clk_prepare_enable(i2c->clk);
754 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
755 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
756 if (IS_ERR(i2c->regs)) {
757 ret = PTR_ERR(i2c->regs);
761 i2c->adap.dev.of_node = np;
762 i2c->adap.algo_data = i2c;
763 i2c->adap.dev.parent = &pdev->dev;
765 /* Clear pending interrupts from u-boot or misc causes */
766 exynos5_i2c_clr_pend_irq(i2c);
768 spin_lock_init(&i2c->lock);
769 init_completion(&i2c->msg_complete);
771 i2c->irq = ret = platform_get_irq(pdev, 0);
773 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
778 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
779 IRQF_NO_SUSPEND | IRQF_ONESHOT,
780 dev_name(&pdev->dev), i2c);
783 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
787 /* Need to check the variant before setting up. */
788 i2c->variant = exynos5_i2c_get_variant(pdev);
790 ret = exynos5_hsi2c_clock_setup(i2c);
794 exynos5_i2c_reset(i2c);
796 ret = i2c_add_adapter(&i2c->adap);
800 platform_set_drvdata(pdev, i2c);
802 clk_disable(i2c->clk);
807 clk_disable_unprepare(i2c->clk);
811 static int exynos5_i2c_remove(struct platform_device *pdev)
813 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
815 i2c_del_adapter(&i2c->adap);
817 clk_unprepare(i2c->clk);
822 #ifdef CONFIG_PM_SLEEP
823 static int exynos5_i2c_suspend_noirq(struct device *dev)
825 struct platform_device *pdev = to_platform_device(dev);
826 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
830 clk_unprepare(i2c->clk);
835 static int exynos5_i2c_resume_noirq(struct device *dev)
837 struct platform_device *pdev = to_platform_device(dev);
838 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
841 ret = clk_prepare_enable(i2c->clk);
845 ret = exynos5_hsi2c_clock_setup(i2c);
847 clk_disable_unprepare(i2c->clk);
851 exynos5_i2c_init(i2c);
852 clk_disable(i2c->clk);
859 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
860 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq,
861 exynos5_i2c_resume_noirq)
864 static struct platform_driver exynos5_i2c_driver = {
865 .probe = exynos5_i2c_probe,
866 .remove = exynos5_i2c_remove,
868 .name = "exynos5-hsi2c",
869 .pm = &exynos5_i2c_dev_pm_ops,
870 .of_match_table = exynos5_i2c_match,
874 module_platform_driver(exynos5_i2c_driver);
876 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
877 MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>");
878 MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>");
879 MODULE_LICENSE("GPL v2");