drivers/i2c/busses/i2c-exynos5.c

   1 /**
   2  * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13
  14 #include <linux/i2c.h>
  15 #include <linux/time.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/delay.h>
  18 #include <linux/errno.h>
  19 #include <linux/err.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/slab.h>
  23 #include <linux/io.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26 #include <linux/spinlock.h>
  27
  28 /*
  29  * HSI2C controller from Samsung supports 2 modes of operation
  30  * 1. Auto mode: Where in master automatically controls the whole transaction
  31  * 2. Manual mode: Software controls the transaction by issuing commands
  32  *    START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
  33  *
  34  * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
  35  *
  36  * Special bits are available for both modes of operation to set commands
  37  * and for checking transfer status
  38  */
  39
  40 /* Register Map */
  41 #define HSI2C_CTL               0x00
  42 #define HSI2C_FIFO_CTL          0x04
  43 #define HSI2C_TRAILIG_CTL       0x08
  44 #define HSI2C_CLK_CTL           0x0C
  45 #define HSI2C_CLK_SLOT          0x10
  46 #define HSI2C_INT_ENABLE        0x20
  47 #define HSI2C_INT_STATUS        0x24
  48 #define HSI2C_ERR_STATUS        0x2C
  49 #define HSI2C_FIFO_STATUS       0x30
  50 #define HSI2C_TX_DATA           0x34
  51 #define HSI2C_RX_DATA           0x38
  52 #define HSI2C_CONF              0x40
  53 #define HSI2C_AUTO_CONF         0x44
  54 #define HSI2C_TIMEOUT           0x48
  55 #define HSI2C_MANUAL_CMD        0x4C
  56 #define HSI2C_TRANS_STATUS      0x50
  57 #define HSI2C_TIMING_HS1        0x54
  58 #define HSI2C_TIMING_HS2        0x58
  59 #define HSI2C_TIMING_HS3        0x5C
  60 #define HSI2C_TIMING_FS1        0x60
  61 #define HSI2C_TIMING_FS2        0x64
  62 #define HSI2C_TIMING_FS3        0x68
  63 #define HSI2C_TIMING_SLA        0x6C
  64 #define HSI2C_ADDR              0x70
  65
  66 /* I2C_CTL Register bits */
  67 #define HSI2C_FUNC_MODE_I2C                     (1u << 0)
  68 #define HSI2C_MASTER                            (1u << 3)
  69 #define HSI2C_RXCHON                            (1u << 6)
  70 #define HSI2C_TXCHON                            (1u << 7)
  71 #define HSI2C_SW_RST                            (1u << 31)
  72
  73 /* I2C_FIFO_CTL Register bits */
  74 #define HSI2C_RXFIFO_EN                         (1u << 0)
  75 #define HSI2C_TXFIFO_EN                         (1u << 1)
  76 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x)           ((x) << 4)
  77 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x)           ((x) << 16)
  78
  79 /* I2C_TRAILING_CTL Register bits */
  80 #define HSI2C_TRAILING_COUNT                    (0xf)
  81
  82 /* I2C_INT_EN Register bits */
  83 #define HSI2C_INT_TX_ALMOSTEMPTY_EN             (1u << 0)
  84 #define HSI2C_INT_RX_ALMOSTFULL_EN              (1u << 1)
  85 #define HSI2C_INT_TRAILING_EN                   (1u << 6)
  86
  87 /* I2C_INT_STAT Register bits */
  88 #define HSI2C_INT_TX_ALMOSTEMPTY                (1u << 0)
  89 #define HSI2C_INT_RX_ALMOSTFULL                 (1u << 1)
  90 #define HSI2C_INT_TX_UNDERRUN                   (1u << 2)
  91 #define HSI2C_INT_TX_OVERRUN                    (1u << 3)
  92 #define HSI2C_INT_RX_UNDERRUN                   (1u << 4)
  93 #define HSI2C_INT_RX_OVERRUN                    (1u << 5)
  94 #define HSI2C_INT_TRAILING                      (1u << 6)
  95 #define HSI2C_INT_I2C                           (1u << 9)
  96
  97 #define HSI2C_INT_TRANS_DONE                    (1u << 7)
  98 #define HSI2C_INT_TRANS_ABORT                   (1u << 8)
  99 #define HSI2C_INT_NO_DEV_ACK                    (1u << 9)
 100 #define HSI2C_INT_NO_DEV                        (1u << 10)
 101 #define HSI2C_INT_TIMEOUT                       (1u << 11)
 102 #define HSI2C_INT_I2C_TRANS                     (HSI2C_INT_TRANS_DONE | \
 103                                                 HSI2C_INT_TRANS_ABORT | \
 104                                                 HSI2C_INT_NO_DEV_ACK |  \
 105                                                 HSI2C_INT_NO_DEV |      \
 106                                                 HSI2C_INT_TIMEOUT)
 107
 108 /* I2C_FIFO_STAT Register bits */
 109 #define HSI2C_RX_FIFO_EMPTY                     (1u << 24)
 110 #define HSI2C_RX_FIFO_FULL                      (1u << 23)
 111 #define HSI2C_RX_FIFO_LVL(x)                    ((x >> 16) & 0x7f)
 112 #define HSI2C_TX_FIFO_EMPTY                     (1u << 8)
 113 #define HSI2C_TX_FIFO_FULL                      (1u << 7)
 114 #define HSI2C_TX_FIFO_LVL(x)                    ((x >> 0) & 0x7f)
 115
 116 /* I2C_CONF Register bits */
 117 #define HSI2C_AUTO_MODE                         (1u << 31)
 118 #define HSI2C_10BIT_ADDR_MODE                   (1u << 30)
 119 #define HSI2C_HS_MODE                           (1u << 29)
 120
 121 /* I2C_AUTO_CONF Register bits */
 122 #define HSI2C_READ_WRITE                        (1u << 16)
 123 #define HSI2C_STOP_AFTER_TRANS                  (1u << 17)
 124 #define HSI2C_MASTER_RUN                        (1u << 31)
 125
 126 /* I2C_TIMEOUT Register bits */
 127 #define HSI2C_TIMEOUT_EN                        (1u << 31)
 128 #define HSI2C_TIMEOUT_MASK                      0xff
 129
 130 /* I2C_TRANS_STATUS register bits */
 131 #define HSI2C_MASTER_BUSY                       (1u << 17)
 132 #define HSI2C_SLAVE_BUSY                        (1u << 16)
 133
 134 /* I2C_TRANS_STATUS register bits for Exynos5 variant */
 135 #define HSI2C_TIMEOUT_AUTO                      (1u << 4)
 136 #define HSI2C_NO_DEV                            (1u << 3)
 137 #define HSI2C_NO_DEV_ACK                        (1u << 2)
 138 #define HSI2C_TRANS_ABORT                       (1u << 1)
 139 #define HSI2C_TRANS_DONE                        (1u << 0)
 140
 141 /* I2C_TRANS_STATUS register bits for Exynos7 variant */
 142 #define HSI2C_MASTER_ST_MASK                    0xf
 143 #define HSI2C_MASTER_ST_IDLE                    0x0
 144 #define HSI2C_MASTER_ST_START                   0x1
 145 #define HSI2C_MASTER_ST_RESTART                 0x2
 146 #define HSI2C_MASTER_ST_STOP                    0x3
 147 #define HSI2C_MASTER_ST_MASTER_ID               0x4
 148 #define HSI2C_MASTER_ST_ADDR0                   0x5
 149 #define HSI2C_MASTER_ST_ADDR1                   0x6
 150 #define HSI2C_MASTER_ST_ADDR2                   0x7
 151 #define HSI2C_MASTER_ST_ADDR_SR                 0x8
 152 #define HSI2C_MASTER_ST_READ                    0x9
 153 #define HSI2C_MASTER_ST_WRITE                   0xa
 154 #define HSI2C_MASTER_ST_NO_ACK                  0xb
 155 #define HSI2C_MASTER_ST_LOSE                    0xc
 156 #define HSI2C_MASTER_ST_WAIT                    0xd
 157 #define HSI2C_MASTER_ST_WAIT_CMD                0xe
 158
 159 /* I2C_ADDR register bits */
 160 #define HSI2C_SLV_ADDR_SLV(x)                   ((x & 0x3ff) << 0)
 161 #define HSI2C_SLV_ADDR_MAS(x)                   ((x & 0x3ff) << 10)
 162 #define HSI2C_MASTER_ID(x)                      ((x & 0xff) << 24)
 163 #define MASTER_ID(x)                            ((x & 0x7) + 0x08)
 164
 165 /*
 166  * Controller operating frequency, timing values for operation
 167  * are calculated against this frequency
 168  */
 169 #define HSI2C_HS_TX_CLOCK       1000000
 170 #define HSI2C_FS_TX_CLOCK       100000
 171 #define HSI2C_HIGH_SPD          1
 172 #define HSI2C_FAST_SPD          0
 173
 174 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
 175
 176 #define HSI2C_EXYNOS7   BIT(0)
 177
 178 struct exynos5_i2c {
 179         struct i2c_adapter      adap;
 180         unsigned int            suspended:1;
 181
 182         struct i2c_msg          *msg;
 183         struct completion       msg_complete;
 184         unsigned int            msg_ptr;
 185
 186         unsigned int            irq;
 187
 188         void __iomem            *regs;
 189         struct clk              *clk;
 190         struct device           *dev;
 191         int                     state;
 192
 193         spinlock_t              lock;           /* IRQ synchronization */
 194
 195         /*
 196          * Since the TRANS_DONE bit is cleared on read, and we may read it
 197          * either during an IRQ or after a transaction, keep track of its
 198          * state here.
 199          */
 200         int                     trans_done;
 201
 202         /* Controller operating frequency */
 203         unsigned int            fs_clock;
 204         unsigned int            hs_clock;
 205
 206         /*
 207          * HSI2C Controller can operate in
 208          * 1. High speed upto 3.4Mbps
 209          * 2. Fast speed upto 1Mbps
 210          */
 211         int                     speed_mode;
 212
 213         /* Version of HS-I2C Hardware */
 214         struct exynos_hsi2c_variant     *variant;
 215 };
 216
 217 /**
 218  * struct exynos_hsi2c_variant - platform specific HSI2C driver data
 219  * @fifo_depth: the fifo depth supported by the HSI2C module
 220  *
 221  * Specifies platform specific configuration of HSI2C module.
 222  * Note: A structure for driver specific platform data is used for future
 223  * expansion of its usage.
 224  */
 225 struct exynos_hsi2c_variant {
 226         unsigned int    fifo_depth;
 227         unsigned int    hw;
 228 };
 229
 230 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
 231         .fifo_depth     = 64,
 232 };
 233
 234 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
 235         .fifo_depth     = 16,
 236 };
 237
 238 static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
 239         .fifo_depth     = 16,
 240         .hw             = HSI2C_EXYNOS7,
 241 };
 242
 243 static const struct of_device_id exynos5_i2c_match[] = {
 244         {
 245                 .compatible = "samsung,exynos5-hsi2c",
 246                 .data = &exynos5250_hsi2c_data
 247         }, {
 248                 .compatible = "samsung,exynos5250-hsi2c",
 249                 .data = &exynos5250_hsi2c_data
 250         }, {
 251                 .compatible = "samsung,exynos5260-hsi2c",
 252                 .data = &exynos5260_hsi2c_data
 253         }, {
 254                 .compatible = "samsung,exynos7-hsi2c",
 255                 .data = &exynos7_hsi2c_data
 256         }, {},
 257 };
 258 MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
 259
 260 static inline struct exynos_hsi2c_variant *exynos5_i2c_get_variant
 261                                         (struct platform_device *pdev)
 262 {
 263         const struct of_device_id *match;
 264
 265         match = of_match_node(exynos5_i2c_match, pdev->dev.of_node);
 266         return (struct exynos_hsi2c_variant *)match->data;
 267 }
 268
 269 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
 270 {
 271         writel(readl(i2c->regs + HSI2C_INT_STATUS),
 272                                 i2c->regs + HSI2C_INT_STATUS);
 273 }
 274
 275 /*
 276  * exynos5_i2c_set_timing: updates the registers with appropriate
 277  * timing values calculated
 278  *
 279  * Returns 0 on success, -EINVAL if the cycle length cannot
 280  * be calculated.
 281  */
 282 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode)
 283 {
 284         u32 i2c_timing_s1;
 285         u32 i2c_timing_s2;
 286         u32 i2c_timing_s3;
 287         u32 i2c_timing_sla;
 288         unsigned int t_start_su, t_start_hd;
 289         unsigned int t_stop_su;
 290         unsigned int t_data_su, t_data_hd;
 291         unsigned int t_scl_l, t_scl_h;
 292         unsigned int t_sr_release;
 293         unsigned int t_ftl_cycle;
 294         unsigned int clkin = clk_get_rate(i2c->clk);
 295         unsigned int op_clk = (mode == HSI2C_HIGH_SPD) ?
 296                                 i2c->hs_clock : i2c->fs_clock;
 297         int div, clk_cycle, temp;
 298
 299         /*
 300          * In case of HSI2C controller in Exynos5 series
 301          * FPCLK / FI2C =
 302          * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
 303          *
 304          * In case of HSI2C controllers in Exynos7 series
 305          * FPCLK / FI2C =
 306          * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
 307          *
 308          * clk_cycle := TSCLK_L + TSCLK_H
 309          * temp := (CLK_DIV + 1) * (clk_cycle + 2)
 310          *
 311          * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510
 312          *
 313          */
 314         t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
 315         temp = clkin / op_clk - 8 - t_ftl_cycle;
 316         if (i2c->variant->hw != HSI2C_EXYNOS7)
 317                 temp -= t_ftl_cycle;
 318         div = temp / 512;
 319         clk_cycle = temp / (div + 1) - 2;
 320         if (temp < 4 || div >= 256 || clk_cycle < 2) {
 321                 dev_warn(i2c->dev, "Failed to calculate divisor");
 322                 return -EINVAL;
 323         }
 324
 325         t_scl_l = clk_cycle / 2;
 326         t_scl_h = clk_cycle / 2;
 327         t_start_su = t_scl_l;
 328         t_start_hd = t_scl_l;
 329         t_stop_su = t_scl_l;
 330         t_data_su = t_scl_l / 2;
 331         t_data_hd = t_scl_l / 2;
 332         t_sr_release = clk_cycle;
 333
 334         i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
 335         i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
 336         i2c_timing_s3 = div << 16 | t_sr_release << 0;
 337         i2c_timing_sla = t_data_hd << 0;
 338
 339         dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
 340                 t_start_su, t_start_hd, t_stop_su);
 341         dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
 342                 t_data_su, t_scl_l, t_scl_h);
 343         dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
 344                 div, t_sr_release);
 345         dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
 346
 347         if (mode == HSI2C_HIGH_SPD) {
 348                 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
 349                 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
 350                 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
 351         } else {
 352                 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
 353                 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
 354                 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
 355         }
 356         writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
 357
 358         return 0;
 359 }
 360
 361 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
 362 {
 363         /*
 364          * Configure the Fast speed timing values
 365          * Even the High Speed mode initially starts with Fast mode
 366          */
 367         if (exynos5_i2c_set_timing(i2c, HSI2C_FAST_SPD)) {
 368                 dev_err(i2c->dev, "HSI2C FS Clock set up failed\n");
 369                 return -EINVAL;
 370         }
 371
 372         /* configure the High speed timing values */
 373         if (i2c->speed_mode == HSI2C_HIGH_SPD) {
 374                 if (exynos5_i2c_set_timing(i2c, HSI2C_HIGH_SPD)) {
 375                         dev_err(i2c->dev, "HSI2C HS Clock set up failed\n");
 376                         return -EINVAL;
 377                 }
 378         }
 379
 380         return 0;
 381 }
 382
 383 /*
 384  * exynos5_i2c_init: configures the controller for I2C functionality
 385  * Programs I2C controller for Master mode operation
 386  */
 387 static void exynos5_i2c_init(struct exynos5_i2c *i2c)
 388 {
 389         u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
 390         u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
 391
 392         /* Clear to disable Timeout */
 393         i2c_timeout &= ~HSI2C_TIMEOUT_EN;
 394         writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
 395
 396         writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
 397                                         i2c->regs + HSI2C_CTL);
 398         writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
 399
 400         if (i2c->speed_mode == HSI2C_HIGH_SPD) {
 401                 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
 402                                         i2c->regs + HSI2C_ADDR);
 403                 i2c_conf |= HSI2C_HS_MODE;
 404         }
 405
 406         writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
 407 }
 408
 409 static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
 410 {
 411         u32 i2c_ctl;
 412
 413         /* Set and clear the bit for reset */
 414         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 415         i2c_ctl |= HSI2C_SW_RST;
 416         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 417
 418         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 419         i2c_ctl &= ~HSI2C_SW_RST;
 420         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 421
 422         /* We don't expect calculations to fail during the run */
 423         exynos5_hsi2c_clock_setup(i2c);
 424         /* Initialize the configure registers */
 425         exynos5_i2c_init(i2c);
 426 }
 427
 428 /*
 429  * exynos5_i2c_irq: top level IRQ servicing routine
 430  *
 431  * INT_STATUS registers gives the interrupt details. Further,
 432  * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
 433  * state of the bus.
 434  */
 435 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
 436 {
 437         struct exynos5_i2c *i2c = dev_id;
 438         u32 fifo_level, int_status, fifo_status, trans_status;
 439         unsigned char byte;
 440         int len = 0;
 441
 442         i2c->state = -EINVAL;
 443
 444         spin_lock(&i2c->lock);
 445
 446         int_status = readl(i2c->regs + HSI2C_INT_STATUS);
 447         writel(int_status, i2c->regs + HSI2C_INT_STATUS);
 448
 449         /* handle interrupt related to the transfer status */
 450         if (i2c->variant->hw == HSI2C_EXYNOS7) {
 451                 if (int_status & HSI2C_INT_TRANS_DONE) {
 452                         i2c->trans_done = 1;
 453                         i2c->state = 0;
 454                 } else if (int_status & HSI2C_INT_TRANS_ABORT) {
 455                         dev_dbg(i2c->dev, "Deal with arbitration lose\n");
 456                         i2c->state = -EAGAIN;
 457                         goto stop;
 458                 } else if (int_status & HSI2C_INT_NO_DEV_ACK) {
 459                         dev_dbg(i2c->dev, "No ACK from device\n");
 460                         i2c->state = -ENXIO;
 461                         goto stop;
 462                 } else if (int_status & HSI2C_INT_NO_DEV) {
 463                         dev_dbg(i2c->dev, "No device\n");
 464                         i2c->state = -ENXIO;
 465                         goto stop;
 466                 } else if (int_status & HSI2C_INT_TIMEOUT) {
 467                         dev_dbg(i2c->dev, "Accessing device timed out\n");
 468                         i2c->state = -ETIMEDOUT;
 469                         goto stop;
 470                 }
 471
 472                 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
 473                 if ((trans_status & HSI2C_MASTER_ST_MASK) == HSI2C_MASTER_ST_LOSE) {
 474                         i2c->state = -EAGAIN;
 475                         goto stop;
 476                 }
 477         } else if (int_status & HSI2C_INT_I2C) {
 478                 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
 479                 if (trans_status & HSI2C_NO_DEV_ACK) {
 480                         dev_dbg(i2c->dev, "No ACK from device\n");
 481                         i2c->state = -ENXIO;
 482                         goto stop;
 483                 } else if (trans_status & HSI2C_NO_DEV) {
 484                         dev_dbg(i2c->dev, "No device\n");
 485                         i2c->state = -ENXIO;
 486                         goto stop;
 487                 } else if (trans_status & HSI2C_TRANS_ABORT) {
 488                         dev_dbg(i2c->dev, "Deal with arbitration lose\n");
 489                         i2c->state = -EAGAIN;
 490                         goto stop;
 491                 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
 492                         dev_dbg(i2c->dev, "Accessing device timed out\n");
 493                         i2c->state = -ETIMEDOUT;
 494                         goto stop;
 495                 } else if (trans_status & HSI2C_TRANS_DONE) {
 496                         i2c->trans_done = 1;
 497                         i2c->state = 0;
 498                 }
 499         }
 500
 501         if ((i2c->msg->flags & I2C_M_RD) && (int_status &
 502                         (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
 503                 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
 504                 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
 505                 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
 506
 507                 while (len > 0) {
 508                         byte = (unsigned char)
 509                                 readl(i2c->regs + HSI2C_RX_DATA);
 510                         i2c->msg->buf[i2c->msg_ptr++] = byte;
 511                         len--;
 512                 }
 513                 i2c->state = 0;
 514         } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
 515                 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
 516                 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
 517
 518                 len = i2c->variant->fifo_depth - fifo_level;
 519                 if (len > (i2c->msg->len - i2c->msg_ptr)) {
 520                         u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
 521
 522                         int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN;
 523                         writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
 524                         len = i2c->msg->len - i2c->msg_ptr;
 525                 }
 526
 527                 while (len > 0) {
 528                         byte = i2c->msg->buf[i2c->msg_ptr++];
 529                         writel(byte, i2c->regs + HSI2C_TX_DATA);
 530                         len--;
 531                 }
 532                 i2c->state = 0;
 533         }
 534
 535  stop:
 536         if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
 537             (i2c->state < 0)) {
 538                 writel(0, i2c->regs + HSI2C_INT_ENABLE);
 539                 exynos5_i2c_clr_pend_irq(i2c);
 540                 complete(&i2c->msg_complete);
 541         }
 542
 543         spin_unlock(&i2c->lock);
 544
 545         return IRQ_HANDLED;
 546 }
 547
 548 /*
 549  * exynos5_i2c_wait_bus_idle
 550  *
 551  * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
 552  * cleared.
 553  *
 554  * Returns -EBUSY if the bus cannot be bought to idle
 555  */
 556 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
 557 {
 558         unsigned long stop_time;
 559         u32 trans_status;
 560
 561         /* wait for 100 milli seconds for the bus to be idle */
 562         stop_time = jiffies + msecs_to_jiffies(100) + 1;
 563         do {
 564                 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
 565                 if (!(trans_status & HSI2C_MASTER_BUSY))
 566                         return 0;
 567
 568                 usleep_range(50, 200);
 569         } while (time_before(jiffies, stop_time));
 570
 571         return -EBUSY;
 572 }
 573
 574 /*
 575  * exynos5_i2c_message_start: Configures the bus and starts the xfer
 576  * i2c: struct exynos5_i2c pointer for the current bus
 577  * stop: Enables stop after transfer if set. Set for last transfer of
 578  *       in the list of messages.
 579  *
 580  * Configures the bus for read/write function
 581  * Sets chip address to talk to, message length to be sent.
 582  * Enables appropriate interrupts and sends start xfer command.
 583  */
 584 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
 585 {
 586         u32 i2c_ctl;
 587         u32 int_en = 0;
 588         u32 i2c_auto_conf = 0;
 589         u32 fifo_ctl;
 590         unsigned long flags;
 591         unsigned short trig_lvl;
 592
 593         if (i2c->variant->hw == HSI2C_EXYNOS7)
 594                 int_en |= HSI2C_INT_I2C_TRANS;
 595         else
 596                 int_en |= HSI2C_INT_I2C;
 597
 598         i2c_ctl = readl(i2c->regs + HSI2C_CTL);
 599         i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
 600         fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
 601
 602         if (i2c->msg->flags & I2C_M_RD) {
 603                 i2c_ctl |= HSI2C_RXCHON;
 604
 605                 i2c_auto_conf |= HSI2C_READ_WRITE;
 606
 607                 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
 608                         (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
 609                 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
 610
 611                 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
 612                         HSI2C_INT_TRAILING_EN);
 613         } else {
 614                 i2c_ctl |= HSI2C_TXCHON;
 615
 616                 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
 617                         (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
 618                 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
 619
 620                 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
 621         }
 622
 623         writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR);
 624
 625         writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
 626         writel(i2c_ctl, i2c->regs + HSI2C_CTL);
 627
 628         /*
 629          * Enable interrupts before starting the transfer so that we don't
 630          * miss any INT_I2C interrupts.
 631          */
 632         spin_lock_irqsave(&i2c->lock, flags);
 633         writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
 634
 635         if (stop == 1)
 636                 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
 637         i2c_auto_conf |= i2c->msg->len;
 638         i2c_auto_conf |= HSI2C_MASTER_RUN;
 639         writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
 640         spin_unlock_irqrestore(&i2c->lock, flags);
 641 }
 642
 643 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
 644                               struct i2c_msg *msgs, int stop)
 645 {
 646         unsigned long timeout;
 647         int ret;
 648
 649         i2c->msg = msgs;
 650         i2c->msg_ptr = 0;
 651         i2c->trans_done = 0;
 652
 653         reinit_completion(&i2c->msg_complete);
 654
 655         exynos5_i2c_message_start(i2c, stop);
 656
 657         timeout = wait_for_completion_timeout(&i2c->msg_complete,
 658                                               EXYNOS5_I2C_TIMEOUT);
 659         if (timeout == 0)
 660                 ret = -ETIMEDOUT;
 661         else
 662                 ret = i2c->state;
 663
 664         /*
 665          * If this is the last message to be transfered (stop == 1)
 666          * Then check if the bus can be brought back to idle.
 667          */
 668         if (ret == 0 && stop)
 669                 ret = exynos5_i2c_wait_bus_idle(i2c);
 670
 671         if (ret < 0) {
 672                 exynos5_i2c_reset(i2c);
 673                 if (ret == -ETIMEDOUT)
 674                         dev_warn(i2c->dev, "%s timeout\n",
 675                                  (msgs->flags & I2C_M_RD) ? "rx" : "tx");
 676         }
 677
 678         /* Return the state as in interrupt routine */
 679         return ret;
 680 }
 681
 682 static int exynos5_i2c_xfer(struct i2c_adapter *adap,
 683                         struct i2c_msg *msgs, int num)
 684 {
 685         struct exynos5_i2c *i2c = adap->algo_data;
 686         int i = 0, ret = 0, stop = 0;
 687
 688         if (i2c->suspended) {
 689                 dev_err(i2c->dev, "HS-I2C is not initialized.\n");
 690                 return -EIO;
 691         }
 692
 693         ret = clk_enable(i2c->clk);
 694         if (ret)
 695                 return ret;
 696
 697         for (i = 0; i < num; i++, msgs++) {
 698                 stop = (i == num - 1);
 699
 700                 ret = exynos5_i2c_xfer_msg(i2c, msgs, stop);
 701
 702                 if (ret < 0)
 703                         goto out;
 704         }
 705
 706         if (i == num) {
 707                 ret = num;
 708         } else {
 709                 /* Only one message, cannot access the device */
 710                 if (i == 1)
 711                         ret = -EREMOTEIO;
 712                 else
 713                         ret = i;
 714
 715                 dev_warn(i2c->dev, "xfer message failed\n");
 716         }
 717
 718  out:
 719         clk_disable(i2c->clk);
 720         return ret;
 721 }
 722
 723 static u32 exynos5_i2c_func(struct i2c_adapter *adap)
 724 {
 725         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 726 }
 727
 728 static const struct i2c_algorithm exynos5_i2c_algorithm = {
 729         .master_xfer            = exynos5_i2c_xfer,
 730         .functionality          = exynos5_i2c_func,
 731 };
 732
 733 static int exynos5_i2c_probe(struct platform_device *pdev)
 734 {
 735         struct device_node *np = pdev->dev.of_node;
 736         struct exynos5_i2c *i2c;
 737         struct resource *mem;
 738         unsigned int op_clock;
 739         int ret;
 740
 741         i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
 742         if (!i2c)
 743                 return -ENOMEM;
 744
 745         if (of_property_read_u32(np, "clock-frequency", &op_clock)) {
 746                 i2c->speed_mode = HSI2C_FAST_SPD;
 747                 i2c->fs_clock = HSI2C_FS_TX_CLOCK;
 748         } else {
 749                 if (op_clock >= HSI2C_HS_TX_CLOCK) {
 750                         i2c->speed_mode = HSI2C_HIGH_SPD;
 751                         i2c->fs_clock = HSI2C_FS_TX_CLOCK;
 752                         i2c->hs_clock = op_clock;
 753                 } else {
 754                         i2c->speed_mode = HSI2C_FAST_SPD;
 755                         i2c->fs_clock = op_clock;
 756                 }
 757         }
 758
 759         strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
 760         i2c->adap.owner   = THIS_MODULE;
 761         i2c->adap.algo    = &exynos5_i2c_algorithm;
 762         i2c->adap.retries = 3;
 763
 764         i2c->dev = &pdev->dev;
 765         i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
 766         if (IS_ERR(i2c->clk)) {
 767                 dev_err(&pdev->dev, "cannot get clock\n");
 768                 return -ENOENT;
 769         }
 770
 771         ret = clk_prepare_enable(i2c->clk);
 772         if (ret)
 773                 return ret;
 774
 775         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 776         i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
 777         if (IS_ERR(i2c->regs)) {
 778                 ret = PTR_ERR(i2c->regs);
 779                 goto err_clk;
 780         }
 781
 782         i2c->adap.dev.of_node = np;
 783         i2c->adap.algo_data = i2c;
 784         i2c->adap.dev.parent = &pdev->dev;
 785
 786         /* Clear pending interrupts from u-boot or misc causes */
 787         exynos5_i2c_clr_pend_irq(i2c);
 788
 789         spin_lock_init(&i2c->lock);
 790         init_completion(&i2c->msg_complete);
 791
 792         i2c->irq = ret = platform_get_irq(pdev, 0);
 793         if (ret <= 0) {
 794                 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
 795                 ret = -EINVAL;
 796                 goto err_clk;
 797         }
 798
 799         ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
 800                                 IRQF_NO_SUSPEND | IRQF_ONESHOT,
 801                                 dev_name(&pdev->dev), i2c);
 802
 803         if (ret != 0) {
 804                 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
 805                 goto err_clk;
 806         }
 807
 808         /* Need to check the variant before setting up. */
 809         i2c->variant = exynos5_i2c_get_variant(pdev);
 810
 811         ret = exynos5_hsi2c_clock_setup(i2c);
 812         if (ret)
 813                 goto err_clk;
 814
 815         exynos5_i2c_reset(i2c);
 816
 817         ret = i2c_add_adapter(&i2c->adap);
 818         if (ret < 0)
 819                 goto err_clk;
 820
 821         platform_set_drvdata(pdev, i2c);
 822
 823         clk_disable(i2c->clk);
 824
 825         return 0;
 826
 827  err_clk:
 828         clk_disable_unprepare(i2c->clk);
 829         return ret;
 830 }
 831
 832 static int exynos5_i2c_remove(struct platform_device *pdev)
 833 {
 834         struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
 835
 836         i2c_del_adapter(&i2c->adap);
 837
 838         clk_unprepare(i2c->clk);
 839
 840         return 0;
 841 }
 842
 843 #ifdef CONFIG_PM_SLEEP
 844 static int exynos5_i2c_suspend_noirq(struct device *dev)
 845 {
 846         struct platform_device *pdev = to_platform_device(dev);
 847         struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
 848
 849         i2c->suspended = 1;
 850
 851         clk_unprepare(i2c->clk);
 852
 853         return 0;
 854 }
 855
 856 static int exynos5_i2c_resume_noirq(struct device *dev)
 857 {
 858         struct platform_device *pdev = to_platform_device(dev);
 859         struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
 860         int ret = 0;
 861
 862         ret = clk_prepare_enable(i2c->clk);
 863         if (ret)
 864                 return ret;
 865
 866         ret = exynos5_hsi2c_clock_setup(i2c);
 867         if (ret) {
 868                 clk_disable_unprepare(i2c->clk);
 869                 return ret;
 870         }
 871
 872         exynos5_i2c_init(i2c);
 873         clk_disable(i2c->clk);
 874         i2c->suspended = 0;
 875
 876         return 0;
 877 }
 878 #endif
 879
 880 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
 881         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq,
 882                                       exynos5_i2c_resume_noirq)
 883 };
 884
 885 static struct platform_driver exynos5_i2c_driver = {
 886         .probe          = exynos5_i2c_probe,
 887         .remove         = exynos5_i2c_remove,
 888         .driver         = {
 889                 .name   = "exynos5-hsi2c",
 890                 .pm     = &exynos5_i2c_dev_pm_ops,
 891                 .of_match_table = exynos5_i2c_match,
 892         },
 893 };
 894
 895 module_platform_driver(exynos5_i2c_driver);
 896
 897 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
 898 MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>");
 899 MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>");
 900 MODULE_LICENSE("GPL v2");