drivers/i2c/busses/i2c-eg20t.c

   1 /*
   2  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/i2c.h>
  24 #include <linux/fs.h>
  25 #include <linux/io.h>
  26 #include <linux/types.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/jiffies.h>
  29 #include <linux/pci.h>
  30 #include <linux/mutex.h>
  31 #include <linux/ktime.h>
  32 #include <linux/slab.h>
  33
  34 #define PCH_EVENT_SET   0       /* I2C Interrupt Event Set Status */
  35 #define PCH_EVENT_NONE  1       /* I2C Interrupt Event Clear Status */
  36 #define PCH_MAX_CLK             100000  /* Maximum Clock speed in MHz */
  37 #define PCH_BUFFER_MODE_ENABLE  0x0002  /* flag for Buffer mode enable */
  38 #define PCH_EEPROM_SW_RST_MODE_ENABLE   0x0008  /* EEPROM SW RST enable flag */
  39
  40 #define PCH_I2CSADR     0x00    /* I2C slave address register */
  41 #define PCH_I2CCTL      0x04    /* I2C control register */
  42 #define PCH_I2CSR       0x08    /* I2C status register */
  43 #define PCH_I2CDR       0x0C    /* I2C data register */
  44 #define PCH_I2CMON      0x10    /* I2C bus monitor register */
  45 #define PCH_I2CBC       0x14    /* I2C bus transfer rate setup counter */
  46 #define PCH_I2CMOD      0x18    /* I2C mode register */
  47 #define PCH_I2CBUFSLV   0x1C    /* I2C buffer mode slave address register */
  48 #define PCH_I2CBUFSUB   0x20    /* I2C buffer mode subaddress register */
  49 #define PCH_I2CBUFFOR   0x24    /* I2C buffer mode format register */
  50 #define PCH_I2CBUFCTL   0x28    /* I2C buffer mode control register */
  51 #define PCH_I2CBUFMSK   0x2C    /* I2C buffer mode interrupt mask register */
  52 #define PCH_I2CBUFSTA   0x30    /* I2C buffer mode status register */
  53 #define PCH_I2CBUFLEV   0x34    /* I2C buffer mode level register */
  54 #define PCH_I2CESRFOR   0x38    /* EEPROM software reset mode format register */
  55 #define PCH_I2CESRCTL   0x3C    /* EEPROM software reset mode ctrl register */
  56 #define PCH_I2CESRMSK   0x40    /* EEPROM software reset mode */
  57 #define PCH_I2CESRSTA   0x44    /* EEPROM software reset mode status register */
  58 #define PCH_I2CTMR      0x48    /* I2C timer register */
  59 #define PCH_I2CSRST     0xFC    /* I2C reset register */
  60 #define PCH_I2CNF       0xF8    /* I2C noise filter register */
  61
  62 #define BUS_IDLE_TIMEOUT        20
  63 #define PCH_I2CCTL_I2CMEN       0x0080
  64 #define TEN_BIT_ADDR_DEFAULT    0xF000
  65 #define TEN_BIT_ADDR_MASK       0xF0
  66 #define PCH_START               0x0020
  67 #define PCH_RESTART             0x0004
  68 #define PCH_ESR_START           0x0001
  69 #define PCH_BUFF_START          0x1
  70 #define PCH_REPSTART            0x0004
  71 #define PCH_ACK                 0x0008
  72 #define PCH_GETACK              0x0001
  73 #define CLR_REG                 0x0
  74 #define I2C_RD                  0x1
  75 #define I2CMCF_BIT              0x0080
  76 #define I2CMIF_BIT              0x0002
  77 #define I2CMAL_BIT              0x0010
  78 #define I2CBMFI_BIT             0x0001
  79 #define I2CBMAL_BIT             0x0002
  80 #define I2CBMNA_BIT             0x0004
  81 #define I2CBMTO_BIT             0x0008
  82 #define I2CBMIS_BIT             0x0010
  83 #define I2CESRFI_BIT            0X0001
  84 #define I2CESRTO_BIT            0x0002
  85 #define I2CESRFIIE_BIT          0x1
  86 #define I2CESRTOIE_BIT          0x2
  87 #define I2CBMDZ_BIT             0x0040
  88 #define I2CBMAG_BIT             0x0020
  89 #define I2CMBB_BIT              0x0020
  90 #define BUFFER_MODE_MASK        (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
  91                                 I2CBMTO_BIT | I2CBMIS_BIT)
  92 #define I2C_ADDR_MSK            0xFF
  93 #define I2C_MSB_2B_MSK          0x300
  94 #define FAST_MODE_CLK           400
  95 #define FAST_MODE_EN            0x0001
  96 #define SUB_ADDR_LEN_MAX        4
  97 #define BUF_LEN_MAX             32
  98 #define PCH_BUFFER_MODE         0x1
  99 #define EEPROM_SW_RST_MODE      0x0002
 100 #define NORMAL_INTR_ENBL        0x0300
 101 #define EEPROM_RST_INTR_ENBL    (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
 102 #define EEPROM_RST_INTR_DISBL   0x0
 103 #define BUFFER_MODE_INTR_ENBL   0x001F
 104 #define BUFFER_MODE_INTR_DISBL  0x0
 105 #define NORMAL_MODE             0x0
 106 #define BUFFER_MODE             0x1
 107 #define EEPROM_SR_MODE          0x2
 108 #define I2C_TX_MODE             0x0010
 109 #define PCH_BUF_TX              0xFFF7
 110 #define PCH_BUF_RD              0x0008
 111 #define I2C_ERROR_MASK  (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
 112                         I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
 113 #define I2CMAL_EVENT            0x0001
 114 #define I2CMCF_EVENT            0x0002
 115 #define I2CBMFI_EVENT           0x0004
 116 #define I2CBMAL_EVENT           0x0008
 117 #define I2CBMNA_EVENT           0x0010
 118 #define I2CBMTO_EVENT           0x0020
 119 #define I2CBMIS_EVENT           0x0040
 120 #define I2CESRFI_EVENT          0x0080
 121 #define I2CESRTO_EVENT          0x0100
 122 #define PCI_DEVICE_ID_PCH_I2C   0x8817
 123
 124 #define pch_dbg(adap, fmt, arg...)  \
 125         dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 126
 127 #define pch_err(adap, fmt, arg...)  \
 128         dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 129
 130 #define pch_pci_err(pdev, fmt, arg...)  \
 131         dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
 132
 133 #define pch_pci_dbg(pdev, fmt, arg...)  \
 134         dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
 135
 136 /*
 137 Set the number of I2C instance max
 138 Intel EG20T PCH :               1ch
 139 LAPIS Semiconductor ML7213 IOH :        2ch
 140 LAPIS Semiconductor ML7831 IOH :        1ch
 141 */
 142 #define PCH_I2C_MAX_DEV                 2
 143
 144 /**
 145  * struct i2c_algo_pch_data - for I2C driver functionalities
 146  * @pch_adapter:                stores the reference to i2c_adapter structure
 147  * @p_adapter_info:             stores the reference to adapter_info structure
 148  * @pch_base_address:           specifies the remapped base address
 149  * @pch_buff_mode_en:           specifies if buffer mode is enabled
 150  * @pch_event_flag:             specifies occurrence of interrupt events
 151  * @pch_i2c_xfer_in_progress:   specifies whether the transfer is completed
 152  */
 153 struct i2c_algo_pch_data {
 154         struct i2c_adapter pch_adapter;
 155         struct adapter_info *p_adapter_info;
 156         void __iomem *pch_base_address;
 157         int pch_buff_mode_en;
 158         u32 pch_event_flag;
 159         bool pch_i2c_xfer_in_progress;
 160 };
 161
 162 /**
 163  * struct adapter_info - This structure holds the adapter information for the
 164                          PCH i2c controller
 165  * @pch_data:           stores a list of i2c_algo_pch_data
 166  * @pch_i2c_suspended:  specifies whether the system is suspended or not
 167  *                      perhaps with more lines and words.
 168  * @ch_num:             specifies the number of i2c instance
 169  *
 170  * pch_data has as many elements as maximum I2C channels
 171  */
 172 struct adapter_info {
 173         struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
 174         bool pch_i2c_suspended;
 175         int ch_num;
 176 };
 177
 178
 179 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
 180 static int pch_clk = 50000;     /* specifies I2C clock speed in KHz */
 181 static wait_queue_head_t pch_event;
 182 static DEFINE_MUTEX(pch_mutex);
 183
 184 /* Definition for ML7213 by LAPIS Semiconductor */
 185 #define PCI_VENDOR_ID_ROHM              0x10DB
 186 #define PCI_DEVICE_ID_ML7213_I2C        0x802D
 187 #define PCI_DEVICE_ID_ML7223_I2C        0x8010
 188 #define PCI_DEVICE_ID_ML7831_I2C        0x8817
 189
 190 static DEFINE_PCI_DEVICE_TABLE(pch_pcidev_id) = {
 191         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C),   1, },
 192         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
 193         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
 194         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
 195         {0,}
 196 };
 197
 198 static irqreturn_t pch_i2c_handler(int irq, void *pData);
 199
 200 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
 201 {
 202         u32 val;
 203         val = ioread32(addr + offset);
 204         val |= bitmask;
 205         iowrite32(val, addr + offset);
 206 }
 207
 208 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
 209 {
 210         u32 val;
 211         val = ioread32(addr + offset);
 212         val &= (~bitmask);
 213         iowrite32(val, addr + offset);
 214 }
 215
 216 /**
 217  * pch_i2c_init() - hardware initialization of I2C module
 218  * @adap:       Pointer to struct i2c_algo_pch_data.
 219  */
 220 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
 221 {
 222         void __iomem *p = adap->pch_base_address;
 223         u32 pch_i2cbc;
 224         u32 pch_i2ctmr;
 225         u32 reg_value;
 226
 227         /* reset I2C controller */
 228         iowrite32(0x01, p + PCH_I2CSRST);
 229         msleep(20);
 230         iowrite32(0x0, p + PCH_I2CSRST);
 231
 232         /* Initialize I2C registers */
 233         iowrite32(0x21, p + PCH_I2CNF);
 234
 235         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
 236
 237         if (pch_i2c_speed != 400)
 238                 pch_i2c_speed = 100;
 239
 240         reg_value = PCH_I2CCTL_I2CMEN;
 241         if (pch_i2c_speed == FAST_MODE_CLK) {
 242                 reg_value |= FAST_MODE_EN;
 243                 pch_dbg(adap, "Fast mode enabled\n");
 244         }
 245
 246         if (pch_clk > PCH_MAX_CLK)
 247                 pch_clk = 62500;
 248
 249         pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
 250         /* Set transfer speed in I2CBC */
 251         iowrite32(pch_i2cbc, p + PCH_I2CBC);
 252
 253         pch_i2ctmr = (pch_clk) / 8;
 254         iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
 255
 256         reg_value |= NORMAL_INTR_ENBL;  /* Enable interrupts in normal mode */
 257         iowrite32(reg_value, p + PCH_I2CCTL);
 258
 259         pch_dbg(adap,
 260                 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
 261                 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
 262
 263         init_waitqueue_head(&pch_event);
 264 }
 265
 266 /**
 267  * pch_i2c_wait_for_bus_idle() - check the status of bus.
 268  * @adap:       Pointer to struct i2c_algo_pch_data.
 269  * @timeout:    waiting time counter (ms).
 270  */
 271 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
 272                                      s32 timeout)
 273 {
 274         void __iomem *p = adap->pch_base_address;
 275         int schedule = 0;
 276         unsigned long end = jiffies + msecs_to_jiffies(timeout);
 277
 278         while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
 279                 if (time_after(jiffies, end)) {
 280                         pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 281                         pch_err(adap, "%s: Timeout Error.return%d\n",
 282                                         __func__, -ETIME);
 283                         pch_i2c_init(adap);
 284
 285                         return -ETIME;
 286                 }
 287
 288                 if (!schedule)
 289                         /* Retry after some usecs */
 290                         udelay(5);
 291                 else
 292                         /* Wait a bit more without consuming CPU */
 293                         usleep_range(20, 1000);
 294
 295                 schedule = 1;
 296         }
 297
 298         return 0;
 299 }
 300
 301 /**
 302  * pch_i2c_start() - Generate I2C start condition in normal mode.
 303  * @adap:       Pointer to struct i2c_algo_pch_data.
 304  *
 305  * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
 306  */
 307 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
 308 {
 309         void __iomem *p = adap->pch_base_address;
 310         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 311         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 312 }
 313
 314 /**
 315  * pch_i2c_stop() - generate stop condition in normal mode.
 316  * @adap:       Pointer to struct i2c_algo_pch_data.
 317  */
 318 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
 319 {
 320         void __iomem *p = adap->pch_base_address;
 321         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 322         /* clear the start bit */
 323         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 324 }
 325
 326 static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
 327 {
 328         long ret;
 329         void __iomem *p = adap->pch_base_address;
 330
 331         ret = wait_event_timeout(pch_event,
 332                         (adap->pch_event_flag != 0), msecs_to_jiffies(1000));
 333         if (!ret) {
 334                 pch_err(adap, "%s:wait-event timeout\n", __func__);
 335                 adap->pch_event_flag = 0;
 336                 pch_i2c_stop(adap);
 337                 pch_i2c_init(adap);
 338                 return -ETIMEDOUT;
 339         }
 340
 341         if (adap->pch_event_flag & I2C_ERROR_MASK) {
 342                 pch_err(adap, "Lost Arbitration\n");
 343                 adap->pch_event_flag = 0;
 344                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
 345                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
 346                 pch_i2c_init(adap);
 347                 return -EAGAIN;
 348         }
 349
 350         adap->pch_event_flag = 0;
 351
 352         if (ioread32(p + PCH_I2CSR) & PCH_GETACK) {
 353                 pch_dbg(adap, "Receive NACK for slave address setting\n");
 354                 return -ENXIO;
 355         }
 356
 357         return 0;
 358 }
 359
 360 /**
 361  * pch_i2c_repstart() - generate repeated start condition in normal mode
 362  * @adap:       Pointer to struct i2c_algo_pch_data.
 363  */
 364 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
 365 {
 366         void __iomem *p = adap->pch_base_address;
 367         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 368         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
 369 }
 370
 371 /**
 372  * pch_i2c_writebytes() - write data to I2C bus in normal mode
 373  * @i2c_adap:   Pointer to the struct i2c_adapter.
 374  * @last:       specifies whether last message or not.
 375  *              In the case of compound mode it will be 1 for last message,
 376  *              otherwise 0.
 377  * @first:      specifies whether first message or not.
 378  *              1 for first message otherwise 0.
 379  */
 380 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
 381                               struct i2c_msg *msgs, u32 last, u32 first)
 382 {
 383         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 384         u8 *buf;
 385         u32 length;
 386         u32 addr;
 387         u32 addr_2_msb;
 388         u32 addr_8_lsb;
 389         s32 wrcount;
 390         s32 rtn;
 391         void __iomem *p = adap->pch_base_address;
 392
 393         length = msgs->len;
 394         buf = msgs->buf;
 395         addr = msgs->addr;
 396
 397         /* enable master tx */
 398         pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 399
 400         pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
 401                 length);
 402
 403         if (first) {
 404                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 405                         return -ETIME;
 406         }
 407
 408         if (msgs->flags & I2C_M_TEN) {
 409                 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
 410                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 411                 if (first)
 412                         pch_i2c_start(adap);
 413
 414                 rtn = pch_i2c_wait_for_check_xfer(adap);
 415                 if (rtn)
 416                         return rtn;
 417
 418                 addr_8_lsb = (addr & I2C_ADDR_MSK);
 419                 iowrite32(addr_8_lsb, p + PCH_I2CDR);
 420         } else {
 421                 /* set 7 bit slave address and R/W bit as 0 */
 422                 iowrite32(addr << 1, p + PCH_I2CDR);
 423                 if (first)
 424                         pch_i2c_start(adap);
 425         }
 426
 427         rtn = pch_i2c_wait_for_check_xfer(adap);
 428         if (rtn)
 429                 return rtn;
 430
 431         for (wrcount = 0; wrcount < length; ++wrcount) {
 432                 /* write buffer value to I2C data register */
 433                 iowrite32(buf[wrcount], p + PCH_I2CDR);
 434                 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
 435
 436                 rtn = pch_i2c_wait_for_check_xfer(adap);
 437                 if (rtn)
 438                         return rtn;
 439
 440                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT);
 441                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
 442         }
 443
 444         /* check if this is the last message */
 445         if (last)
 446                 pch_i2c_stop(adap);
 447         else
 448                 pch_i2c_repstart(adap);
 449
 450         pch_dbg(adap, "return=%d\n", wrcount);
 451
 452         return wrcount;
 453 }
 454
 455 /**
 456  * pch_i2c_sendack() - send ACK
 457  * @adap:       Pointer to struct i2c_algo_pch_data.
 458  */
 459 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
 460 {
 461         void __iomem *p = adap->pch_base_address;
 462         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 463         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 464 }
 465
 466 /**
 467  * pch_i2c_sendnack() - send NACK
 468  * @adap:       Pointer to struct i2c_algo_pch_data.
 469  */
 470 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
 471 {
 472         void __iomem *p = adap->pch_base_address;
 473         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 474         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 475 }
 476
 477 /**
 478  * pch_i2c_restart() - Generate I2C restart condition in normal mode.
 479  * @adap:       Pointer to struct i2c_algo_pch_data.
 480  *
 481  * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
 482  */
 483 static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
 484 {
 485         void __iomem *p = adap->pch_base_address;
 486         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 487         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
 488 }
 489
 490 /**
 491  * pch_i2c_readbytes() - read data  from I2C bus in normal mode.
 492  * @i2c_adap:   Pointer to the struct i2c_adapter.
 493  * @msgs:       Pointer to i2c_msg structure.
 494  * @last:       specifies whether last message or not.
 495  * @first:      specifies whether first message or not.
 496  */
 497 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
 498                              u32 last, u32 first)
 499 {
 500         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 501
 502         u8 *buf;
 503         u32 count;
 504         u32 length;
 505         u32 addr;
 506         u32 addr_2_msb;
 507         u32 addr_8_lsb;
 508         void __iomem *p = adap->pch_base_address;
 509         s32 rtn;
 510
 511         length = msgs->len;
 512         buf = msgs->buf;
 513         addr = msgs->addr;
 514
 515         /* enable master reception */
 516         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 517
 518         if (first) {
 519                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 520                         return -ETIME;
 521         }
 522
 523         if (msgs->flags & I2C_M_TEN) {
 524                 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
 525                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 526                 if (first)
 527                         pch_i2c_start(adap);
 528
 529                 rtn = pch_i2c_wait_for_check_xfer(adap);
 530                 if (rtn)
 531                         return rtn;
 532
 533                 addr_8_lsb = (addr & I2C_ADDR_MSK);
 534                 iowrite32(addr_8_lsb, p + PCH_I2CDR);
 535
 536                 pch_i2c_restart(adap);
 537
 538                 rtn = pch_i2c_wait_for_check_xfer(adap);
 539                 if (rtn)
 540                         return rtn;
 541
 542                 addr_2_msb |= I2C_RD;
 543                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 544         } else {
 545                 /* 7 address bits + R/W bit */
 546                 addr = (((addr) << 1) | (I2C_RD));
 547                 iowrite32(addr, p + PCH_I2CDR);
 548         }
 549
 550         /* check if it is the first message */
 551         if (first)
 552                 pch_i2c_start(adap);
 553
 554         rtn = pch_i2c_wait_for_check_xfer(adap);
 555         if (rtn)
 556                 return rtn;
 557
 558         if (length == 0) {
 559                 pch_i2c_stop(adap);
 560                 ioread32(p + PCH_I2CDR); /* Dummy read needs */
 561
 562                 count = length;
 563         } else {
 564                 int read_index;
 565                 int loop;
 566                 pch_i2c_sendack(adap);
 567
 568                 /* Dummy read */
 569                 for (loop = 1, read_index = 0; loop < length; loop++) {
 570                         buf[read_index] = ioread32(p + PCH_I2CDR);
 571
 572                         if (loop != 1)
 573                                 read_index++;
 574
 575                         rtn = pch_i2c_wait_for_check_xfer(adap);
 576                         if (rtn)
 577                                 return rtn;
 578                 }       /* end for */
 579
 580                 pch_i2c_sendnack(adap);
 581
 582                 buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
 583
 584                 if (length != 1)
 585                         read_index++;
 586
 587                 rtn = pch_i2c_wait_for_check_xfer(adap);
 588                 if (rtn)
 589                         return rtn;
 590
 591                 if (last)
 592                         pch_i2c_stop(adap);
 593                 else
 594                         pch_i2c_repstart(adap);
 595
 596                 buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
 597                 count = read_index;
 598         }
 599
 600         return count;
 601 }
 602
 603 /**
 604  * pch_i2c_cb() - Interrupt handler Call back function
 605  * @adap:       Pointer to struct i2c_algo_pch_data.
 606  */
 607 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
 608 {
 609         u32 sts;
 610         void __iomem *p = adap->pch_base_address;
 611
 612         sts = ioread32(p + PCH_I2CSR);
 613         sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
 614         if (sts & I2CMAL_BIT)
 615                 adap->pch_event_flag |= I2CMAL_EVENT;
 616
 617         if (sts & I2CMCF_BIT)
 618                 adap->pch_event_flag |= I2CMCF_EVENT;
 619
 620         /* clear the applicable bits */
 621         pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
 622
 623         pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 624
 625         wake_up(&pch_event);
 626 }
 627
 628 /**
 629  * pch_i2c_handler() - interrupt handler for the PCH I2C controller
 630  * @irq:        irq number.
 631  * @pData:      cookie passed back to the handler function.
 632  */
 633 static irqreturn_t pch_i2c_handler(int irq, void *pData)
 634 {
 635         u32 reg_val;
 636         int flag;
 637         int i;
 638         struct adapter_info *adap_info = pData;
 639         void __iomem *p;
 640         u32 mode;
 641
 642         for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
 643                 p = adap_info->pch_data[i].pch_base_address;
 644                 mode = ioread32(p + PCH_I2CMOD);
 645                 mode &= BUFFER_MODE | EEPROM_SR_MODE;
 646                 if (mode != NORMAL_MODE) {
 647                         pch_err(adap_info->pch_data,
 648                                 "I2C-%d mode(%d) is not supported\n", mode, i);
 649                         continue;
 650                 }
 651                 reg_val = ioread32(p + PCH_I2CSR);
 652                 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
 653                         pch_i2c_cb(&adap_info->pch_data[i]);
 654                         flag = 1;
 655                 }
 656         }
 657
 658         return flag ? IRQ_HANDLED : IRQ_NONE;
 659 }
 660
 661 /**
 662  * pch_i2c_xfer() - Reading adnd writing data through I2C bus
 663  * @i2c_adap:   Pointer to the struct i2c_adapter.
 664  * @msgs:       Pointer to i2c_msg structure.
 665  * @num:        number of messages.
 666  */
 667 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
 668                         struct i2c_msg *msgs, s32 num)
 669 {
 670         struct i2c_msg *pmsg;
 671         u32 i = 0;
 672         u32 status;
 673         s32 ret;
 674
 675         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 676
 677         ret = mutex_lock_interruptible(&pch_mutex);
 678         if (ret)
 679                 return ret;
 680
 681         if (adap->p_adapter_info->pch_i2c_suspended) {
 682                 mutex_unlock(&pch_mutex);
 683                 return -EBUSY;
 684         }
 685
 686         pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
 687                 adap->p_adapter_info->pch_i2c_suspended);
 688         /* transfer not completed */
 689         adap->pch_i2c_xfer_in_progress = true;
 690
 691         for (i = 0; i < num && ret >= 0; i++) {
 692                 pmsg = &msgs[i];
 693                 pmsg->flags |= adap->pch_buff_mode_en;
 694                 status = pmsg->flags;
 695                 pch_dbg(adap,
 696                         "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
 697
 698                 if ((status & (I2C_M_RD)) != false) {
 699                         ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
 700                                                 (i == 0));
 701                 } else {
 702                         ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
 703                                                  (i == 0));
 704                 }
 705         }
 706
 707         adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
 708
 709         mutex_unlock(&pch_mutex);
 710
 711         return (ret < 0) ? ret : num;
 712 }
 713
 714 /**
 715  * pch_i2c_func() - return the functionality of the I2C driver
 716  * @adap:       Pointer to struct i2c_algo_pch_data.
 717  */
 718 static u32 pch_i2c_func(struct i2c_adapter *adap)
 719 {
 720         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 721 }
 722
 723 static struct i2c_algorithm pch_algorithm = {
 724         .master_xfer = pch_i2c_xfer,
 725         .functionality = pch_i2c_func
 726 };
 727
 728 /**
 729  * pch_i2c_disbl_int() - Disable PCH I2C interrupts
 730  * @adap:       Pointer to struct i2c_algo_pch_data.
 731  */
 732 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
 733 {
 734         void __iomem *p = adap->pch_base_address;
 735
 736         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
 737
 738         iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
 739
 740         iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
 741 }
 742
 743 static int pch_i2c_probe(struct pci_dev *pdev,
 744                                    const struct pci_device_id *id)
 745 {
 746         void __iomem *base_addr;
 747         int ret;
 748         int i, j;
 749         struct adapter_info *adap_info;
 750         struct i2c_adapter *pch_adap;
 751
 752         pch_pci_dbg(pdev, "Entered.\n");
 753
 754         adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
 755         if (adap_info == NULL) {
 756                 pch_pci_err(pdev, "Memory allocation FAILED\n");
 757                 return -ENOMEM;
 758         }
 759
 760         ret = pci_enable_device(pdev);
 761         if (ret) {
 762                 pch_pci_err(pdev, "pci_enable_device FAILED\n");
 763                 goto err_pci_enable;
 764         }
 765
 766         ret = pci_request_regions(pdev, KBUILD_MODNAME);
 767         if (ret) {
 768                 pch_pci_err(pdev, "pci_request_regions FAILED\n");
 769                 goto err_pci_req;
 770         }
 771
 772         base_addr = pci_iomap(pdev, 1, 0);
 773
 774         if (base_addr == NULL) {
 775                 pch_pci_err(pdev, "pci_iomap FAILED\n");
 776                 ret = -ENOMEM;
 777                 goto err_pci_iomap;
 778         }
 779
 780         /* Set the number of I2C channel instance */
 781         adap_info->ch_num = id->driver_data;
 782
 783         ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
 784                   KBUILD_MODNAME, adap_info);
 785         if (ret) {
 786                 pch_pci_err(pdev, "request_irq FAILED\n");
 787                 goto err_request_irq;
 788         }
 789
 790         for (i = 0; i < adap_info->ch_num; i++) {
 791                 pch_adap = &adap_info->pch_data[i].pch_adapter;
 792                 adap_info->pch_i2c_suspended = false;
 793
 794                 adap_info->pch_data[i].p_adapter_info = adap_info;
 795
 796                 pch_adap->owner = THIS_MODULE;
 797                 pch_adap->class = I2C_CLASS_HWMON;
 798                 strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
 799                 pch_adap->algo = &pch_algorithm;
 800                 pch_adap->algo_data = &adap_info->pch_data[i];
 801
 802                 /* base_addr + offset; */
 803                 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
 804
 805                 pch_adap->dev.parent = &pdev->dev;
 806
 807                 pch_i2c_init(&adap_info->pch_data[i]);
 808
 809                 pch_adap->nr = i;
 810                 ret = i2c_add_numbered_adapter(pch_adap);
 811                 if (ret) {
 812                         pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
 813                         goto err_add_adapter;
 814                 }
 815         }
 816
 817         pci_set_drvdata(pdev, adap_info);
 818         pch_pci_dbg(pdev, "returns %d.\n", ret);
 819         return 0;
 820
 821 err_add_adapter:
 822         for (j = 0; j < i; j++)
 823                 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
 824         free_irq(pdev->irq, adap_info);
 825 err_request_irq:
 826         pci_iounmap(pdev, base_addr);
 827 err_pci_iomap:
 828         pci_release_regions(pdev);
 829 err_pci_req:
 830         pci_disable_device(pdev);
 831 err_pci_enable:
 832         kfree(adap_info);
 833         return ret;
 834 }
 835
 836 static void pch_i2c_remove(struct pci_dev *pdev)
 837 {
 838         int i;
 839         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 840
 841         free_irq(pdev->irq, adap_info);
 842
 843         for (i = 0; i < adap_info->ch_num; i++) {
 844                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 845                 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
 846         }
 847
 848         if (adap_info->pch_data[0].pch_base_address)
 849                 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
 850
 851         for (i = 0; i < adap_info->ch_num; i++)
 852                 adap_info->pch_data[i].pch_base_address = NULL;
 853
 854         pci_release_regions(pdev);
 855
 856         pci_disable_device(pdev);
 857         kfree(adap_info);
 858 }
 859
 860 #ifdef CONFIG_PM
 861 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
 862 {
 863         int ret;
 864         int i;
 865         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 866         void __iomem *p = adap_info->pch_data[0].pch_base_address;
 867
 868         adap_info->pch_i2c_suspended = true;
 869
 870         for (i = 0; i < adap_info->ch_num; i++) {
 871                 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
 872                         /* Wait until all channel transfers are completed */
 873                         msleep(20);
 874                 }
 875         }
 876
 877         /* Disable the i2c interrupts */
 878         for (i = 0; i < adap_info->ch_num; i++)
 879                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 880
 881         pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
 882                 "invoked function pch_i2c_disbl_int successfully\n",
 883                 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
 884                 ioread32(p + PCH_I2CESRSTA));
 885
 886         ret = pci_save_state(pdev);
 887
 888         if (ret) {
 889                 pch_pci_err(pdev, "pci_save_state\n");
 890                 return ret;
 891         }
 892
 893         pci_enable_wake(pdev, PCI_D3hot, 0);
 894         pci_disable_device(pdev);
 895         pci_set_power_state(pdev, pci_choose_state(pdev, state));
 896
 897         return 0;
 898 }
 899
 900 static int pch_i2c_resume(struct pci_dev *pdev)
 901 {
 902         int i;
 903         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 904
 905         pci_set_power_state(pdev, PCI_D0);
 906         pci_restore_state(pdev);
 907
 908         if (pci_enable_device(pdev) < 0) {
 909                 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
 910                 return -EIO;
 911         }
 912
 913         pci_enable_wake(pdev, PCI_D3hot, 0);
 914
 915         for (i = 0; i < adap_info->ch_num; i++)
 916                 pch_i2c_init(&adap_info->pch_data[i]);
 917
 918         adap_info->pch_i2c_suspended = false;
 919
 920         return 0;
 921 }
 922 #else
 923 #define pch_i2c_suspend NULL
 924 #define pch_i2c_resume NULL
 925 #endif
 926
 927 static struct pci_driver pch_pcidriver = {
 928         .name = KBUILD_MODNAME,
 929         .id_table = pch_pcidev_id,
 930         .probe = pch_i2c_probe,
 931         .remove = pch_i2c_remove,
 932         .suspend = pch_i2c_suspend,
 933         .resume = pch_i2c_resume
 934 };
 935
 936 module_pci_driver(pch_pcidriver);
 937
 938 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
 939 MODULE_LICENSE("GPL");
 940 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
 941 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
 942 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));