drivers/i2c/busses/i2c-designware-master.c

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  *
  10  * ----------------------------------------------------------------------------
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  * ----------------------------------------------------------------------------
  22  *
  23  */
  24 #include <linux/delay.h>
  25 #include <linux/err.h>
  26 #include <linux/errno.h>
  27 #include <linux/export.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/i2c.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/module.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/reset.h>
  35
  36 #include "i2c-designware-core.h"
  37
  38 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
  39 {
  40         /* Configure Tx/Rx FIFO threshold levels */
  41         dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
  42         dw_writel(dev, 0, DW_IC_RX_TL);
  43
  44         /* Configure the I2C master */
  45         dw_writel(dev, dev->master_cfg, DW_IC_CON);
  46 }
  47
  48 /**
  49  * i2c_dw_init() - Initialize the designware I2C master hardware
  50  * @dev: device private data
  51  *
  52  * This functions configures and enables the I2C master.
  53  * This function is called during I2C init function, and in case of timeout at
  54  * run time.
  55  */
  56 static int i2c_dw_init_master(struct dw_i2c_dev *dev)
  57 {
  58         u32 hcnt, lcnt;
  59         u32 reg, comp_param1;
  60         u32 sda_falling_time, scl_falling_time;
  61         int ret;
  62
  63         ret = i2c_dw_acquire_lock(dev);
  64         if (ret)
  65                 return ret;
  66
  67         reg = dw_readl(dev, DW_IC_COMP_TYPE);
  68         if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
  69                 /* Configure register endianess access */
  70                 dev->flags |= ACCESS_SWAP;
  71         } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
  72                 /* Configure register access mode 16bit */
  73                 dev->flags |= ACCESS_16BIT;
  74         } else if (reg != DW_IC_COMP_TYPE_VALUE) {
  75                 dev_err(dev->dev,
  76                         "Unknown Synopsys component type: 0x%08x\n", reg);
  77                 i2c_dw_release_lock(dev);
  78                 return -ENODEV;
  79         }
  80
  81         comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
  82
  83         /* Disable the adapter */
  84         __i2c_dw_disable(dev);
  85
  86         /* Set standard and fast speed deviders for high/low periods */
  87
  88         sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
  89         scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
  90
  91         /* Set SCL timing parameters for standard-mode */
  92         if (dev->ss_hcnt && dev->ss_lcnt) {
  93                 hcnt = dev->ss_hcnt;
  94                 lcnt = dev->ss_lcnt;
  95         } else {
  96                 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
  97                                         4000,   /* tHD;STA = tHIGH = 4.0 us */
  98                                         sda_falling_time,
  99                                         0,      /* 0: DW default, 1: Ideal */
 100                                         0);     /* No offset */
 101                 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
 102                                         4700,   /* tLOW = 4.7 us */
 103                                         scl_falling_time,
 104                                         0);     /* No offset */
 105         }
 106         dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
 107         dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
 108         dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 109
 110         /* Set SCL timing parameters for fast-mode or fast-mode plus */
 111         if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) {
 112                 hcnt = dev->fp_hcnt;
 113                 lcnt = dev->fp_lcnt;
 114         } else if (dev->fs_hcnt && dev->fs_lcnt) {
 115                 hcnt = dev->fs_hcnt;
 116                 lcnt = dev->fs_lcnt;
 117         } else {
 118                 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
 119                                         600,    /* tHD;STA = tHIGH = 0.6 us */
 120                                         sda_falling_time,
 121                                         0,      /* 0: DW default, 1: Ideal */
 122                                         0);     /* No offset */
 123                 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
 124                                         1300,   /* tLOW = 1.3 us */
 125                                         scl_falling_time,
 126                                         0);     /* No offset */
 127         }
 128         dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
 129         dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
 130         dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 131
 132         if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
 133                 DW_IC_CON_SPEED_HIGH) {
 134                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 135                         != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
 136                         dev_err(dev->dev, "High Speed not supported!\n");
 137                         dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
 138                         dev->master_cfg |= DW_IC_CON_SPEED_FAST;
 139                 } else if (dev->hs_hcnt && dev->hs_lcnt) {
 140                         hcnt = dev->hs_hcnt;
 141                         lcnt = dev->hs_lcnt;
 142                         dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT);
 143                         dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT);
 144                         dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n",
 145                                 hcnt, lcnt);
 146                 }
 147         }
 148
 149         /* Configure SDA Hold Time if required */
 150         reg = dw_readl(dev, DW_IC_COMP_VERSION);
 151         if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
 152                 if (!dev->sda_hold_time) {
 153                         /* Keep previous hold time setting if no one set it */
 154                         dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
 155                 }
 156                 /*
 157                  * Workaround for avoiding TX arbitration lost in case I2C
 158                  * slave pulls SDA down "too quickly" after falling egde of
 159                  * SCL by enabling non-zero SDA RX hold. Specification says it
 160                  * extends incoming SDA low to high transition while SCL is
 161                  * high but it apprears to help also above issue.
 162                  */
 163                 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
 164                         dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
 165                 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
 166         } else if (dev->sda_hold_time) {
 167                 dev_warn(dev->dev,
 168                         "Hardware too old to adjust SDA hold time.\n");
 169         }
 170
 171         i2c_dw_configure_fifo_master(dev);
 172         i2c_dw_release_lock(dev);
 173
 174         return 0;
 175 }
 176
 177 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 178 {
 179         struct i2c_msg *msgs = dev->msgs;
 180         u32 ic_con, ic_tar = 0;
 181
 182         /* Disable the adapter */
 183         __i2c_dw_disable(dev);
 184
 185         /* If the slave address is ten bit address, enable 10BITADDR */
 186         ic_con = dw_readl(dev, DW_IC_CON);
 187         if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
 188                 ic_con |= DW_IC_CON_10BITADDR_MASTER;
 189                 /*
 190                  * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
 191                  * mode has to be enabled via bit 12 of IC_TAR register.
 192                  * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
 193                  * detected from registers.
 194                  */
 195                 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
 196         } else {
 197                 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
 198         }
 199
 200         dw_writel(dev, ic_con, DW_IC_CON);
 201
 202         /*
 203          * Set the slave (target) address and enable 10-bit addressing mode
 204          * if applicable.
 205          */
 206         dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
 207
 208         /* Enforce disabled interrupts (due to HW issues) */
 209         i2c_dw_disable_int(dev);
 210
 211         /* Enable the adapter */
 212         __i2c_dw_enable(dev);
 213
 214         /* Dummy read to avoid the register getting stuck on Bay Trail */
 215         dw_readl(dev, DW_IC_ENABLE_STATUS);
 216
 217         /* Clear and enable interrupts */
 218         dw_readl(dev, DW_IC_CLR_INTR);
 219         dw_writel(dev, DW_IC_INTR_MASTER_MASK, DW_IC_INTR_MASK);
 220 }
 221
 222 /*
 223  * Initiate (and continue) low level master read/write transaction.
 224  * This function is only called from i2c_dw_isr, and pumping i2c_msg
 225  * messages into the tx buffer.  Even if the size of i2c_msg data is
 226  * longer than the size of the tx buffer, it handles everything.
 227  */
 228 static void
 229 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 230 {
 231         struct i2c_msg *msgs = dev->msgs;
 232         u32 intr_mask;
 233         int tx_limit, rx_limit;
 234         u32 addr = msgs[dev->msg_write_idx].addr;
 235         u32 buf_len = dev->tx_buf_len;
 236         u8 *buf = dev->tx_buf;
 237         bool need_restart = false;
 238
 239         intr_mask = DW_IC_INTR_MASTER_MASK;
 240
 241         for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
 242                 u32 flags = msgs[dev->msg_write_idx].flags;
 243
 244                 /*
 245                  * If target address has changed, we need to
 246                  * reprogram the target address in the I2C
 247                  * adapter when we are done with this transfer.
 248                  */
 249                 if (msgs[dev->msg_write_idx].addr != addr) {
 250                         dev_err(dev->dev,
 251                                 "%s: invalid target address\n", __func__);
 252                         dev->msg_err = -EINVAL;
 253                         break;
 254                 }
 255
 256                 if (msgs[dev->msg_write_idx].len == 0) {
 257                         dev_err(dev->dev,
 258                                 "%s: invalid message length\n", __func__);
 259                         dev->msg_err = -EINVAL;
 260                         break;
 261                 }
 262
 263                 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
 264                         /* new i2c_msg */
 265                         buf = msgs[dev->msg_write_idx].buf;
 266                         buf_len = msgs[dev->msg_write_idx].len;
 267
 268                         /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
 269                          * IC_RESTART_EN are set, we must manually
 270                          * set restart bit between messages.
 271                          */
 272                         if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
 273                                         (dev->msg_write_idx > 0))
 274                                 need_restart = true;
 275                 }
 276
 277                 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
 278                 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
 279
 280                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
 281                         u32 cmd = 0;
 282
 283                         /*
 284                          * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
 285                          * manually set the stop bit. However, it cannot be
 286                          * detected from the registers so we set it always
 287                          * when writing/reading the last byte.
 288                          */
 289
 290                         /*
 291                          * i2c-core always sets the buffer length of
 292                          * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
 293                          * be adjusted when receiving the first byte.
 294                          * Thus we can't stop the transaction here.
 295                          */
 296                         if (dev->msg_write_idx == dev->msgs_num - 1 &&
 297                             buf_len == 1 && !(flags & I2C_M_RECV_LEN))
 298                                 cmd |= BIT(9);
 299
 300                         if (need_restart) {
 301                                 cmd |= BIT(10);
 302                                 need_restart = false;
 303                         }
 304
 305                         if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 306
 307                                 /* Avoid rx buffer overrun */
 308                                 if (dev->rx_outstanding >= dev->rx_fifo_depth)
 309                                         break;
 310
 311                                 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
 312                                 rx_limit--;
 313                                 dev->rx_outstanding++;
 314                         } else
 315                                 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
 316                         tx_limit--; buf_len--;
 317                 }
 318
 319                 dev->tx_buf = buf;
 320                 dev->tx_buf_len = buf_len;
 321
 322                 /*
 323                  * Because we don't know the buffer length in the
 324                  * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
 325                  * the transaction here.
 326                  */
 327                 if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
 328                         /* more bytes to be written */
 329                         dev->status |= STATUS_WRITE_IN_PROGRESS;
 330                         break;
 331                 } else
 332                         dev->status &= ~STATUS_WRITE_IN_PROGRESS;
 333         }
 334
 335         /*
 336          * If i2c_msg index search is completed, we don't need TX_EMPTY
 337          * interrupt any more.
 338          */
 339         if (dev->msg_write_idx == dev->msgs_num)
 340                 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 341
 342         if (dev->msg_err)
 343                 intr_mask = 0;
 344
 345         dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
 346 }
 347
 348 static u8
 349 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
 350 {
 351         struct i2c_msg *msgs = dev->msgs;
 352         u32 flags = msgs[dev->msg_read_idx].flags;
 353
 354         /*
 355          * Adjust the buffer length and mask the flag
 356          * after receiving the first byte.
 357          */
 358         len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
 359         dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
 360         msgs[dev->msg_read_idx].len = len;
 361         msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
 362
 363         return len;
 364 }
 365
 366 static void
 367 i2c_dw_read(struct dw_i2c_dev *dev)
 368 {
 369         struct i2c_msg *msgs = dev->msgs;
 370         int rx_valid;
 371
 372         for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
 373                 u32 len;
 374                 u8 *buf;
 375
 376                 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
 377                         continue;
 378
 379                 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 380                         len = msgs[dev->msg_read_idx].len;
 381                         buf = msgs[dev->msg_read_idx].buf;
 382                 } else {
 383                         len = dev->rx_buf_len;
 384                         buf = dev->rx_buf;
 385                 }
 386
 387                 rx_valid = dw_readl(dev, DW_IC_RXFLR);
 388
 389                 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
 390                         u32 flags = msgs[dev->msg_read_idx].flags;
 391
 392                         *buf = dw_readl(dev, DW_IC_DATA_CMD);
 393                         /* Ensure length byte is a valid value */
 394                         if (flags & I2C_M_RECV_LEN &&
 395                                 *buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) {
 396                                 len = i2c_dw_recv_len(dev, *buf);
 397                         }
 398                         buf++;
 399                         dev->rx_outstanding--;
 400                 }
 401
 402                 if (len > 0) {
 403                         dev->status |= STATUS_READ_IN_PROGRESS;
 404                         dev->rx_buf_len = len;
 405                         dev->rx_buf = buf;
 406                         return;
 407                 } else
 408                         dev->status &= ~STATUS_READ_IN_PROGRESS;
 409         }
 410 }
 411
 412 /*
 413  * Prepare controller for a transaction and call i2c_dw_xfer_msg.
 414  */
 415 static int
 416 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 417 {
 418         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 419         int ret;
 420
 421         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 422
 423         pm_runtime_get_sync(dev->dev);
 424
 425         reinit_completion(&dev->cmd_complete);
 426         dev->msgs = msgs;
 427         dev->msgs_num = num;
 428         dev->cmd_err = 0;
 429         dev->msg_write_idx = 0;
 430         dev->msg_read_idx = 0;
 431         dev->msg_err = 0;
 432         dev->status = STATUS_IDLE;
 433         dev->abort_source = 0;
 434         dev->rx_outstanding = 0;
 435
 436         ret = i2c_dw_acquire_lock(dev);
 437         if (ret)
 438                 goto done_nolock;
 439
 440         ret = i2c_dw_wait_bus_not_busy(dev);
 441         if (ret < 0)
 442                 goto done;
 443
 444         /* Start the transfers */
 445         i2c_dw_xfer_init(dev);
 446
 447         /* Wait for tx to complete */
 448         if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
 449                 dev_err(dev->dev, "controller timed out\n");
 450                 /* i2c_dw_init implicitly disables the adapter */
 451                 i2c_recover_bus(&dev->adapter);
 452                 i2c_dw_init_master(dev);
 453                 ret = -ETIMEDOUT;
 454                 goto done;
 455         }
 456
 457         /*
 458          * We must disable the adapter before returning and signaling the end
 459          * of the current transfer. Otherwise the hardware might continue
 460          * generating interrupts which in turn causes a race condition with
 461          * the following transfer.  Needs some more investigation if the
 462          * additional interrupts are a hardware bug or this driver doesn't
 463          * handle them correctly yet.
 464          */
 465         __i2c_dw_disable_nowait(dev);
 466
 467         if (dev->msg_err) {
 468                 ret = dev->msg_err;
 469                 goto done;
 470         }
 471
 472         /* No error */
 473         if (likely(!dev->cmd_err && !dev->status)) {
 474                 ret = num;
 475                 goto done;
 476         }
 477
 478         /* We have an error */
 479         if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
 480                 ret = i2c_dw_handle_tx_abort(dev);
 481                 goto done;
 482         }
 483
 484         if (dev->status)
 485                 dev_err(dev->dev,
 486                         "transfer terminated early - interrupt latency too high?\n");
 487
 488         ret = -EIO;
 489
 490 done:
 491         i2c_dw_release_lock(dev);
 492
 493 done_nolock:
 494         pm_runtime_mark_last_busy(dev->dev);
 495         pm_runtime_put_autosuspend(dev->dev);
 496
 497         return ret;
 498 }
 499
 500 static const struct i2c_algorithm i2c_dw_algo = {
 501         .master_xfer = i2c_dw_xfer,
 502         .functionality = i2c_dw_func,
 503 };
 504
 505 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 506 {
 507         u32 stat;
 508
 509         /*
 510          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 511          * Ths unmasked raw version of interrupt status bits are available
 512          * in the IC_RAW_INTR_STAT register.
 513          *
 514          * That is,
 515          *   stat = dw_readl(IC_INTR_STAT);
 516          * equals to,
 517          *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
 518          *
 519          * The raw version might be useful for debugging purposes.
 520          */
 521         stat = dw_readl(dev, DW_IC_INTR_STAT);
 522
 523         /*
 524          * Do not use the IC_CLR_INTR register to clear interrupts, or
 525          * you'll miss some interrupts, triggered during the period from
 526          * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
 527          *
 528          * Instead, use the separately-prepared IC_CLR_* registers.
 529          */
 530         if (stat & DW_IC_INTR_RX_UNDER)
 531                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 532         if (stat & DW_IC_INTR_RX_OVER)
 533                 dw_readl(dev, DW_IC_CLR_RX_OVER);
 534         if (stat & DW_IC_INTR_TX_OVER)
 535                 dw_readl(dev, DW_IC_CLR_TX_OVER);
 536         if (stat & DW_IC_INTR_RD_REQ)
 537                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 538         if (stat & DW_IC_INTR_TX_ABRT) {
 539                 /*
 540                  * The IC_TX_ABRT_SOURCE register is cleared whenever
 541                  * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 542                  */
 543                 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
 544                 dw_readl(dev, DW_IC_CLR_TX_ABRT);
 545         }
 546         if (stat & DW_IC_INTR_RX_DONE)
 547                 dw_readl(dev, DW_IC_CLR_RX_DONE);
 548         if (stat & DW_IC_INTR_ACTIVITY)
 549                 dw_readl(dev, DW_IC_CLR_ACTIVITY);
 550         if (stat & DW_IC_INTR_STOP_DET)
 551                 dw_readl(dev, DW_IC_CLR_STOP_DET);
 552         if (stat & DW_IC_INTR_START_DET)
 553                 dw_readl(dev, DW_IC_CLR_START_DET);
 554         if (stat & DW_IC_INTR_GEN_CALL)
 555                 dw_readl(dev, DW_IC_CLR_GEN_CALL);
 556
 557         return stat;
 558 }
 559
 560 /*
 561  * Interrupt service routine. This gets called whenever an I2C master interrupt
 562  * occurs.
 563  */
 564 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
 565 {
 566         u32 stat;
 567
 568         stat = i2c_dw_read_clear_intrbits(dev);
 569         if (stat & DW_IC_INTR_TX_ABRT) {
 570                 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
 571                 dev->status = STATUS_IDLE;
 572
 573                 /*
 574                  * Anytime TX_ABRT is set, the contents of the tx/rx
 575                  * buffers are flushed. Make sure to skip them.
 576                  */
 577                 dw_writel(dev, 0, DW_IC_INTR_MASK);
 578                 goto tx_aborted;
 579         }
 580
 581         if (stat & DW_IC_INTR_RX_FULL)
 582                 i2c_dw_read(dev);
 583
 584         if (stat & DW_IC_INTR_TX_EMPTY)
 585                 i2c_dw_xfer_msg(dev);
 586
 587         /*
 588          * No need to modify or disable the interrupt mask here.
 589          * i2c_dw_xfer_msg() will take care of it according to
 590          * the current transmit status.
 591          */
 592
 593 tx_aborted:
 594         if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
 595                 complete(&dev->cmd_complete);
 596         else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
 597                 /* Workaround to trigger pending interrupt */
 598                 stat = dw_readl(dev, DW_IC_INTR_MASK);
 599                 i2c_dw_disable_int(dev);
 600                 dw_writel(dev, stat, DW_IC_INTR_MASK);
 601         }
 602
 603         return 0;
 604 }
 605
 606 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
 607 {
 608         struct dw_i2c_dev *dev = dev_id;
 609         u32 stat, enabled;
 610
 611         enabled = dw_readl(dev, DW_IC_ENABLE);
 612         stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
 613         dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
 614         if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
 615                 return IRQ_NONE;
 616
 617         i2c_dw_irq_handler_master(dev);
 618
 619         return IRQ_HANDLED;
 620 }
 621
 622 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
 623 {
 624         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 625
 626         i2c_dw_disable(dev);
 627         reset_control_assert(dev->rst);
 628         i2c_dw_prepare_clk(dev, false);
 629 }
 630
 631 static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
 632 {
 633         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 634
 635         i2c_dw_prepare_clk(dev, true);
 636         reset_control_deassert(dev->rst);
 637         i2c_dw_init_master(dev);
 638 }
 639
 640 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
 641 {
 642         struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
 643         struct i2c_adapter *adap = &dev->adapter;
 644         struct gpio_desc *gpio;
 645         int r;
 646
 647         gpio = devm_gpiod_get(dev->dev, "scl", GPIOD_OUT_HIGH);
 648         if (IS_ERR(gpio)) {
 649                 r = PTR_ERR(gpio);
 650                 if (r == -ENOENT || r == -ENOSYS)
 651                         return 0;
 652                 return r;
 653         }
 654         rinfo->scl_gpiod = gpio;
 655
 656         gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
 657         if (IS_ERR(gpio))
 658                 return PTR_ERR(gpio);
 659         rinfo->sda_gpiod = gpio;
 660
 661         rinfo->recover_bus = i2c_generic_scl_recovery;
 662         rinfo->prepare_recovery = i2c_dw_prepare_recovery;
 663         rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
 664         adap->bus_recovery_info = rinfo;
 665
 666         dev_info(dev->dev, "running with gpio recovery mode! scl%s",
 667                  rinfo->sda_gpiod ? ",sda" : "");
 668
 669         return 0;
 670 }
 671
 672 int i2c_dw_probe(struct dw_i2c_dev *dev)
 673 {
 674         struct i2c_adapter *adap = &dev->adapter;
 675         unsigned long irq_flags;
 676         int ret;
 677
 678         init_completion(&dev->cmd_complete);
 679
 680         dev->init = i2c_dw_init_master;
 681         dev->disable = i2c_dw_disable;
 682         dev->disable_int = i2c_dw_disable_int;
 683
 684         ret = dev->init(dev);
 685         if (ret)
 686                 return ret;
 687
 688         snprintf(adap->name, sizeof(adap->name),
 689                  "Synopsys DesignWare I2C adapter");
 690         adap->retries = 3;
 691         adap->algo = &i2c_dw_algo;
 692         adap->dev.parent = dev->dev;
 693         i2c_set_adapdata(adap, dev);
 694
 695         if (dev->pm_disabled) {
 696                 dev_pm_syscore_device(dev->dev, true);
 697                 irq_flags = IRQF_NO_SUSPEND;
 698         } else {
 699                 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
 700         }
 701
 702         i2c_dw_disable_int(dev);
 703         ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
 704                                dev_name(dev->dev), dev);
 705         if (ret) {
 706                 dev_err(dev->dev, "failure requesting irq %i: %d\n",
 707                         dev->irq, ret);
 708                 return ret;
 709         }
 710
 711         ret = i2c_dw_init_recovery_info(dev);
 712         if (ret)
 713                 return ret;
 714
 715         /*
 716          * Increment PM usage count during adapter registration in order to
 717          * avoid possible spurious runtime suspend when adapter device is
 718          * registered to the device core and immediate resume in case bus has
 719          * registered I2C slaves that do I2C transfers in their probe.
 720          */
 721         pm_runtime_get_noresume(dev->dev);
 722         ret = i2c_add_numbered_adapter(adap);
 723         if (ret)
 724                 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
 725         pm_runtime_put_noidle(dev->dev);
 726
 727         return ret;
 728 }
 729 EXPORT_SYMBOL_GPL(i2c_dw_probe);
 730
 731 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
 732 MODULE_LICENSE("GPL");