drivers/i2c/busses/i2c-designware-master.c

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  *
  10  * ----------------------------------------------------------------------------
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  * ----------------------------------------------------------------------------
  22  *
  23  */
  24 #include <linux/delay.h>
  25 #include <linux/err.h>
  26 #include <linux/errno.h>
  27 #include <linux/export.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/i2c.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/module.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/reset.h>
  35
  36 #include "i2c-designware-core.h"
  37
  38 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
  39 {
  40         /* Configure Tx/Rx FIFO threshold levels */
  41         dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
  42         dw_writel(dev, 0, DW_IC_RX_TL);
  43
  44         /* Configure the I2C master */
  45         dw_writel(dev, dev->master_cfg, DW_IC_CON);
  46 }
  47
  48 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
  49 {
  50         u32 ic_clk = i2c_dw_clk_rate(dev);
  51         const char *mode_str, *fp_str = "";
  52         u32 comp_param1;
  53         u32 sda_falling_time, scl_falling_time;
  54         int ret;
  55
  56         ret = i2c_dw_acquire_lock(dev);
  57         if (ret)
  58                 return ret;
  59         comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
  60         i2c_dw_release_lock(dev);
  61
  62         /* Set standard and fast speed dividers for high/low periods */
  63         sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
  64         scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
  65
  66         /* Calculate SCL timing parameters for standard mode if not set */
  67         if (!dev->ss_hcnt || !dev->ss_lcnt) {
  68                 dev->ss_hcnt =
  69                         i2c_dw_scl_hcnt(ic_clk,
  70                                         4000,   /* tHD;STA = tHIGH = 4.0 us */
  71                                         sda_falling_time,
  72                                         0,      /* 0: DW default, 1: Ideal */
  73                                         0);     /* No offset */
  74                 dev->ss_lcnt =
  75                         i2c_dw_scl_lcnt(ic_clk,
  76                                         4700,   /* tLOW = 4.7 us */
  77                                         scl_falling_time,
  78                                         0);     /* No offset */
  79         }
  80         dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
  81                 dev->ss_hcnt, dev->ss_lcnt);
  82
  83         /*
  84          * Set SCL timing parameters for fast mode or fast mode plus. Only
  85          * difference is the timing parameter values since the registers are
  86          * the same.
  87          */
  88         if (dev->clk_freq == 1000000) {
  89                 /*
  90                  * Check are fast mode plus parameters available and use
  91                  * fast mode if not.
  92                  */
  93                 if (dev->fp_hcnt && dev->fp_lcnt) {
  94                         dev->fs_hcnt = dev->fp_hcnt;
  95                         dev->fs_lcnt = dev->fp_lcnt;
  96                         fp_str = " Plus";
  97                 }
  98         }
  99         /*
 100          * Calculate SCL timing parameters for fast mode if not set. They are
 101          * needed also in high speed mode.
 102          */
 103         if (!dev->fs_hcnt || !dev->fs_lcnt) {
 104                 dev->fs_hcnt =
 105                         i2c_dw_scl_hcnt(ic_clk,
 106                                         600,    /* tHD;STA = tHIGH = 0.6 us */
 107                                         sda_falling_time,
 108                                         0,      /* 0: DW default, 1: Ideal */
 109                                         0);     /* No offset */
 110                 dev->fs_lcnt =
 111                         i2c_dw_scl_lcnt(ic_clk,
 112                                         1300,   /* tLOW = 1.3 us */
 113                                         scl_falling_time,
 114                                         0);     /* No offset */
 115         }
 116         dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
 117                 fp_str, dev->fs_hcnt, dev->fs_lcnt);
 118
 119         /* Check is high speed possible and fall back to fast mode if not */
 120         if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
 121                 DW_IC_CON_SPEED_HIGH) {
 122                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 123                         != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
 124                         dev_err(dev->dev, "High Speed not supported!\n");
 125                         dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
 126                         dev->master_cfg |= DW_IC_CON_SPEED_FAST;
 127                         dev->hs_hcnt = 0;
 128                         dev->hs_lcnt = 0;
 129                 } else if (dev->hs_hcnt && dev->hs_lcnt) {
 130                         dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
 131                                 dev->hs_hcnt, dev->hs_lcnt);
 132                 }
 133         }
 134
 135         ret = i2c_dw_set_sda_hold(dev);
 136         if (ret)
 137                 goto out;
 138
 139         switch (dev->master_cfg & DW_IC_CON_SPEED_MASK) {
 140         case DW_IC_CON_SPEED_STD:
 141                 mode_str = "Standard Mode";
 142                 break;
 143         case DW_IC_CON_SPEED_HIGH:
 144                 mode_str = "High Speed Mode";
 145                 break;
 146         default:
 147                 mode_str = "Fast Mode";
 148         }
 149         dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str);
 150
 151 out:
 152         return ret;
 153 }
 154
 155 /**
 156  * i2c_dw_init() - Initialize the designware I2C master hardware
 157  * @dev: device private data
 158  *
 159  * This functions configures and enables the I2C master.
 160  * This function is called during I2C init function, and in case of timeout at
 161  * run time.
 162  */
 163 static int i2c_dw_init_master(struct dw_i2c_dev *dev)
 164 {
 165         int ret;
 166
 167         ret = i2c_dw_acquire_lock(dev);
 168         if (ret)
 169                 return ret;
 170
 171         /* Disable the adapter */
 172         __i2c_dw_disable(dev);
 173
 174         /* Write standard speed timing parameters */
 175         dw_writel(dev, dev->ss_hcnt, DW_IC_SS_SCL_HCNT);
 176         dw_writel(dev, dev->ss_lcnt, DW_IC_SS_SCL_LCNT);
 177
 178         /* Write fast mode/fast mode plus timing parameters */
 179         dw_writel(dev, dev->fs_hcnt, DW_IC_FS_SCL_HCNT);
 180         dw_writel(dev, dev->fs_lcnt, DW_IC_FS_SCL_LCNT);
 181
 182         /* Write high speed timing parameters if supported */
 183         if (dev->hs_hcnt && dev->hs_lcnt) {
 184                 dw_writel(dev, dev->hs_hcnt, DW_IC_HS_SCL_HCNT);
 185                 dw_writel(dev, dev->hs_lcnt, DW_IC_HS_SCL_LCNT);
 186         }
 187
 188         /* Write SDA hold time if supported */
 189         if (dev->sda_hold_time)
 190                 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
 191
 192         i2c_dw_configure_fifo_master(dev);
 193         i2c_dw_release_lock(dev);
 194
 195         return 0;
 196 }
 197
 198 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 199 {
 200         struct i2c_msg *msgs = dev->msgs;
 201         u32 ic_con, ic_tar = 0;
 202
 203         /* Disable the adapter */
 204         __i2c_dw_disable(dev);
 205
 206         /* If the slave address is ten bit address, enable 10BITADDR */
 207         ic_con = dw_readl(dev, DW_IC_CON);
 208         if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
 209                 ic_con |= DW_IC_CON_10BITADDR_MASTER;
 210                 /*
 211                  * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
 212                  * mode has to be enabled via bit 12 of IC_TAR register.
 213                  * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
 214                  * detected from registers.
 215                  */
 216                 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
 217         } else {
 218                 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
 219         }
 220
 221         dw_writel(dev, ic_con, DW_IC_CON);
 222
 223         /*
 224          * Set the slave (target) address and enable 10-bit addressing mode
 225          * if applicable.
 226          */
 227         dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
 228
 229         /* Enforce disabled interrupts (due to HW issues) */
 230         i2c_dw_disable_int(dev);
 231
 232         /* Enable the adapter */
 233         __i2c_dw_enable(dev);
 234
 235         /* Dummy read to avoid the register getting stuck on Bay Trail */
 236         dw_readl(dev, DW_IC_ENABLE_STATUS);
 237
 238         /* Clear and enable interrupts */
 239         dw_readl(dev, DW_IC_CLR_INTR);
 240         dw_writel(dev, DW_IC_INTR_MASTER_MASK, DW_IC_INTR_MASK);
 241 }
 242
 243 /*
 244  * Initiate (and continue) low level master read/write transaction.
 245  * This function is only called from i2c_dw_isr, and pumping i2c_msg
 246  * messages into the tx buffer.  Even if the size of i2c_msg data is
 247  * longer than the size of the tx buffer, it handles everything.
 248  */
 249 static void
 250 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 251 {
 252         struct i2c_msg *msgs = dev->msgs;
 253         u32 intr_mask;
 254         int tx_limit, rx_limit;
 255         u32 addr = msgs[dev->msg_write_idx].addr;
 256         u32 buf_len = dev->tx_buf_len;
 257         u8 *buf = dev->tx_buf;
 258         bool need_restart = false;
 259
 260         intr_mask = DW_IC_INTR_MASTER_MASK;
 261
 262         for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
 263                 u32 flags = msgs[dev->msg_write_idx].flags;
 264
 265                 /*
 266                  * If target address has changed, we need to
 267                  * reprogram the target address in the I2C
 268                  * adapter when we are done with this transfer.
 269                  */
 270                 if (msgs[dev->msg_write_idx].addr != addr) {
 271                         dev_err(dev->dev,
 272                                 "%s: invalid target address\n", __func__);
 273                         dev->msg_err = -EINVAL;
 274                         break;
 275                 }
 276
 277                 if (msgs[dev->msg_write_idx].len == 0) {
 278                         dev_err(dev->dev,
 279                                 "%s: invalid message length\n", __func__);
 280                         dev->msg_err = -EINVAL;
 281                         break;
 282                 }
 283
 284                 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
 285                         /* new i2c_msg */
 286                         buf = msgs[dev->msg_write_idx].buf;
 287                         buf_len = msgs[dev->msg_write_idx].len;
 288
 289                         /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
 290                          * IC_RESTART_EN are set, we must manually
 291                          * set restart bit between messages.
 292                          */
 293                         if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
 294                                         (dev->msg_write_idx > 0))
 295                                 need_restart = true;
 296                 }
 297
 298                 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
 299                 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
 300
 301                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
 302                         u32 cmd = 0;
 303
 304                         /*
 305                          * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
 306                          * manually set the stop bit. However, it cannot be
 307                          * detected from the registers so we set it always
 308                          * when writing/reading the last byte.
 309                          */
 310
 311                         /*
 312                          * i2c-core always sets the buffer length of
 313                          * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
 314                          * be adjusted when receiving the first byte.
 315                          * Thus we can't stop the transaction here.
 316                          */
 317                         if (dev->msg_write_idx == dev->msgs_num - 1 &&
 318                             buf_len == 1 && !(flags & I2C_M_RECV_LEN))
 319                                 cmd |= BIT(9);
 320
 321                         if (need_restart) {
 322                                 cmd |= BIT(10);
 323                                 need_restart = false;
 324                         }
 325
 326                         if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 327
 328                                 /* Avoid rx buffer overrun */
 329                                 if (dev->rx_outstanding >= dev->rx_fifo_depth)
 330                                         break;
 331
 332                                 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
 333                                 rx_limit--;
 334                                 dev->rx_outstanding++;
 335                         } else
 336                                 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
 337                         tx_limit--; buf_len--;
 338                 }
 339
 340                 dev->tx_buf = buf;
 341                 dev->tx_buf_len = buf_len;
 342
 343                 /*
 344                  * Because we don't know the buffer length in the
 345                  * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
 346                  * the transaction here.
 347                  */
 348                 if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
 349                         /* more bytes to be written */
 350                         dev->status |= STATUS_WRITE_IN_PROGRESS;
 351                         break;
 352                 } else
 353                         dev->status &= ~STATUS_WRITE_IN_PROGRESS;
 354         }
 355
 356         /*
 357          * If i2c_msg index search is completed, we don't need TX_EMPTY
 358          * interrupt any more.
 359          */
 360         if (dev->msg_write_idx == dev->msgs_num)
 361                 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 362
 363         if (dev->msg_err)
 364                 intr_mask = 0;
 365
 366         dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
 367 }
 368
 369 static u8
 370 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
 371 {
 372         struct i2c_msg *msgs = dev->msgs;
 373         u32 flags = msgs[dev->msg_read_idx].flags;
 374
 375         /*
 376          * Adjust the buffer length and mask the flag
 377          * after receiving the first byte.
 378          */
 379         len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
 380         dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
 381         msgs[dev->msg_read_idx].len = len;
 382         msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
 383
 384         return len;
 385 }
 386
 387 static void
 388 i2c_dw_read(struct dw_i2c_dev *dev)
 389 {
 390         struct i2c_msg *msgs = dev->msgs;
 391         int rx_valid;
 392
 393         for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
 394                 u32 len;
 395                 u8 *buf;
 396
 397                 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
 398                         continue;
 399
 400                 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 401                         len = msgs[dev->msg_read_idx].len;
 402                         buf = msgs[dev->msg_read_idx].buf;
 403                 } else {
 404                         len = dev->rx_buf_len;
 405                         buf = dev->rx_buf;
 406                 }
 407
 408                 rx_valid = dw_readl(dev, DW_IC_RXFLR);
 409
 410                 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
 411                         u32 flags = msgs[dev->msg_read_idx].flags;
 412
 413                         *buf = dw_readl(dev, DW_IC_DATA_CMD);
 414                         /* Ensure length byte is a valid value */
 415                         if (flags & I2C_M_RECV_LEN &&
 416                                 *buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) {
 417                                 len = i2c_dw_recv_len(dev, *buf);
 418                         }
 419                         buf++;
 420                         dev->rx_outstanding--;
 421                 }
 422
 423                 if (len > 0) {
 424                         dev->status |= STATUS_READ_IN_PROGRESS;
 425                         dev->rx_buf_len = len;
 426                         dev->rx_buf = buf;
 427                         return;
 428                 } else
 429                         dev->status &= ~STATUS_READ_IN_PROGRESS;
 430         }
 431 }
 432
 433 /*
 434  * Prepare controller for a transaction and call i2c_dw_xfer_msg.
 435  */
 436 static int
 437 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 438 {
 439         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 440         int ret;
 441
 442         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 443
 444         pm_runtime_get_sync(dev->dev);
 445
 446         reinit_completion(&dev->cmd_complete);
 447         dev->msgs = msgs;
 448         dev->msgs_num = num;
 449         dev->cmd_err = 0;
 450         dev->msg_write_idx = 0;
 451         dev->msg_read_idx = 0;
 452         dev->msg_err = 0;
 453         dev->status = STATUS_IDLE;
 454         dev->abort_source = 0;
 455         dev->rx_outstanding = 0;
 456
 457         ret = i2c_dw_acquire_lock(dev);
 458         if (ret)
 459                 goto done_nolock;
 460
 461         ret = i2c_dw_wait_bus_not_busy(dev);
 462         if (ret < 0)
 463                 goto done;
 464
 465         /* Start the transfers */
 466         i2c_dw_xfer_init(dev);
 467
 468         /* Wait for tx to complete */
 469         if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
 470                 dev_err(dev->dev, "controller timed out\n");
 471                 /* i2c_dw_init implicitly disables the adapter */
 472                 i2c_recover_bus(&dev->adapter);
 473                 i2c_dw_init_master(dev);
 474                 ret = -ETIMEDOUT;
 475                 goto done;
 476         }
 477
 478         /*
 479          * We must disable the adapter before returning and signaling the end
 480          * of the current transfer. Otherwise the hardware might continue
 481          * generating interrupts which in turn causes a race condition with
 482          * the following transfer.  Needs some more investigation if the
 483          * additional interrupts are a hardware bug or this driver doesn't
 484          * handle them correctly yet.
 485          */
 486         __i2c_dw_disable_nowait(dev);
 487
 488         if (dev->msg_err) {
 489                 ret = dev->msg_err;
 490                 goto done;
 491         }
 492
 493         /* No error */
 494         if (likely(!dev->cmd_err && !dev->status)) {
 495                 ret = num;
 496                 goto done;
 497         }
 498
 499         /* We have an error */
 500         if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
 501                 ret = i2c_dw_handle_tx_abort(dev);
 502                 goto done;
 503         }
 504
 505         if (dev->status)
 506                 dev_err(dev->dev,
 507                         "transfer terminated early - interrupt latency too high?\n");
 508
 509         ret = -EIO;
 510
 511 done:
 512         i2c_dw_release_lock(dev);
 513
 514 done_nolock:
 515         pm_runtime_mark_last_busy(dev->dev);
 516         pm_runtime_put_autosuspend(dev->dev);
 517
 518         return ret;
 519 }
 520
 521 static const struct i2c_algorithm i2c_dw_algo = {
 522         .master_xfer = i2c_dw_xfer,
 523         .functionality = i2c_dw_func,
 524 };
 525
 526 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 527 {
 528         u32 stat;
 529
 530         /*
 531          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 532          * Ths unmasked raw version of interrupt status bits are available
 533          * in the IC_RAW_INTR_STAT register.
 534          *
 535          * That is,
 536          *   stat = dw_readl(IC_INTR_STAT);
 537          * equals to,
 538          *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
 539          *
 540          * The raw version might be useful for debugging purposes.
 541          */
 542         stat = dw_readl(dev, DW_IC_INTR_STAT);
 543
 544         /*
 545          * Do not use the IC_CLR_INTR register to clear interrupts, or
 546          * you'll miss some interrupts, triggered during the period from
 547          * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
 548          *
 549          * Instead, use the separately-prepared IC_CLR_* registers.
 550          */
 551         if (stat & DW_IC_INTR_RX_UNDER)
 552                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 553         if (stat & DW_IC_INTR_RX_OVER)
 554                 dw_readl(dev, DW_IC_CLR_RX_OVER);
 555         if (stat & DW_IC_INTR_TX_OVER)
 556                 dw_readl(dev, DW_IC_CLR_TX_OVER);
 557         if (stat & DW_IC_INTR_RD_REQ)
 558                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 559         if (stat & DW_IC_INTR_TX_ABRT) {
 560                 /*
 561                  * The IC_TX_ABRT_SOURCE register is cleared whenever
 562                  * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 563                  */
 564                 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
 565                 dw_readl(dev, DW_IC_CLR_TX_ABRT);
 566         }
 567         if (stat & DW_IC_INTR_RX_DONE)
 568                 dw_readl(dev, DW_IC_CLR_RX_DONE);
 569         if (stat & DW_IC_INTR_ACTIVITY)
 570                 dw_readl(dev, DW_IC_CLR_ACTIVITY);
 571         if (stat & DW_IC_INTR_STOP_DET)
 572                 dw_readl(dev, DW_IC_CLR_STOP_DET);
 573         if (stat & DW_IC_INTR_START_DET)
 574                 dw_readl(dev, DW_IC_CLR_START_DET);
 575         if (stat & DW_IC_INTR_GEN_CALL)
 576                 dw_readl(dev, DW_IC_CLR_GEN_CALL);
 577
 578         return stat;
 579 }
 580
 581 /*
 582  * Interrupt service routine. This gets called whenever an I2C master interrupt
 583  * occurs.
 584  */
 585 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
 586 {
 587         u32 stat;
 588
 589         stat = i2c_dw_read_clear_intrbits(dev);
 590         if (stat & DW_IC_INTR_TX_ABRT) {
 591                 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
 592                 dev->status = STATUS_IDLE;
 593
 594                 /*
 595                  * Anytime TX_ABRT is set, the contents of the tx/rx
 596                  * buffers are flushed. Make sure to skip them.
 597                  */
 598                 dw_writel(dev, 0, DW_IC_INTR_MASK);
 599                 goto tx_aborted;
 600         }
 601
 602         if (stat & DW_IC_INTR_RX_FULL)
 603                 i2c_dw_read(dev);
 604
 605         if (stat & DW_IC_INTR_TX_EMPTY)
 606                 i2c_dw_xfer_msg(dev);
 607
 608         /*
 609          * No need to modify or disable the interrupt mask here.
 610          * i2c_dw_xfer_msg() will take care of it according to
 611          * the current transmit status.
 612          */
 613
 614 tx_aborted:
 615         if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
 616                 complete(&dev->cmd_complete);
 617         else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
 618                 /* Workaround to trigger pending interrupt */
 619                 stat = dw_readl(dev, DW_IC_INTR_MASK);
 620                 i2c_dw_disable_int(dev);
 621                 dw_writel(dev, stat, DW_IC_INTR_MASK);
 622         }
 623
 624         return 0;
 625 }
 626
 627 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
 628 {
 629         struct dw_i2c_dev *dev = dev_id;
 630         u32 stat, enabled;
 631
 632         enabled = dw_readl(dev, DW_IC_ENABLE);
 633         stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
 634         dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
 635         if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
 636                 return IRQ_NONE;
 637
 638         i2c_dw_irq_handler_master(dev);
 639
 640         return IRQ_HANDLED;
 641 }
 642
 643 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
 644 {
 645         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 646
 647         i2c_dw_disable(dev);
 648         reset_control_assert(dev->rst);
 649         i2c_dw_prepare_clk(dev, false);
 650 }
 651
 652 static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
 653 {
 654         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 655
 656         i2c_dw_prepare_clk(dev, true);
 657         reset_control_deassert(dev->rst);
 658         i2c_dw_init_master(dev);
 659 }
 660
 661 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
 662 {
 663         struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
 664         struct i2c_adapter *adap = &dev->adapter;
 665         struct gpio_desc *gpio;
 666         int r;
 667
 668         gpio = devm_gpiod_get(dev->dev, "scl", GPIOD_OUT_HIGH);
 669         if (IS_ERR(gpio)) {
 670                 r = PTR_ERR(gpio);
 671                 if (r == -ENOENT || r == -ENOSYS)
 672                         return 0;
 673                 return r;
 674         }
 675         rinfo->scl_gpiod = gpio;
 676
 677         gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
 678         if (IS_ERR(gpio))
 679                 return PTR_ERR(gpio);
 680         rinfo->sda_gpiod = gpio;
 681
 682         rinfo->recover_bus = i2c_generic_scl_recovery;
 683         rinfo->prepare_recovery = i2c_dw_prepare_recovery;
 684         rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
 685         adap->bus_recovery_info = rinfo;
 686
 687         dev_info(dev->dev, "running with gpio recovery mode! scl%s",
 688                  rinfo->sda_gpiod ? ",sda" : "");
 689
 690         return 0;
 691 }
 692
 693 int i2c_dw_probe(struct dw_i2c_dev *dev)
 694 {
 695         struct i2c_adapter *adap = &dev->adapter;
 696         unsigned long irq_flags;
 697         int ret;
 698
 699         init_completion(&dev->cmd_complete);
 700
 701         dev->init = i2c_dw_init_master;
 702         dev->disable = i2c_dw_disable;
 703         dev->disable_int = i2c_dw_disable_int;
 704
 705         ret = i2c_dw_set_reg_access(dev);
 706         if (ret)
 707                 return ret;
 708
 709         ret = i2c_dw_set_timings_master(dev);
 710         if (ret)
 711                 return ret;
 712
 713         ret = dev->init(dev);
 714         if (ret)
 715                 return ret;
 716
 717         snprintf(adap->name, sizeof(adap->name),
 718                  "Synopsys DesignWare I2C adapter");
 719         adap->retries = 3;
 720         adap->algo = &i2c_dw_algo;
 721         adap->dev.parent = dev->dev;
 722         i2c_set_adapdata(adap, dev);
 723
 724         if (dev->pm_disabled) {
 725                 dev_pm_syscore_device(dev->dev, true);
 726                 irq_flags = IRQF_NO_SUSPEND;
 727         } else {
 728                 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
 729         }
 730
 731         i2c_dw_disable_int(dev);
 732         ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
 733                                dev_name(dev->dev), dev);
 734         if (ret) {
 735                 dev_err(dev->dev, "failure requesting irq %i: %d\n",
 736                         dev->irq, ret);
 737                 return ret;
 738         }
 739
 740         ret = i2c_dw_init_recovery_info(dev);
 741         if (ret)
 742                 return ret;
 743
 744         /*
 745          * Increment PM usage count during adapter registration in order to
 746          * avoid possible spurious runtime suspend when adapter device is
 747          * registered to the device core and immediate resume in case bus has
 748          * registered I2C slaves that do I2C transfers in their probe.
 749          */
 750         pm_runtime_get_noresume(dev->dev);
 751         ret = i2c_add_numbered_adapter(adap);
 752         if (ret)
 753                 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
 754         pm_runtime_put_noidle(dev->dev);
 755
 756         return ret;
 757 }
 758 EXPORT_SYMBOL_GPL(i2c_dw_probe);
 759
 760 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
 761 MODULE_LICENSE("GPL");