2 * Synopsys DesignWare I2C adapter driver (master only).
4 * Based on the TI DAVINCI I2C adapter driver.
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
10 * ----------------------------------------------------------------------------
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 * ----------------------------------------------------------------------------
24 #include <linux/export.h>
25 #include <linux/errno.h>
26 #include <linux/err.h>
27 #include <linux/i2c.h>
28 #include <linux/interrupt.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/delay.h>
32 #include <linux/module.h>
33 #include "i2c-designware-core.h"
40 #define DW_IC_DATA_CMD 0x10
41 #define DW_IC_SS_SCL_HCNT 0x14
42 #define DW_IC_SS_SCL_LCNT 0x18
43 #define DW_IC_FS_SCL_HCNT 0x1c
44 #define DW_IC_FS_SCL_LCNT 0x20
45 #define DW_IC_INTR_STAT 0x2c
46 #define DW_IC_INTR_MASK 0x30
47 #define DW_IC_RAW_INTR_STAT 0x34
48 #define DW_IC_RX_TL 0x38
49 #define DW_IC_TX_TL 0x3c
50 #define DW_IC_CLR_INTR 0x40
51 #define DW_IC_CLR_RX_UNDER 0x44
52 #define DW_IC_CLR_RX_OVER 0x48
53 #define DW_IC_CLR_TX_OVER 0x4c
54 #define DW_IC_CLR_RD_REQ 0x50
55 #define DW_IC_CLR_TX_ABRT 0x54
56 #define DW_IC_CLR_RX_DONE 0x58
57 #define DW_IC_CLR_ACTIVITY 0x5c
58 #define DW_IC_CLR_STOP_DET 0x60
59 #define DW_IC_CLR_START_DET 0x64
60 #define DW_IC_CLR_GEN_CALL 0x68
61 #define DW_IC_ENABLE 0x6c
62 #define DW_IC_STATUS 0x70
63 #define DW_IC_TXFLR 0x74
64 #define DW_IC_RXFLR 0x78
65 #define DW_IC_SDA_HOLD 0x7c
66 #define DW_IC_TX_ABRT_SOURCE 0x80
67 #define DW_IC_ENABLE_STATUS 0x9c
68 #define DW_IC_COMP_PARAM_1 0xf4
69 #define DW_IC_COMP_VERSION 0xf8
70 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
71 #define DW_IC_COMP_TYPE 0xfc
72 #define DW_IC_COMP_TYPE_VALUE 0x44570140
74 #define DW_IC_INTR_RX_UNDER 0x001
75 #define DW_IC_INTR_RX_OVER 0x002
76 #define DW_IC_INTR_RX_FULL 0x004
77 #define DW_IC_INTR_TX_OVER 0x008
78 #define DW_IC_INTR_TX_EMPTY 0x010
79 #define DW_IC_INTR_RD_REQ 0x020
80 #define DW_IC_INTR_TX_ABRT 0x040
81 #define DW_IC_INTR_RX_DONE 0x080
82 #define DW_IC_INTR_ACTIVITY 0x100
83 #define DW_IC_INTR_STOP_DET 0x200
84 #define DW_IC_INTR_START_DET 0x400
85 #define DW_IC_INTR_GEN_CALL 0x800
87 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
88 DW_IC_INTR_TX_EMPTY | \
89 DW_IC_INTR_TX_ABRT | \
92 #define DW_IC_STATUS_ACTIVITY 0x1
94 #define DW_IC_ERR_TX_ABRT 0x1
96 #define DW_IC_TAR_10BITADDR_MASTER BIT(12)
101 #define STATUS_IDLE 0x0
102 #define STATUS_WRITE_IN_PROGRESS 0x1
103 #define STATUS_READ_IN_PROGRESS 0x2
105 #define TIMEOUT 20 /* ms */
108 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
110 * only expected abort codes are listed here
111 * refer to the datasheet for the full list
113 #define ABRT_7B_ADDR_NOACK 0
114 #define ABRT_10ADDR1_NOACK 1
115 #define ABRT_10ADDR2_NOACK 2
116 #define ABRT_TXDATA_NOACK 3
117 #define ABRT_GCALL_NOACK 4
118 #define ABRT_GCALL_READ 5
119 #define ABRT_SBYTE_ACKDET 7
120 #define ABRT_SBYTE_NORSTRT 9
121 #define ABRT_10B_RD_NORSTRT 10
122 #define ABRT_MASTER_DIS 11
125 #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
126 #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
127 #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
128 #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
129 #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
130 #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
131 #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
132 #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
133 #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
134 #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
135 #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
137 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
138 DW_IC_TX_ABRT_10ADDR1_NOACK | \
139 DW_IC_TX_ABRT_10ADDR2_NOACK | \
140 DW_IC_TX_ABRT_TXDATA_NOACK | \
141 DW_IC_TX_ABRT_GCALL_NOACK)
143 static char *abort_sources[] = {
144 [ABRT_7B_ADDR_NOACK] =
145 "slave address not acknowledged (7bit mode)",
146 [ABRT_10ADDR1_NOACK] =
147 "first address byte not acknowledged (10bit mode)",
148 [ABRT_10ADDR2_NOACK] =
149 "second address byte not acknowledged (10bit mode)",
150 [ABRT_TXDATA_NOACK] =
151 "data not acknowledged",
153 "no acknowledgement for a general call",
155 "read after general call",
156 [ABRT_SBYTE_ACKDET] =
157 "start byte acknowledged",
158 [ABRT_SBYTE_NORSTRT] =
159 "trying to send start byte when restart is disabled",
160 [ABRT_10B_RD_NORSTRT] =
161 "trying to read when restart is disabled (10bit mode)",
163 "trying to use disabled adapter",
168 u32 dw_readl(struct dw_i2c_dev *dev, int offset)
172 if (dev->accessor_flags & ACCESS_16BIT)
173 value = readw(dev->base + offset) |
174 (readw(dev->base + offset + 2) << 16);
176 value = readl(dev->base + offset);
178 if (dev->accessor_flags & ACCESS_SWAP)
179 return swab32(value);
184 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
186 if (dev->accessor_flags & ACCESS_SWAP)
189 if (dev->accessor_flags & ACCESS_16BIT) {
190 writew((u16)b, dev->base + offset);
191 writew((u16)(b >> 16), dev->base + offset + 2);
193 writel(b, dev->base + offset);
198 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
201 * DesignWare I2C core doesn't seem to have solid strategy to meet
202 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
203 * will result in violation of the tHD;STA spec.
207 * Conditional expression:
209 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
211 * This is based on the DW manuals, and represents an ideal
212 * configuration. The resulting I2C bus speed will be
213 * faster than any of the others.
215 * If your hardware is free from tHD;STA issue, try this one.
217 return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset;
220 * Conditional expression:
222 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
224 * This is just experimental rule; the tHD;STA period turned
225 * out to be proportinal to (_HCNT + 3). With this setting,
226 * we could meet both tHIGH and tHD;STA timing specs.
228 * If unsure, you'd better to take this alternative.
230 * The reason why we need to take into account "tf" here,
231 * is the same as described in i2c_dw_scl_lcnt().
233 return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset;
236 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
239 * Conditional expression:
241 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
243 * DW I2C core starts counting the SCL CNTs for the LOW period
244 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
245 * In order to meet the tLOW timing spec, we need to take into
246 * account the fall time of SCL signal (tf). Default tf value
247 * should be 0.3 us, for safety.
249 return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset;
252 static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
257 dw_writel(dev, enable, DW_IC_ENABLE);
258 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
262 * Wait 10 times the signaling period of the highest I2C
263 * transfer supported by the driver (for 400KHz this is
264 * 25us) as described in the DesignWare I2C databook.
266 usleep_range(25, 250);
269 dev_warn(dev->dev, "timeout in %sabling adapter\n",
270 enable ? "en" : "dis");
274 * i2c_dw_init() - initialize the designware i2c master hardware
275 * @dev: device private data
277 * This functions configures and enables the I2C master.
278 * This function is called during I2C init function, and in case of timeout at
281 int i2c_dw_init(struct dw_i2c_dev *dev)
287 input_clock_khz = dev->get_clk_rate_khz(dev);
289 reg = dw_readl(dev, DW_IC_COMP_TYPE);
290 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
291 /* Configure register endianess access */
292 dev->accessor_flags |= ACCESS_SWAP;
293 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
294 /* Configure register access mode 16bit */
295 dev->accessor_flags |= ACCESS_16BIT;
296 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
297 dev_err(dev->dev, "Unknown Synopsys component type: "
302 /* Disable the adapter */
303 __i2c_dw_enable(dev, false);
305 /* set standard and fast speed deviders for high/low periods */
308 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
309 40, /* tHD;STA = tHIGH = 4.0 us */
311 0, /* 0: DW default, 1: Ideal */
313 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
314 47, /* tLOW = 4.7 us */
318 /* Allow platforms to specify the ideal HCNT and LCNT values */
319 if (dev->ss_hcnt && dev->ss_lcnt) {
323 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
324 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
325 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
328 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
329 6, /* tHD;STA = tHIGH = 0.6 us */
331 0, /* 0: DW default, 1: Ideal */
333 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
334 13, /* tLOW = 1.3 us */
338 if (dev->fs_hcnt && dev->fs_lcnt) {
342 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
343 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
344 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
346 /* Configure SDA Hold Time if required */
347 if (dev->sda_hold_time) {
348 reg = dw_readl(dev, DW_IC_COMP_VERSION);
349 if (reg >= DW_IC_SDA_HOLD_MIN_VERS)
350 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
353 "Hardware too old to adjust SDA hold time.");
356 /* Configure Tx/Rx FIFO threshold levels */
357 dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL);
358 dw_writel(dev, 0, DW_IC_RX_TL);
360 /* configure the i2c master */
361 dw_writel(dev, dev->master_cfg , DW_IC_CON);
364 EXPORT_SYMBOL_GPL(i2c_dw_init);
367 * Waiting for bus not busy
369 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
371 int timeout = TIMEOUT;
373 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
375 dev_warn(dev->dev, "timeout waiting for bus ready\n");
379 usleep_range(1000, 1100);
385 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
387 struct i2c_msg *msgs = dev->msgs;
388 u32 ic_con, ic_tar = 0;
390 /* Disable the adapter */
391 __i2c_dw_enable(dev, false);
393 /* if the slave address is ten bit address, enable 10BITADDR */
394 ic_con = dw_readl(dev, DW_IC_CON);
395 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
396 ic_con |= DW_IC_CON_10BITADDR_MASTER;
398 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
399 * mode has to be enabled via bit 12 of IC_TAR register.
400 * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
401 * detected from registers.
403 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
405 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
408 dw_writel(dev, ic_con, DW_IC_CON);
411 * Set the slave (target) address and enable 10-bit addressing mode
414 dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
416 /* enforce disabled interrupts (due to HW issues) */
417 i2c_dw_disable_int(dev);
419 /* Enable the adapter */
420 __i2c_dw_enable(dev, true);
422 /* Clear and enable interrupts */
423 i2c_dw_clear_int(dev);
424 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
428 * Initiate (and continue) low level master read/write transaction.
429 * This function is only called from i2c_dw_isr, and pumping i2c_msg
430 * messages into the tx buffer. Even if the size of i2c_msg data is
431 * longer than the size of the tx buffer, it handles everything.
434 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
436 struct i2c_msg *msgs = dev->msgs;
438 int tx_limit, rx_limit;
439 u32 addr = msgs[dev->msg_write_idx].addr;
440 u32 buf_len = dev->tx_buf_len;
441 u8 *buf = dev->tx_buf;
442 bool need_restart = false;
444 intr_mask = DW_IC_INTR_DEFAULT_MASK;
446 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
448 * if target address has changed, we need to
449 * reprogram the target address in the i2c
450 * adapter when we are done with this transfer
452 if (msgs[dev->msg_write_idx].addr != addr) {
454 "%s: invalid target address\n", __func__);
455 dev->msg_err = -EINVAL;
459 if (msgs[dev->msg_write_idx].len == 0) {
461 "%s: invalid message length\n", __func__);
462 dev->msg_err = -EINVAL;
466 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
468 buf = msgs[dev->msg_write_idx].buf;
469 buf_len = msgs[dev->msg_write_idx].len;
471 /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
472 * IC_RESTART_EN are set, we must manually
473 * set restart bit between messages.
475 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
476 (dev->msg_write_idx > 0))
480 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
481 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
483 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
487 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
488 * manually set the stop bit. However, it cannot be
489 * detected from the registers so we set it always
490 * when writing/reading the last byte.
492 if (dev->msg_write_idx == dev->msgs_num - 1 &&
498 need_restart = false;
501 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
503 /* avoid rx buffer overrun */
504 if (rx_limit - dev->rx_outstanding <= 0)
507 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
509 dev->rx_outstanding++;
511 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
512 tx_limit--; buf_len--;
516 dev->tx_buf_len = buf_len;
519 /* more bytes to be written */
520 dev->status |= STATUS_WRITE_IN_PROGRESS;
523 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
527 * If i2c_msg index search is completed, we don't need TX_EMPTY
528 * interrupt any more.
530 if (dev->msg_write_idx == dev->msgs_num)
531 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
536 dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
540 i2c_dw_read(struct dw_i2c_dev *dev)
542 struct i2c_msg *msgs = dev->msgs;
545 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
549 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
552 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
553 len = msgs[dev->msg_read_idx].len;
554 buf = msgs[dev->msg_read_idx].buf;
556 len = dev->rx_buf_len;
560 rx_valid = dw_readl(dev, DW_IC_RXFLR);
562 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
563 *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
564 dev->rx_outstanding--;
568 dev->status |= STATUS_READ_IN_PROGRESS;
569 dev->rx_buf_len = len;
573 dev->status &= ~STATUS_READ_IN_PROGRESS;
577 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
579 unsigned long abort_source = dev->abort_source;
582 if (abort_source & DW_IC_TX_ABRT_NOACK) {
583 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
585 "%s: %s\n", __func__, abort_sources[i]);
589 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
590 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
592 if (abort_source & DW_IC_TX_ARB_LOST)
594 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
595 return -EINVAL; /* wrong msgs[] data */
601 * Prepare controller for a transaction and call i2c_dw_xfer_msg
604 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
606 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
609 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
611 mutex_lock(&dev->lock);
612 pm_runtime_get_sync(dev->dev);
614 reinit_completion(&dev->cmd_complete);
618 dev->msg_write_idx = 0;
619 dev->msg_read_idx = 0;
621 dev->status = STATUS_IDLE;
622 dev->abort_source = 0;
623 dev->rx_outstanding = 0;
625 ret = i2c_dw_wait_bus_not_busy(dev);
629 /* start the transfers */
630 i2c_dw_xfer_init(dev);
632 /* wait for tx to complete */
633 ret = wait_for_completion_timeout(&dev->cmd_complete, HZ);
635 dev_err(dev->dev, "controller timed out\n");
636 /* i2c_dw_init implicitly disables the adapter */
643 * We must disable the adapter before unlocking the &dev->lock mutex
644 * below. Otherwise the hardware might continue generating interrupts
645 * which in turn causes a race condition with the following transfer.
646 * Needs some more investigation if the additional interrupts are
647 * a hardware bug or this driver doesn't handle them correctly yet.
649 __i2c_dw_enable(dev, false);
657 if (likely(!dev->cmd_err)) {
662 /* We have an error */
663 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
664 ret = i2c_dw_handle_tx_abort(dev);
670 pm_runtime_mark_last_busy(dev->dev);
671 pm_runtime_put_autosuspend(dev->dev);
672 mutex_unlock(&dev->lock);
676 EXPORT_SYMBOL_GPL(i2c_dw_xfer);
678 u32 i2c_dw_func(struct i2c_adapter *adap)
680 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
681 return dev->functionality;
683 EXPORT_SYMBOL_GPL(i2c_dw_func);
685 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
690 * The IC_INTR_STAT register just indicates "enabled" interrupts.
691 * Ths unmasked raw version of interrupt status bits are available
692 * in the IC_RAW_INTR_STAT register.
695 * stat = dw_readl(IC_INTR_STAT);
697 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
699 * The raw version might be useful for debugging purposes.
701 stat = dw_readl(dev, DW_IC_INTR_STAT);
704 * Do not use the IC_CLR_INTR register to clear interrupts, or
705 * you'll miss some interrupts, triggered during the period from
706 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
708 * Instead, use the separately-prepared IC_CLR_* registers.
710 if (stat & DW_IC_INTR_RX_UNDER)
711 dw_readl(dev, DW_IC_CLR_RX_UNDER);
712 if (stat & DW_IC_INTR_RX_OVER)
713 dw_readl(dev, DW_IC_CLR_RX_OVER);
714 if (stat & DW_IC_INTR_TX_OVER)
715 dw_readl(dev, DW_IC_CLR_TX_OVER);
716 if (stat & DW_IC_INTR_RD_REQ)
717 dw_readl(dev, DW_IC_CLR_RD_REQ);
718 if (stat & DW_IC_INTR_TX_ABRT) {
720 * The IC_TX_ABRT_SOURCE register is cleared whenever
721 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
723 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
724 dw_readl(dev, DW_IC_CLR_TX_ABRT);
726 if (stat & DW_IC_INTR_RX_DONE)
727 dw_readl(dev, DW_IC_CLR_RX_DONE);
728 if (stat & DW_IC_INTR_ACTIVITY)
729 dw_readl(dev, DW_IC_CLR_ACTIVITY);
730 if (stat & DW_IC_INTR_STOP_DET)
731 dw_readl(dev, DW_IC_CLR_STOP_DET);
732 if (stat & DW_IC_INTR_START_DET)
733 dw_readl(dev, DW_IC_CLR_START_DET);
734 if (stat & DW_IC_INTR_GEN_CALL)
735 dw_readl(dev, DW_IC_CLR_GEN_CALL);
741 * Interrupt service routine. This gets called whenever an I2C interrupt
744 irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
746 struct dw_i2c_dev *dev = dev_id;
749 enabled = dw_readl(dev, DW_IC_ENABLE);
750 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
751 dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__,
752 dev->adapter.name, enabled, stat);
753 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
756 stat = i2c_dw_read_clear_intrbits(dev);
758 if (stat & DW_IC_INTR_TX_ABRT) {
759 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
760 dev->status = STATUS_IDLE;
763 * Anytime TX_ABRT is set, the contents of the tx/rx
764 * buffers are flushed. Make sure to skip them.
766 dw_writel(dev, 0, DW_IC_INTR_MASK);
770 if (stat & DW_IC_INTR_RX_FULL)
773 if (stat & DW_IC_INTR_TX_EMPTY)
774 i2c_dw_xfer_msg(dev);
777 * No need to modify or disable the interrupt mask here.
778 * i2c_dw_xfer_msg() will take care of it according to
779 * the current transmit status.
783 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
784 complete(&dev->cmd_complete);
788 EXPORT_SYMBOL_GPL(i2c_dw_isr);
790 void i2c_dw_enable(struct dw_i2c_dev *dev)
792 /* Enable the adapter */
793 __i2c_dw_enable(dev, true);
795 EXPORT_SYMBOL_GPL(i2c_dw_enable);
797 u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev)
799 return dw_readl(dev, DW_IC_ENABLE);
801 EXPORT_SYMBOL_GPL(i2c_dw_is_enabled);
803 void i2c_dw_disable(struct dw_i2c_dev *dev)
805 /* Disable controller */
806 __i2c_dw_enable(dev, false);
808 /* Disable all interupts */
809 dw_writel(dev, 0, DW_IC_INTR_MASK);
810 dw_readl(dev, DW_IC_CLR_INTR);
812 EXPORT_SYMBOL_GPL(i2c_dw_disable);
814 void i2c_dw_clear_int(struct dw_i2c_dev *dev)
816 dw_readl(dev, DW_IC_CLR_INTR);
818 EXPORT_SYMBOL_GPL(i2c_dw_clear_int);
820 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
822 dw_writel(dev, 0, DW_IC_INTR_MASK);
824 EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
826 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
828 return dw_readl(dev, DW_IC_COMP_PARAM_1);
830 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
832 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
833 MODULE_LICENSE("GPL");