2 * Synopsys DesignWare I2C adapter driver (master only).
4 * Based on the TI DAVINCI I2C adapter driver.
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
10 * ----------------------------------------------------------------------------
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ----------------------------------------------------------------------------
28 #include <linux/export.h>
29 #include <linux/clk.h>
30 #include <linux/errno.h>
31 #include <linux/err.h>
32 #include <linux/i2c.h>
33 #include <linux/interrupt.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/delay.h>
37 #include <linux/module.h>
38 #include "i2c-designware-core.h"
45 #define DW_IC_DATA_CMD 0x10
46 #define DW_IC_SS_SCL_HCNT 0x14
47 #define DW_IC_SS_SCL_LCNT 0x18
48 #define DW_IC_FS_SCL_HCNT 0x1c
49 #define DW_IC_FS_SCL_LCNT 0x20
50 #define DW_IC_INTR_STAT 0x2c
51 #define DW_IC_INTR_MASK 0x30
52 #define DW_IC_RAW_INTR_STAT 0x34
53 #define DW_IC_RX_TL 0x38
54 #define DW_IC_TX_TL 0x3c
55 #define DW_IC_CLR_INTR 0x40
56 #define DW_IC_CLR_RX_UNDER 0x44
57 #define DW_IC_CLR_RX_OVER 0x48
58 #define DW_IC_CLR_TX_OVER 0x4c
59 #define DW_IC_CLR_RD_REQ 0x50
60 #define DW_IC_CLR_TX_ABRT 0x54
61 #define DW_IC_CLR_RX_DONE 0x58
62 #define DW_IC_CLR_ACTIVITY 0x5c
63 #define DW_IC_CLR_STOP_DET 0x60
64 #define DW_IC_CLR_START_DET 0x64
65 #define DW_IC_CLR_GEN_CALL 0x68
66 #define DW_IC_ENABLE 0x6c
67 #define DW_IC_STATUS 0x70
68 #define DW_IC_TXFLR 0x74
69 #define DW_IC_RXFLR 0x78
70 #define DW_IC_TX_ABRT_SOURCE 0x80
71 #define DW_IC_ENABLE_STATUS 0x9c
72 #define DW_IC_COMP_PARAM_1 0xf4
73 #define DW_IC_COMP_TYPE 0xfc
74 #define DW_IC_COMP_TYPE_VALUE 0x44570140
76 #define DW_IC_INTR_RX_UNDER 0x001
77 #define DW_IC_INTR_RX_OVER 0x002
78 #define DW_IC_INTR_RX_FULL 0x004
79 #define DW_IC_INTR_TX_OVER 0x008
80 #define DW_IC_INTR_TX_EMPTY 0x010
81 #define DW_IC_INTR_RD_REQ 0x020
82 #define DW_IC_INTR_TX_ABRT 0x040
83 #define DW_IC_INTR_RX_DONE 0x080
84 #define DW_IC_INTR_ACTIVITY 0x100
85 #define DW_IC_INTR_STOP_DET 0x200
86 #define DW_IC_INTR_START_DET 0x400
87 #define DW_IC_INTR_GEN_CALL 0x800
89 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
90 DW_IC_INTR_TX_EMPTY | \
91 DW_IC_INTR_TX_ABRT | \
94 #define DW_IC_STATUS_ACTIVITY 0x1
96 #define DW_IC_ERR_TX_ABRT 0x1
101 #define STATUS_IDLE 0x0
102 #define STATUS_WRITE_IN_PROGRESS 0x1
103 #define STATUS_READ_IN_PROGRESS 0x2
105 #define TIMEOUT 20 /* ms */
108 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
110 * only expected abort codes are listed here
111 * refer to the datasheet for the full list
113 #define ABRT_7B_ADDR_NOACK 0
114 #define ABRT_10ADDR1_NOACK 1
115 #define ABRT_10ADDR2_NOACK 2
116 #define ABRT_TXDATA_NOACK 3
117 #define ABRT_GCALL_NOACK 4
118 #define ABRT_GCALL_READ 5
119 #define ABRT_SBYTE_ACKDET 7
120 #define ABRT_SBYTE_NORSTRT 9
121 #define ABRT_10B_RD_NORSTRT 10
122 #define ABRT_MASTER_DIS 11
125 #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
126 #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
127 #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
128 #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
129 #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
130 #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
131 #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
132 #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
133 #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
134 #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
135 #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
137 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
138 DW_IC_TX_ABRT_10ADDR1_NOACK | \
139 DW_IC_TX_ABRT_10ADDR2_NOACK | \
140 DW_IC_TX_ABRT_TXDATA_NOACK | \
141 DW_IC_TX_ABRT_GCALL_NOACK)
143 static char *abort_sources[] = {
144 [ABRT_7B_ADDR_NOACK] =
145 "slave address not acknowledged (7bit mode)",
146 [ABRT_10ADDR1_NOACK] =
147 "first address byte not acknowledged (10bit mode)",
148 [ABRT_10ADDR2_NOACK] =
149 "second address byte not acknowledged (10bit mode)",
150 [ABRT_TXDATA_NOACK] =
151 "data not acknowledged",
153 "no acknowledgement for a general call",
155 "read after general call",
156 [ABRT_SBYTE_ACKDET] =
157 "start byte acknowledged",
158 [ABRT_SBYTE_NORSTRT] =
159 "trying to send start byte when restart is disabled",
160 [ABRT_10B_RD_NORSTRT] =
161 "trying to read when restart is disabled (10bit mode)",
163 "trying to use disabled adapter",
168 u32 dw_readl(struct dw_i2c_dev *dev, int offset)
172 if (dev->accessor_flags & ACCESS_16BIT)
173 value = readw(dev->base + offset) |
174 (readw(dev->base + offset + 2) << 16);
176 value = readl(dev->base + offset);
178 if (dev->accessor_flags & ACCESS_SWAP)
179 return swab32(value);
184 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
186 if (dev->accessor_flags & ACCESS_SWAP)
189 if (dev->accessor_flags & ACCESS_16BIT) {
190 writew((u16)b, dev->base + offset);
191 writew((u16)(b >> 16), dev->base + offset + 2);
193 writel(b, dev->base + offset);
198 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
201 * DesignWare I2C core doesn't seem to have solid strategy to meet
202 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
203 * will result in violation of the tHD;STA spec.
207 * Conditional expression:
209 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
211 * This is based on the DW manuals, and represents an ideal
212 * configuration. The resulting I2C bus speed will be
213 * faster than any of the others.
215 * If your hardware is free from tHD;STA issue, try this one.
217 return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset;
220 * Conditional expression:
222 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
224 * This is just experimental rule; the tHD;STA period turned
225 * out to be proportinal to (_HCNT + 3). With this setting,
226 * we could meet both tHIGH and tHD;STA timing specs.
228 * If unsure, you'd better to take this alternative.
230 * The reason why we need to take into account "tf" here,
231 * is the same as described in i2c_dw_scl_lcnt().
233 return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset;
236 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
239 * Conditional expression:
241 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
243 * DW I2C core starts counting the SCL CNTs for the LOW period
244 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
245 * In order to meet the tLOW timing spec, we need to take into
246 * account the fall time of SCL signal (tf). Default tf value
247 * should be 0.3 us, for safety.
249 return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset;
252 static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
257 dw_writel(dev, enable, DW_IC_ENABLE);
258 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
262 * Wait 10 times the signaling period of the highest I2C
263 * transfer supported by the driver (for 400KHz this is
264 * 25us) as described in the DesignWare I2C databook.
266 usleep_range(25, 250);
269 dev_warn(dev->dev, "timeout in %sabling adapter\n",
270 enable ? "en" : "dis");
274 * i2c_dw_init() - initialize the designware i2c master hardware
275 * @dev: device private data
277 * This functions configures and enables the I2C master.
278 * This function is called during I2C init function, and in case of timeout at
281 int i2c_dw_init(struct dw_i2c_dev *dev)
287 input_clock_khz = dev->get_clk_rate_khz(dev);
289 reg = dw_readl(dev, DW_IC_COMP_TYPE);
290 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
291 /* Configure register endianess access */
292 dev->accessor_flags |= ACCESS_SWAP;
293 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
294 /* Configure register access mode 16bit */
295 dev->accessor_flags |= ACCESS_16BIT;
296 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
297 dev_err(dev->dev, "Unknown Synopsys component type: "
302 /* Disable the adapter */
303 __i2c_dw_enable(dev, false);
305 /* set standard and fast speed deviders for high/low periods */
308 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
309 40, /* tHD;STA = tHIGH = 4.0 us */
311 0, /* 0: DW default, 1: Ideal */
313 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
314 47, /* tLOW = 4.7 us */
317 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
318 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
319 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
322 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
323 6, /* tHD;STA = tHIGH = 0.6 us */
325 0, /* 0: DW default, 1: Ideal */
327 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
328 13, /* tLOW = 1.3 us */
331 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
332 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
333 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
335 /* Configure Tx/Rx FIFO threshold levels */
336 dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL);
337 dw_writel(dev, 0, DW_IC_RX_TL);
339 /* configure the i2c master */
340 dw_writel(dev, dev->master_cfg , DW_IC_CON);
343 EXPORT_SYMBOL_GPL(i2c_dw_init);
346 * Waiting for bus not busy
348 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
350 int timeout = TIMEOUT;
352 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
354 dev_warn(dev->dev, "timeout waiting for bus ready\n");
358 usleep_range(1000, 1100);
364 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
366 struct i2c_msg *msgs = dev->msgs;
369 /* Disable the adapter */
370 __i2c_dw_enable(dev, false);
372 /* set the slave (target) address */
373 dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR);
375 /* if the slave address is ten bit address, enable 10BITADDR */
376 ic_con = dw_readl(dev, DW_IC_CON);
377 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
378 ic_con |= DW_IC_CON_10BITADDR_MASTER;
380 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
381 dw_writel(dev, ic_con, DW_IC_CON);
383 /* enforce disabled interrupts (due to HW issues) */
384 i2c_dw_disable_int(dev);
386 /* Enable the adapter */
387 __i2c_dw_enable(dev, true);
389 /* Clear and enable interrupts */
390 i2c_dw_clear_int(dev);
391 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
395 * Initiate (and continue) low level master read/write transaction.
396 * This function is only called from i2c_dw_isr, and pumping i2c_msg
397 * messages into the tx buffer. Even if the size of i2c_msg data is
398 * longer than the size of the tx buffer, it handles everything.
401 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
403 struct i2c_msg *msgs = dev->msgs;
405 int tx_limit, rx_limit;
406 u32 addr = msgs[dev->msg_write_idx].addr;
407 u32 buf_len = dev->tx_buf_len;
408 u8 *buf = dev->tx_buf;
410 intr_mask = DW_IC_INTR_DEFAULT_MASK;
412 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
414 * if target address has changed, we need to
415 * reprogram the target address in the i2c
416 * adapter when we are done with this transfer
418 if (msgs[dev->msg_write_idx].addr != addr) {
420 "%s: invalid target address\n", __func__);
421 dev->msg_err = -EINVAL;
425 if (msgs[dev->msg_write_idx].len == 0) {
427 "%s: invalid message length\n", __func__);
428 dev->msg_err = -EINVAL;
432 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
434 buf = msgs[dev->msg_write_idx].buf;
435 buf_len = msgs[dev->msg_write_idx].len;
438 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
439 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
441 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
445 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
446 * manually set the stop bit. However, it cannot be
447 * detected from the registers so we set it always
448 * when writing/reading the last byte.
450 if (dev->msg_write_idx == dev->msgs_num - 1 &&
454 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
456 /* avoid rx buffer overrun */
457 if (rx_limit - dev->rx_outstanding <= 0)
460 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
462 dev->rx_outstanding++;
464 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
465 tx_limit--; buf_len--;
469 dev->tx_buf_len = buf_len;
472 /* more bytes to be written */
473 dev->status |= STATUS_WRITE_IN_PROGRESS;
476 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
480 * If i2c_msg index search is completed, we don't need TX_EMPTY
481 * interrupt any more.
483 if (dev->msg_write_idx == dev->msgs_num)
484 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
489 dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
493 i2c_dw_read(struct dw_i2c_dev *dev)
495 struct i2c_msg *msgs = dev->msgs;
498 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
502 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
505 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
506 len = msgs[dev->msg_read_idx].len;
507 buf = msgs[dev->msg_read_idx].buf;
509 len = dev->rx_buf_len;
513 rx_valid = dw_readl(dev, DW_IC_RXFLR);
515 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
516 *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
517 dev->rx_outstanding--;
521 dev->status |= STATUS_READ_IN_PROGRESS;
522 dev->rx_buf_len = len;
526 dev->status &= ~STATUS_READ_IN_PROGRESS;
530 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
532 unsigned long abort_source = dev->abort_source;
535 if (abort_source & DW_IC_TX_ABRT_NOACK) {
536 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
538 "%s: %s\n", __func__, abort_sources[i]);
542 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
543 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
545 if (abort_source & DW_IC_TX_ARB_LOST)
547 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
548 return -EINVAL; /* wrong msgs[] data */
554 * Prepare controller for a transaction and call i2c_dw_xfer_msg
557 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
559 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
562 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
564 mutex_lock(&dev->lock);
565 pm_runtime_get_sync(dev->dev);
567 INIT_COMPLETION(dev->cmd_complete);
571 dev->msg_write_idx = 0;
572 dev->msg_read_idx = 0;
574 dev->status = STATUS_IDLE;
575 dev->abort_source = 0;
576 dev->rx_outstanding = 0;
578 ret = i2c_dw_wait_bus_not_busy(dev);
582 /* start the transfers */
583 i2c_dw_xfer_init(dev);
585 /* wait for tx to complete */
586 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ);
588 dev_err(dev->dev, "controller timed out\n");
601 if (likely(!dev->cmd_err)) {
602 /* Disable the adapter */
603 __i2c_dw_enable(dev, false);
608 /* We have an error */
609 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
610 ret = i2c_dw_handle_tx_abort(dev);
616 pm_runtime_mark_last_busy(dev->dev);
617 pm_runtime_put_autosuspend(dev->dev);
618 mutex_unlock(&dev->lock);
622 EXPORT_SYMBOL_GPL(i2c_dw_xfer);
624 u32 i2c_dw_func(struct i2c_adapter *adap)
626 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
627 return dev->functionality;
629 EXPORT_SYMBOL_GPL(i2c_dw_func);
631 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
636 * The IC_INTR_STAT register just indicates "enabled" interrupts.
637 * Ths unmasked raw version of interrupt status bits are available
638 * in the IC_RAW_INTR_STAT register.
641 * stat = dw_readl(IC_INTR_STAT);
643 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
645 * The raw version might be useful for debugging purposes.
647 stat = dw_readl(dev, DW_IC_INTR_STAT);
650 * Do not use the IC_CLR_INTR register to clear interrupts, or
651 * you'll miss some interrupts, triggered during the period from
652 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
654 * Instead, use the separately-prepared IC_CLR_* registers.
656 if (stat & DW_IC_INTR_RX_UNDER)
657 dw_readl(dev, DW_IC_CLR_RX_UNDER);
658 if (stat & DW_IC_INTR_RX_OVER)
659 dw_readl(dev, DW_IC_CLR_RX_OVER);
660 if (stat & DW_IC_INTR_TX_OVER)
661 dw_readl(dev, DW_IC_CLR_TX_OVER);
662 if (stat & DW_IC_INTR_RD_REQ)
663 dw_readl(dev, DW_IC_CLR_RD_REQ);
664 if (stat & DW_IC_INTR_TX_ABRT) {
666 * The IC_TX_ABRT_SOURCE register is cleared whenever
667 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
669 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
670 dw_readl(dev, DW_IC_CLR_TX_ABRT);
672 if (stat & DW_IC_INTR_RX_DONE)
673 dw_readl(dev, DW_IC_CLR_RX_DONE);
674 if (stat & DW_IC_INTR_ACTIVITY)
675 dw_readl(dev, DW_IC_CLR_ACTIVITY);
676 if (stat & DW_IC_INTR_STOP_DET)
677 dw_readl(dev, DW_IC_CLR_STOP_DET);
678 if (stat & DW_IC_INTR_START_DET)
679 dw_readl(dev, DW_IC_CLR_START_DET);
680 if (stat & DW_IC_INTR_GEN_CALL)
681 dw_readl(dev, DW_IC_CLR_GEN_CALL);
687 * Interrupt service routine. This gets called whenever an I2C interrupt
690 irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
692 struct dw_i2c_dev *dev = dev_id;
695 enabled = dw_readl(dev, DW_IC_ENABLE);
696 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
697 dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__,
698 dev->adapter.name, enabled, stat);
699 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
702 stat = i2c_dw_read_clear_intrbits(dev);
704 if (stat & DW_IC_INTR_TX_ABRT) {
705 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
706 dev->status = STATUS_IDLE;
709 * Anytime TX_ABRT is set, the contents of the tx/rx
710 * buffers are flushed. Make sure to skip them.
712 dw_writel(dev, 0, DW_IC_INTR_MASK);
716 if (stat & DW_IC_INTR_RX_FULL)
719 if (stat & DW_IC_INTR_TX_EMPTY)
720 i2c_dw_xfer_msg(dev);
723 * No need to modify or disable the interrupt mask here.
724 * i2c_dw_xfer_msg() will take care of it according to
725 * the current transmit status.
729 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
730 complete(&dev->cmd_complete);
734 EXPORT_SYMBOL_GPL(i2c_dw_isr);
736 void i2c_dw_enable(struct dw_i2c_dev *dev)
738 /* Enable the adapter */
739 __i2c_dw_enable(dev, true);
741 EXPORT_SYMBOL_GPL(i2c_dw_enable);
743 u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev)
745 return dw_readl(dev, DW_IC_ENABLE);
747 EXPORT_SYMBOL_GPL(i2c_dw_is_enabled);
749 void i2c_dw_disable(struct dw_i2c_dev *dev)
751 /* Disable controller */
752 __i2c_dw_enable(dev, false);
754 /* Disable all interupts */
755 dw_writel(dev, 0, DW_IC_INTR_MASK);
756 dw_readl(dev, DW_IC_CLR_INTR);
758 EXPORT_SYMBOL_GPL(i2c_dw_disable);
760 void i2c_dw_clear_int(struct dw_i2c_dev *dev)
762 dw_readl(dev, DW_IC_CLR_INTR);
764 EXPORT_SYMBOL_GPL(i2c_dw_clear_int);
766 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
768 dw_writel(dev, 0, DW_IC_INTR_MASK);
770 EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
772 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
774 return dw_readl(dev, DW_IC_COMP_PARAM_1);
776 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
778 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
779 MODULE_LICENSE("GPL");