2 * Synopsys DesignWare I2C adapter driver (master only).
4 * Based on the TI DAVINCI I2C adapter driver.
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
10 * ----------------------------------------------------------------------------
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ----------------------------------------------------------------------------
28 #include <linux/export.h>
29 #include <linux/errno.h>
30 #include <linux/err.h>
31 #include <linux/i2c.h>
32 #include <linux/interrupt.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/delay.h>
36 #include <linux/module.h>
37 #include "i2c-designware-core.h"
44 #define DW_IC_DATA_CMD 0x10
45 #define DW_IC_SS_SCL_HCNT 0x14
46 #define DW_IC_SS_SCL_LCNT 0x18
47 #define DW_IC_FS_SCL_HCNT 0x1c
48 #define DW_IC_FS_SCL_LCNT 0x20
49 #define DW_IC_INTR_STAT 0x2c
50 #define DW_IC_INTR_MASK 0x30
51 #define DW_IC_RAW_INTR_STAT 0x34
52 #define DW_IC_RX_TL 0x38
53 #define DW_IC_TX_TL 0x3c
54 #define DW_IC_CLR_INTR 0x40
55 #define DW_IC_CLR_RX_UNDER 0x44
56 #define DW_IC_CLR_RX_OVER 0x48
57 #define DW_IC_CLR_TX_OVER 0x4c
58 #define DW_IC_CLR_RD_REQ 0x50
59 #define DW_IC_CLR_TX_ABRT 0x54
60 #define DW_IC_CLR_RX_DONE 0x58
61 #define DW_IC_CLR_ACTIVITY 0x5c
62 #define DW_IC_CLR_STOP_DET 0x60
63 #define DW_IC_CLR_START_DET 0x64
64 #define DW_IC_CLR_GEN_CALL 0x68
65 #define DW_IC_ENABLE 0x6c
66 #define DW_IC_STATUS 0x70
67 #define DW_IC_TXFLR 0x74
68 #define DW_IC_RXFLR 0x78
69 #define DW_IC_SDA_HOLD 0x7c
70 #define DW_IC_TX_ABRT_SOURCE 0x80
71 #define DW_IC_ENABLE_STATUS 0x9c
72 #define DW_IC_COMP_PARAM_1 0xf4
73 #define DW_IC_COMP_VERSION 0xf8
74 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
75 #define DW_IC_COMP_TYPE 0xfc
76 #define DW_IC_COMP_TYPE_VALUE 0x44570140
78 #define DW_IC_INTR_RX_UNDER 0x001
79 #define DW_IC_INTR_RX_OVER 0x002
80 #define DW_IC_INTR_RX_FULL 0x004
81 #define DW_IC_INTR_TX_OVER 0x008
82 #define DW_IC_INTR_TX_EMPTY 0x010
83 #define DW_IC_INTR_RD_REQ 0x020
84 #define DW_IC_INTR_TX_ABRT 0x040
85 #define DW_IC_INTR_RX_DONE 0x080
86 #define DW_IC_INTR_ACTIVITY 0x100
87 #define DW_IC_INTR_STOP_DET 0x200
88 #define DW_IC_INTR_START_DET 0x400
89 #define DW_IC_INTR_GEN_CALL 0x800
91 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
92 DW_IC_INTR_TX_EMPTY | \
93 DW_IC_INTR_TX_ABRT | \
96 #define DW_IC_STATUS_ACTIVITY 0x1
98 #define DW_IC_ERR_TX_ABRT 0x1
100 #define DW_IC_TAR_10BITADDR_MASTER BIT(12)
105 #define STATUS_IDLE 0x0
106 #define STATUS_WRITE_IN_PROGRESS 0x1
107 #define STATUS_READ_IN_PROGRESS 0x2
109 #define TIMEOUT 20 /* ms */
112 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
114 * only expected abort codes are listed here
115 * refer to the datasheet for the full list
117 #define ABRT_7B_ADDR_NOACK 0
118 #define ABRT_10ADDR1_NOACK 1
119 #define ABRT_10ADDR2_NOACK 2
120 #define ABRT_TXDATA_NOACK 3
121 #define ABRT_GCALL_NOACK 4
122 #define ABRT_GCALL_READ 5
123 #define ABRT_SBYTE_ACKDET 7
124 #define ABRT_SBYTE_NORSTRT 9
125 #define ABRT_10B_RD_NORSTRT 10
126 #define ABRT_MASTER_DIS 11
129 #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
130 #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
131 #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
132 #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
133 #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
134 #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
135 #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
136 #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
137 #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
138 #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
139 #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
141 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
142 DW_IC_TX_ABRT_10ADDR1_NOACK | \
143 DW_IC_TX_ABRT_10ADDR2_NOACK | \
144 DW_IC_TX_ABRT_TXDATA_NOACK | \
145 DW_IC_TX_ABRT_GCALL_NOACK)
147 static char *abort_sources[] = {
148 [ABRT_7B_ADDR_NOACK] =
149 "slave address not acknowledged (7bit mode)",
150 [ABRT_10ADDR1_NOACK] =
151 "first address byte not acknowledged (10bit mode)",
152 [ABRT_10ADDR2_NOACK] =
153 "second address byte not acknowledged (10bit mode)",
154 [ABRT_TXDATA_NOACK] =
155 "data not acknowledged",
157 "no acknowledgement for a general call",
159 "read after general call",
160 [ABRT_SBYTE_ACKDET] =
161 "start byte acknowledged",
162 [ABRT_SBYTE_NORSTRT] =
163 "trying to send start byte when restart is disabled",
164 [ABRT_10B_RD_NORSTRT] =
165 "trying to read when restart is disabled (10bit mode)",
167 "trying to use disabled adapter",
172 u32 dw_readl(struct dw_i2c_dev *dev, int offset)
176 if (dev->accessor_flags & ACCESS_16BIT)
177 value = readw(dev->base + offset) |
178 (readw(dev->base + offset + 2) << 16);
180 value = readl(dev->base + offset);
182 if (dev->accessor_flags & ACCESS_SWAP)
183 return swab32(value);
188 void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
190 if (dev->accessor_flags & ACCESS_SWAP)
193 if (dev->accessor_flags & ACCESS_16BIT) {
194 writew((u16)b, dev->base + offset);
195 writew((u16)(b >> 16), dev->base + offset + 2);
197 writel(b, dev->base + offset);
202 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
205 * DesignWare I2C core doesn't seem to have solid strategy to meet
206 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
207 * will result in violation of the tHD;STA spec.
211 * Conditional expression:
213 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
215 * This is based on the DW manuals, and represents an ideal
216 * configuration. The resulting I2C bus speed will be
217 * faster than any of the others.
219 * If your hardware is free from tHD;STA issue, try this one.
221 return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset;
224 * Conditional expression:
226 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
228 * This is just experimental rule; the tHD;STA period turned
229 * out to be proportinal to (_HCNT + 3). With this setting,
230 * we could meet both tHIGH and tHD;STA timing specs.
232 * If unsure, you'd better to take this alternative.
234 * The reason why we need to take into account "tf" here,
235 * is the same as described in i2c_dw_scl_lcnt().
237 return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset;
240 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
243 * Conditional expression:
245 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
247 * DW I2C core starts counting the SCL CNTs for the LOW period
248 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
249 * In order to meet the tLOW timing spec, we need to take into
250 * account the fall time of SCL signal (tf). Default tf value
251 * should be 0.3 us, for safety.
253 return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset;
256 static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
261 dw_writel(dev, enable, DW_IC_ENABLE);
262 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
266 * Wait 10 times the signaling period of the highest I2C
267 * transfer supported by the driver (for 400KHz this is
268 * 25us) as described in the DesignWare I2C databook.
270 usleep_range(25, 250);
273 dev_warn(dev->dev, "timeout in %sabling adapter\n",
274 enable ? "en" : "dis");
278 * i2c_dw_init() - initialize the designware i2c master hardware
279 * @dev: device private data
281 * This functions configures and enables the I2C master.
282 * This function is called during I2C init function, and in case of timeout at
285 int i2c_dw_init(struct dw_i2c_dev *dev)
291 input_clock_khz = dev->get_clk_rate_khz(dev);
293 reg = dw_readl(dev, DW_IC_COMP_TYPE);
294 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
295 /* Configure register endianess access */
296 dev->accessor_flags |= ACCESS_SWAP;
297 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
298 /* Configure register access mode 16bit */
299 dev->accessor_flags |= ACCESS_16BIT;
300 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
301 dev_err(dev->dev, "Unknown Synopsys component type: "
306 /* Disable the adapter */
307 __i2c_dw_enable(dev, false);
309 /* set standard and fast speed deviders for high/low periods */
312 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
313 40, /* tHD;STA = tHIGH = 4.0 us */
315 0, /* 0: DW default, 1: Ideal */
317 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
318 47, /* tLOW = 4.7 us */
322 /* Allow platforms to specify the ideal HCNT and LCNT values */
323 if (dev->ss_hcnt && dev->ss_lcnt) {
327 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
328 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
329 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
332 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
333 6, /* tHD;STA = tHIGH = 0.6 us */
335 0, /* 0: DW default, 1: Ideal */
337 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
338 13, /* tLOW = 1.3 us */
342 if (dev->fs_hcnt && dev->fs_lcnt) {
346 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
347 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
348 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
350 /* Configure SDA Hold Time if required */
351 if (dev->sda_hold_time) {
352 reg = dw_readl(dev, DW_IC_COMP_VERSION);
353 if (reg >= DW_IC_SDA_HOLD_MIN_VERS)
354 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
357 "Hardware too old to adjust SDA hold time.");
360 /* Configure Tx/Rx FIFO threshold levels */
361 dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL);
362 dw_writel(dev, 0, DW_IC_RX_TL);
364 /* configure the i2c master */
365 dw_writel(dev, dev->master_cfg , DW_IC_CON);
368 EXPORT_SYMBOL_GPL(i2c_dw_init);
371 * Waiting for bus not busy
373 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
375 int timeout = TIMEOUT;
377 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
379 dev_warn(dev->dev, "timeout waiting for bus ready\n");
383 usleep_range(1000, 1100);
389 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
391 struct i2c_msg *msgs = dev->msgs;
392 u32 ic_con, ic_tar = 0;
394 /* Disable the adapter */
395 __i2c_dw_enable(dev, false);
397 /* if the slave address is ten bit address, enable 10BITADDR */
398 ic_con = dw_readl(dev, DW_IC_CON);
399 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
400 ic_con |= DW_IC_CON_10BITADDR_MASTER;
402 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
403 * mode has to be enabled via bit 12 of IC_TAR register.
404 * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
405 * detected from registers.
407 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
409 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
412 dw_writel(dev, ic_con, DW_IC_CON);
415 * Set the slave (target) address and enable 10-bit addressing mode
418 dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
420 /* enforce disabled interrupts (due to HW issues) */
421 i2c_dw_disable_int(dev);
423 /* Enable the adapter */
424 __i2c_dw_enable(dev, true);
426 /* Clear and enable interrupts */
427 i2c_dw_clear_int(dev);
428 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
432 * Initiate (and continue) low level master read/write transaction.
433 * This function is only called from i2c_dw_isr, and pumping i2c_msg
434 * messages into the tx buffer. Even if the size of i2c_msg data is
435 * longer than the size of the tx buffer, it handles everything.
438 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
440 struct i2c_msg *msgs = dev->msgs;
442 int tx_limit, rx_limit;
443 u32 addr = msgs[dev->msg_write_idx].addr;
444 u32 buf_len = dev->tx_buf_len;
445 u8 *buf = dev->tx_buf;
446 bool need_restart = false;
448 intr_mask = DW_IC_INTR_DEFAULT_MASK;
450 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
452 * if target address has changed, we need to
453 * reprogram the target address in the i2c
454 * adapter when we are done with this transfer
456 if (msgs[dev->msg_write_idx].addr != addr) {
458 "%s: invalid target address\n", __func__);
459 dev->msg_err = -EINVAL;
463 if (msgs[dev->msg_write_idx].len == 0) {
465 "%s: invalid message length\n", __func__);
466 dev->msg_err = -EINVAL;
470 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
472 buf = msgs[dev->msg_write_idx].buf;
473 buf_len = msgs[dev->msg_write_idx].len;
475 /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
476 * IC_RESTART_EN are set, we must manually
477 * set restart bit between messages.
479 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
480 (dev->msg_write_idx > 0))
484 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
485 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
487 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
491 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
492 * manually set the stop bit. However, it cannot be
493 * detected from the registers so we set it always
494 * when writing/reading the last byte.
496 if (dev->msg_write_idx == dev->msgs_num - 1 &&
502 need_restart = false;
505 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
507 /* avoid rx buffer overrun */
508 if (rx_limit - dev->rx_outstanding <= 0)
511 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
513 dev->rx_outstanding++;
515 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
516 tx_limit--; buf_len--;
520 dev->tx_buf_len = buf_len;
523 /* more bytes to be written */
524 dev->status |= STATUS_WRITE_IN_PROGRESS;
527 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
531 * If i2c_msg index search is completed, we don't need TX_EMPTY
532 * interrupt any more.
534 if (dev->msg_write_idx == dev->msgs_num)
535 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
540 dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
544 i2c_dw_read(struct dw_i2c_dev *dev)
546 struct i2c_msg *msgs = dev->msgs;
549 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
553 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
556 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
557 len = msgs[dev->msg_read_idx].len;
558 buf = msgs[dev->msg_read_idx].buf;
560 len = dev->rx_buf_len;
564 rx_valid = dw_readl(dev, DW_IC_RXFLR);
566 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
567 *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
568 dev->rx_outstanding--;
572 dev->status |= STATUS_READ_IN_PROGRESS;
573 dev->rx_buf_len = len;
577 dev->status &= ~STATUS_READ_IN_PROGRESS;
581 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
583 unsigned long abort_source = dev->abort_source;
586 if (abort_source & DW_IC_TX_ABRT_NOACK) {
587 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
589 "%s: %s\n", __func__, abort_sources[i]);
593 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
594 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
596 if (abort_source & DW_IC_TX_ARB_LOST)
598 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
599 return -EINVAL; /* wrong msgs[] data */
605 * Prepare controller for a transaction and call i2c_dw_xfer_msg
608 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
610 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
613 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
615 mutex_lock(&dev->lock);
616 pm_runtime_get_sync(dev->dev);
618 reinit_completion(&dev->cmd_complete);
622 dev->msg_write_idx = 0;
623 dev->msg_read_idx = 0;
625 dev->status = STATUS_IDLE;
626 dev->abort_source = 0;
627 dev->rx_outstanding = 0;
629 ret = i2c_dw_wait_bus_not_busy(dev);
633 /* start the transfers */
634 i2c_dw_xfer_init(dev);
636 /* wait for tx to complete */
637 ret = wait_for_completion_timeout(&dev->cmd_complete, HZ);
639 dev_err(dev->dev, "controller timed out\n");
640 /* i2c_dw_init implicitly disables the adapter */
647 * We must disable the adapter before unlocking the &dev->lock mutex
648 * below. Otherwise the hardware might continue generating interrupts
649 * which in turn causes a race condition with the following transfer.
650 * Needs some more investigation if the additional interrupts are
651 * a hardware bug or this driver doesn't handle them correctly yet.
653 __i2c_dw_enable(dev, false);
661 if (likely(!dev->cmd_err)) {
666 /* We have an error */
667 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
668 ret = i2c_dw_handle_tx_abort(dev);
674 pm_runtime_mark_last_busy(dev->dev);
675 pm_runtime_put_autosuspend(dev->dev);
676 mutex_unlock(&dev->lock);
680 EXPORT_SYMBOL_GPL(i2c_dw_xfer);
682 u32 i2c_dw_func(struct i2c_adapter *adap)
684 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
685 return dev->functionality;
687 EXPORT_SYMBOL_GPL(i2c_dw_func);
689 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
694 * The IC_INTR_STAT register just indicates "enabled" interrupts.
695 * Ths unmasked raw version of interrupt status bits are available
696 * in the IC_RAW_INTR_STAT register.
699 * stat = dw_readl(IC_INTR_STAT);
701 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
703 * The raw version might be useful for debugging purposes.
705 stat = dw_readl(dev, DW_IC_INTR_STAT);
708 * Do not use the IC_CLR_INTR register to clear interrupts, or
709 * you'll miss some interrupts, triggered during the period from
710 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
712 * Instead, use the separately-prepared IC_CLR_* registers.
714 if (stat & DW_IC_INTR_RX_UNDER)
715 dw_readl(dev, DW_IC_CLR_RX_UNDER);
716 if (stat & DW_IC_INTR_RX_OVER)
717 dw_readl(dev, DW_IC_CLR_RX_OVER);
718 if (stat & DW_IC_INTR_TX_OVER)
719 dw_readl(dev, DW_IC_CLR_TX_OVER);
720 if (stat & DW_IC_INTR_RD_REQ)
721 dw_readl(dev, DW_IC_CLR_RD_REQ);
722 if (stat & DW_IC_INTR_TX_ABRT) {
724 * The IC_TX_ABRT_SOURCE register is cleared whenever
725 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
727 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
728 dw_readl(dev, DW_IC_CLR_TX_ABRT);
730 if (stat & DW_IC_INTR_RX_DONE)
731 dw_readl(dev, DW_IC_CLR_RX_DONE);
732 if (stat & DW_IC_INTR_ACTIVITY)
733 dw_readl(dev, DW_IC_CLR_ACTIVITY);
734 if (stat & DW_IC_INTR_STOP_DET)
735 dw_readl(dev, DW_IC_CLR_STOP_DET);
736 if (stat & DW_IC_INTR_START_DET)
737 dw_readl(dev, DW_IC_CLR_START_DET);
738 if (stat & DW_IC_INTR_GEN_CALL)
739 dw_readl(dev, DW_IC_CLR_GEN_CALL);
745 * Interrupt service routine. This gets called whenever an I2C interrupt
748 irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
750 struct dw_i2c_dev *dev = dev_id;
753 enabled = dw_readl(dev, DW_IC_ENABLE);
754 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
755 dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__,
756 dev->adapter.name, enabled, stat);
757 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
760 stat = i2c_dw_read_clear_intrbits(dev);
762 if (stat & DW_IC_INTR_TX_ABRT) {
763 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
764 dev->status = STATUS_IDLE;
767 * Anytime TX_ABRT is set, the contents of the tx/rx
768 * buffers are flushed. Make sure to skip them.
770 dw_writel(dev, 0, DW_IC_INTR_MASK);
774 if (stat & DW_IC_INTR_RX_FULL)
777 if (stat & DW_IC_INTR_TX_EMPTY)
778 i2c_dw_xfer_msg(dev);
781 * No need to modify or disable the interrupt mask here.
782 * i2c_dw_xfer_msg() will take care of it according to
783 * the current transmit status.
787 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
788 complete(&dev->cmd_complete);
792 EXPORT_SYMBOL_GPL(i2c_dw_isr);
794 void i2c_dw_enable(struct dw_i2c_dev *dev)
796 /* Enable the adapter */
797 __i2c_dw_enable(dev, true);
799 EXPORT_SYMBOL_GPL(i2c_dw_enable);
801 u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev)
803 return dw_readl(dev, DW_IC_ENABLE);
805 EXPORT_SYMBOL_GPL(i2c_dw_is_enabled);
807 void i2c_dw_disable(struct dw_i2c_dev *dev)
809 /* Disable controller */
810 __i2c_dw_enable(dev, false);
812 /* Disable all interupts */
813 dw_writel(dev, 0, DW_IC_INTR_MASK);
814 dw_readl(dev, DW_IC_CLR_INTR);
816 EXPORT_SYMBOL_GPL(i2c_dw_disable);
818 void i2c_dw_clear_int(struct dw_i2c_dev *dev)
820 dw_readl(dev, DW_IC_CLR_INTR);
822 EXPORT_SYMBOL_GPL(i2c_dw_clear_int);
824 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
826 dw_writel(dev, 0, DW_IC_INTR_MASK);
828 EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
830 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
832 return dw_readl(dev, DW_IC_COMP_PARAM_1);
834 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
836 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
837 MODULE_LICENSE("GPL");