1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver.
5 * Based on the TI DAVINCI I2C adapter driver.
7 * Copyright (C) 2006 Texas Instruments.
8 * Copyright (C) 2007 MontaVista Software Inc.
9 * Copyright (C) 2009 Provigent Ltd.
11 #include <linux/acpi.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/errno.h>
17 #include <linux/export.h>
18 #include <linux/i2c.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regmap.h>
25 #include <linux/swab.h>
26 #include <linux/types.h>
27 #include <linux/units.h>
29 #include "i2c-designware-core.h"
31 static char *abort_sources[] = {
32 [ABRT_7B_ADDR_NOACK] =
33 "slave address not acknowledged (7bit mode)",
34 [ABRT_10ADDR1_NOACK] =
35 "first address byte not acknowledged (10bit mode)",
36 [ABRT_10ADDR2_NOACK] =
37 "second address byte not acknowledged (10bit mode)",
39 "data not acknowledged",
41 "no acknowledgement for a general call",
43 "read after general call",
45 "start byte acknowledged",
46 [ABRT_SBYTE_NORSTRT] =
47 "trying to send start byte when restart is disabled",
48 [ABRT_10B_RD_NORSTRT] =
49 "trying to read when restart is disabled (10bit mode)",
51 "trying to use disabled adapter",
54 [ABRT_SLAVE_FLUSH_TXFIFO] =
55 "read command so flush old data in the TX FIFO",
56 [ABRT_SLAVE_ARBLOST] =
57 "slave lost the bus while transmitting data to a remote master",
58 [ABRT_SLAVE_RD_INTX] =
59 "incorrect slave-transmitter mode configuration",
62 static int dw_reg_read(void *context, unsigned int reg, unsigned int *val)
64 struct dw_i2c_dev *dev = context;
66 *val = readl_relaxed(dev->base + reg);
71 static int dw_reg_write(void *context, unsigned int reg, unsigned int val)
73 struct dw_i2c_dev *dev = context;
75 writel_relaxed(val, dev->base + reg);
80 static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val)
82 struct dw_i2c_dev *dev = context;
84 *val = swab32(readl_relaxed(dev->base + reg));
89 static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val)
91 struct dw_i2c_dev *dev = context;
93 writel_relaxed(swab32(val), dev->base + reg);
98 static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val)
100 struct dw_i2c_dev *dev = context;
102 *val = readw_relaxed(dev->base + reg) |
103 (readw_relaxed(dev->base + reg + 2) << 16);
108 static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val)
110 struct dw_i2c_dev *dev = context;
112 writew_relaxed(val, dev->base + reg);
113 writew_relaxed(val >> 16, dev->base + reg + 2);
119 * i2c_dw_init_regmap() - Initialize registers map
120 * @dev: device private data
122 * Autodetects needed register access mode and creates the regmap with
123 * corresponding read/write callbacks. This must be called before doing any
124 * other register access.
126 int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
128 struct regmap_config map_cfg = {
132 .disable_locking = true,
133 .reg_read = dw_reg_read,
134 .reg_write = dw_reg_write,
135 .max_register = DW_IC_COMP_TYPE,
141 * Skip detecting the registers map configuration if the regmap has
142 * already been provided by a higher code.
147 ret = i2c_dw_acquire_lock(dev);
151 reg = readl(dev->base + DW_IC_COMP_TYPE);
152 i2c_dw_release_lock(dev);
154 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU)
155 map_cfg.max_register = AMD_UCSI_INTR_REG;
157 if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
158 map_cfg.reg_read = dw_reg_read_swab;
159 map_cfg.reg_write = dw_reg_write_swab;
160 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
161 map_cfg.reg_read = dw_reg_read_word;
162 map_cfg.reg_write = dw_reg_write_word;
163 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
165 "Unknown Synopsys component type: 0x%08x\n", reg);
170 * Note we'll check the return value of the regmap IO accessors only
171 * at the probe stage. The rest of the code won't do this because
172 * basically we have MMIO-based regmap so non of the read/write methods
175 dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg);
176 if (IS_ERR(dev->map)) {
177 dev_err(dev->dev, "Failed to init the registers map\n");
178 return PTR_ERR(dev->map);
184 static const u32 supported_speeds[] = {
185 I2C_MAX_HIGH_SPEED_MODE_FREQ,
186 I2C_MAX_FAST_MODE_PLUS_FREQ,
187 I2C_MAX_FAST_MODE_FREQ,
188 I2C_MAX_STANDARD_MODE_FREQ,
191 int i2c_dw_validate_speed(struct dw_i2c_dev *dev)
193 struct i2c_timings *t = &dev->timings;
197 * Only standard mode at 100kHz, fast mode at 400kHz,
198 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported.
200 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
201 if (t->bus_freq_hz == supported_speeds[i])
206 "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n",
211 EXPORT_SYMBOL_GPL(i2c_dw_validate_speed);
215 #include <linux/dmi.h>
218 * The HCNT/LCNT information coming from ACPI should be the most accurate
219 * for given platform. However, some systems get it wrong. On such systems
220 * we get better results by calculating those based on the input clock.
222 static const struct dmi_system_id i2c_dw_no_acpi_params[] = {
224 .ident = "Dell Inspiron 7348",
226 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
227 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"),
233 static void i2c_dw_acpi_params(struct device *device, char method[],
234 u16 *hcnt, u16 *lcnt, u32 *sda_hold)
236 struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
237 acpi_handle handle = ACPI_HANDLE(device);
238 union acpi_object *obj;
240 if (dmi_check_system(i2c_dw_no_acpi_params))
243 if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf)))
246 obj = (union acpi_object *)buf.pointer;
247 if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {
248 const union acpi_object *objs = obj->package.elements;
250 *hcnt = (u16)objs[0].integer.value;
251 *lcnt = (u16)objs[1].integer.value;
252 *sda_hold = (u32)objs[2].integer.value;
258 int i2c_dw_acpi_configure(struct device *device)
260 struct dw_i2c_dev *dev = dev_get_drvdata(device);
261 struct i2c_timings *t = &dev->timings;
262 u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0;
265 * Try to get SDA hold time and *CNT values from an ACPI method for
266 * selected speed modes.
268 i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);
269 i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);
270 i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);
271 i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);
273 switch (t->bus_freq_hz) {
274 case I2C_MAX_STANDARD_MODE_FREQ:
275 dev->sda_hold_time = ss_ht;
277 case I2C_MAX_FAST_MODE_PLUS_FREQ:
278 dev->sda_hold_time = fp_ht;
280 case I2C_MAX_HIGH_SPEED_MODE_FREQ:
281 dev->sda_hold_time = hs_ht;
283 case I2C_MAX_FAST_MODE_FREQ:
285 dev->sda_hold_time = fs_ht;
291 EXPORT_SYMBOL_GPL(i2c_dw_acpi_configure);
293 static u32 i2c_dw_acpi_round_bus_speed(struct device *device)
298 acpi_speed = i2c_acpi_find_bus_speed(device);
300 * Some DSTDs use a non standard speed, round down to the lowest
303 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
304 if (acpi_speed >= supported_speeds[i])
305 return supported_speeds[i];
311 #else /* CONFIG_ACPI */
313 static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; }
315 #endif /* CONFIG_ACPI */
317 void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev)
319 u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev);
320 struct i2c_timings *t = &dev->timings;
323 * Find bus speed from the "clock-frequency" device property, ACPI
324 * or by using fast mode if neither is set.
326 if (acpi_speed && t->bus_freq_hz)
327 t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);
328 else if (acpi_speed || t->bus_freq_hz)
329 t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
331 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
333 EXPORT_SYMBOL_GPL(i2c_dw_adjust_bus_speed);
335 u32 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
338 * DesignWare I2C core doesn't seem to have solid strategy to meet
339 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
340 * will result in violation of the tHD;STA spec.
344 * Conditional expression:
346 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
348 * This is based on the DW manuals, and represents an ideal
349 * configuration. The resulting I2C bus speed will be
350 * faster than any of the others.
352 * If your hardware is free from tHD;STA issue, try this one.
354 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * tSYMBOL, MICRO) -
358 * Conditional expression:
360 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
362 * This is just experimental rule; the tHD;STA period turned
363 * out to be proportinal to (_HCNT + 3). With this setting,
364 * we could meet both tHIGH and tHD;STA timing specs.
366 * If unsure, you'd better to take this alternative.
368 * The reason why we need to take into account "tf" here,
369 * is the same as described in i2c_dw_scl_lcnt().
371 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tSYMBOL + tf), MICRO) -
375 u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
378 * Conditional expression:
380 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
382 * DW I2C core starts counting the SCL CNTs for the LOW period
383 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
384 * In order to meet the tLOW timing spec, we need to take into
385 * account the fall time of SCL signal (tf). Default tf value
386 * should be 0.3 us, for safety.
388 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) -
392 int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev)
397 ret = i2c_dw_acquire_lock(dev);
401 /* Configure SDA Hold Time if required */
402 ret = regmap_read(dev->map, DW_IC_COMP_VERSION, ®);
404 goto err_release_lock;
406 if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
407 if (!dev->sda_hold_time) {
408 /* Keep previous hold time setting if no one set it */
409 ret = regmap_read(dev->map, DW_IC_SDA_HOLD,
410 &dev->sda_hold_time);
412 goto err_release_lock;
416 * Workaround for avoiding TX arbitration lost in case I2C
417 * slave pulls SDA down "too quickly" after falling edge of
418 * SCL by enabling non-zero SDA RX hold. Specification says it
419 * extends incoming SDA low to high transition while SCL is
420 * high but it appears to help also above issue.
422 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
423 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
425 dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",
426 dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK,
427 dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT);
428 } else if (dev->set_sda_hold_time) {
429 dev->set_sda_hold_time(dev);
430 } else if (dev->sda_hold_time) {
432 "Hardware too old to adjust SDA hold time.\n");
433 dev->sda_hold_time = 0;
437 i2c_dw_release_lock(dev);
442 void __i2c_dw_disable(struct dw_i2c_dev *dev)
448 __i2c_dw_disable_nowait(dev);
450 * The enable status register may be unimplemented, but
451 * in that case this test reads zero and exits the loop.
453 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status);
454 if ((status & 1) == 0)
458 * Wait 10 times the signaling period of the highest I2C
459 * transfer supported by the driver (for 400KHz this is
460 * 25us) as described in the DesignWare I2C databook.
462 usleep_range(25, 250);
465 dev_warn(dev->dev, "timeout in disabling adapter\n");
468 u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev)
471 * Clock is not necessary if we got LCNT/HCNT values directly from
474 if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
476 return dev->get_clk_rate_khz(dev);
479 int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
484 /* Optional interface clock */
485 ret = clk_prepare_enable(dev->pclk);
489 ret = clk_prepare_enable(dev->clk);
491 clk_disable_unprepare(dev->pclk);
496 clk_disable_unprepare(dev->clk);
497 clk_disable_unprepare(dev->pclk);
501 EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk);
503 int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
507 if (!dev->acquire_lock)
510 ret = dev->acquire_lock();
514 dev_err(dev->dev, "couldn't acquire bus ownership\n");
519 void i2c_dw_release_lock(struct dw_i2c_dev *dev)
521 if (dev->release_lock)
526 * Waiting for bus not busy
528 int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
533 ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,
534 !(status & DW_IC_STATUS_ACTIVITY),
537 dev_warn(dev->dev, "timeout waiting for bus ready\n");
539 i2c_recover_bus(&dev->adapter);
541 regmap_read(dev->map, DW_IC_STATUS, &status);
542 if (!(status & DW_IC_STATUS_ACTIVITY))
549 int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
551 unsigned long abort_source = dev->abort_source;
554 if (abort_source & DW_IC_TX_ABRT_NOACK) {
555 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
557 "%s: %s\n", __func__, abort_sources[i]);
561 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
562 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
564 if (abort_source & DW_IC_TX_ARB_LOST)
566 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
567 return -EINVAL; /* wrong msgs[] data */
572 int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
574 u32 tx_fifo_depth, rx_fifo_depth;
578 /* DW_IC_COMP_PARAM_1 not implement for IP issue */
579 if ((dev->flags & MODEL_MASK) == MODEL_WANGXUN_SP) {
580 dev->tx_fifo_depth = TXGBE_TX_FIFO_DEPTH;
581 dev->rx_fifo_depth = TXGBE_RX_FIFO_DEPTH;
587 * Try to detect the FIFO depth if not set by interface driver,
588 * the depth could be from 2 to 256 from HW spec.
590 ret = i2c_dw_acquire_lock(dev);
594 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, ¶m);
595 i2c_dw_release_lock(dev);
599 tx_fifo_depth = ((param >> 16) & 0xff) + 1;
600 rx_fifo_depth = ((param >> 8) & 0xff) + 1;
601 if (!dev->tx_fifo_depth) {
602 dev->tx_fifo_depth = tx_fifo_depth;
603 dev->rx_fifo_depth = rx_fifo_depth;
604 } else if (tx_fifo_depth >= 2) {
605 dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth,
607 dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth,
614 u32 i2c_dw_func(struct i2c_adapter *adap)
616 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
618 return dev->functionality;
621 void i2c_dw_disable(struct dw_i2c_dev *dev)
626 ret = i2c_dw_acquire_lock(dev);
630 /* Disable controller */
631 __i2c_dw_disable(dev);
633 /* Disable all interrupts */
634 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
635 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
637 i2c_dw_release_lock(dev);
640 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
641 MODULE_LICENSE("GPL");