drivers/i2c/busses/i2c-at91.c

   1 /*
   2  *  i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
   3  *
   4  *  Copyright (C) 2011 Weinmann Medical GmbH
   5  *  Author: Nikolaus Voss <n.voss@weinmann.de>
   6  *
   7  *  Evolved from original work by:
   8  *  Copyright (C) 2004 Rick Bronson
   9  *  Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
  10  *
  11  *  Borrowed heavily from original work by:
  12  *  Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
  13  *
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License as published by
  16  *  the Free Software Foundation; either version 2 of the License, or
  17  *  (at your option) any later version.
  18  */
  19
  20 #include <linux/clk.h>
  21 #include <linux/completion.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/err.h>
  25 #include <linux/i2c.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/of.h>
  30 #include <linux/of_device.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/slab.h>
  33 #include <linux/platform_data/dma-atmel.h>
  34
  35 #define TWI_CLK_HZ              100000                  /* max 400 Kbits/s */
  36 #define AT91_I2C_TIMEOUT        msecs_to_jiffies(100)   /* transfer timeout */
  37 #define AT91_I2C_DMA_THRESHOLD  8                       /* enable DMA if transfer size is bigger than this threshold */
  38
  39 /* AT91 TWI register definitions */
  40 #define AT91_TWI_CR             0x0000  /* Control Register */
  41 #define AT91_TWI_START          0x0001  /* Send a Start Condition */
  42 #define AT91_TWI_STOP           0x0002  /* Send a Stop Condition */
  43 #define AT91_TWI_MSEN           0x0004  /* Master Transfer Enable */
  44 #define AT91_TWI_SVDIS          0x0020  /* Slave Transfer Disable */
  45 #define AT91_TWI_QUICK          0x0040  /* SMBus quick command */
  46 #define AT91_TWI_SWRST          0x0080  /* Software Reset */
  47
  48 #define AT91_TWI_MMR            0x0004  /* Master Mode Register */
  49 #define AT91_TWI_IADRSZ_1       0x0100  /* Internal Device Address Size */
  50 #define AT91_TWI_MREAD          0x1000  /* Master Read Direction */
  51
  52 #define AT91_TWI_IADR           0x000c  /* Internal Address Register */
  53
  54 #define AT91_TWI_CWGR           0x0010  /* Clock Waveform Generator Reg */
  55
  56 #define AT91_TWI_SR             0x0020  /* Status Register */
  57 #define AT91_TWI_TXCOMP         0x0001  /* Transmission Complete */
  58 #define AT91_TWI_RXRDY          0x0002  /* Receive Holding Register Ready */
  59 #define AT91_TWI_TXRDY          0x0004  /* Transmit Holding Register Ready */
  60
  61 #define AT91_TWI_OVRE           0x0040  /* Overrun Error */
  62 #define AT91_TWI_UNRE           0x0080  /* Underrun Error */
  63 #define AT91_TWI_NACK           0x0100  /* Not Acknowledged */
  64
  65 #define AT91_TWI_IER            0x0024  /* Interrupt Enable Register */
  66 #define AT91_TWI_IDR            0x0028  /* Interrupt Disable Register */
  67 #define AT91_TWI_IMR            0x002c  /* Interrupt Mask Register */
  68 #define AT91_TWI_RHR            0x0030  /* Receive Holding Register */
  69 #define AT91_TWI_THR            0x0034  /* Transmit Holding Register */
  70
  71 struct at91_twi_pdata {
  72         unsigned clk_max_div;
  73         unsigned clk_offset;
  74         bool has_unre_flag;
  75         bool has_dma_support;
  76         struct at_dma_slave dma_slave;
  77 };
  78
  79 struct at91_twi_dma {
  80         struct dma_chan *chan_rx;
  81         struct dma_chan *chan_tx;
  82         struct scatterlist sg;
  83         struct dma_async_tx_descriptor *data_desc;
  84         enum dma_data_direction direction;
  85         bool buf_mapped;
  86         bool xfer_in_progress;
  87 };
  88
  89 struct at91_twi_dev {
  90         struct device *dev;
  91         void __iomem *base;
  92         struct completion cmd_complete;
  93         struct clk *clk;
  94         u8 *buf;
  95         size_t buf_len;
  96         struct i2c_msg *msg;
  97         int irq;
  98         unsigned imr;
  99         unsigned transfer_status;
 100         struct i2c_adapter adapter;
 101         unsigned twi_cwgr_reg;
 102         struct at91_twi_pdata *pdata;
 103         bool use_dma;
 104         struct at91_twi_dma dma;
 105 };
 106
 107 static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
 108 {
 109         return readl_relaxed(dev->base + reg);
 110 }
 111
 112 static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
 113 {
 114         writel_relaxed(val, dev->base + reg);
 115 }
 116
 117 static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
 118 {
 119         at91_twi_write(dev, AT91_TWI_IDR,
 120                        AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY);
 121 }
 122
 123 static void at91_twi_irq_save(struct at91_twi_dev *dev)
 124 {
 125         dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & 0x7;
 126         at91_disable_twi_interrupts(dev);
 127 }
 128
 129 static void at91_twi_irq_restore(struct at91_twi_dev *dev)
 130 {
 131         at91_twi_write(dev, AT91_TWI_IER, dev->imr);
 132 }
 133
 134 static void at91_init_twi_bus(struct at91_twi_dev *dev)
 135 {
 136         at91_disable_twi_interrupts(dev);
 137         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
 138         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
 139         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
 140         at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
 141 }
 142
 143 /*
 144  * Calculate symmetric clock as stated in datasheet:
 145  * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
 146  */
 147 static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
 148 {
 149         int ckdiv, cdiv, div;
 150         struct at91_twi_pdata *pdata = dev->pdata;
 151         int offset = pdata->clk_offset;
 152         int max_ckdiv = pdata->clk_max_div;
 153
 154         div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
 155                                        2 * twi_clk) - offset);
 156         ckdiv = fls(div >> 8);
 157         cdiv = div >> ckdiv;
 158
 159         if (ckdiv > max_ckdiv) {
 160                 dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
 161                          ckdiv, max_ckdiv);
 162                 ckdiv = max_ckdiv;
 163                 cdiv = 255;
 164         }
 165
 166         dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
 167         dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
 168 }
 169
 170 static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
 171 {
 172         struct at91_twi_dma *dma = &dev->dma;
 173
 174         at91_twi_irq_save(dev);
 175
 176         if (dma->xfer_in_progress) {
 177                 if (dma->direction == DMA_FROM_DEVICE)
 178                         dmaengine_terminate_all(dma->chan_rx);
 179                 else
 180                         dmaengine_terminate_all(dma->chan_tx);
 181                 dma->xfer_in_progress = false;
 182         }
 183         if (dma->buf_mapped) {
 184                 dma_unmap_single(dev->dev, sg_dma_address(&dma->sg),
 185                                  dev->buf_len, dma->direction);
 186                 dma->buf_mapped = false;
 187         }
 188
 189         at91_twi_irq_restore(dev);
 190 }
 191
 192 static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
 193 {
 194         if (dev->buf_len <= 0)
 195                 return;
 196
 197         at91_twi_write(dev, AT91_TWI_THR, *dev->buf);
 198
 199         /* send stop when last byte has been written */
 200         if (--dev->buf_len == 0)
 201                 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
 202
 203         dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len);
 204
 205         ++dev->buf;
 206 }
 207
 208 static void at91_twi_write_data_dma_callback(void *data)
 209 {
 210         struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
 211
 212         dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg),
 213                          dev->buf_len, DMA_MEM_TO_DEV);
 214
 215         at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
 216 }
 217
 218 static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
 219 {
 220         dma_addr_t dma_addr;
 221         struct dma_async_tx_descriptor *txdesc;
 222         struct at91_twi_dma *dma = &dev->dma;
 223         struct dma_chan *chan_tx = dma->chan_tx;
 224
 225         if (dev->buf_len <= 0)
 226                 return;
 227
 228         dma->direction = DMA_TO_DEVICE;
 229
 230         at91_twi_irq_save(dev);
 231         dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len,
 232                                   DMA_TO_DEVICE);
 233         if (dma_mapping_error(dev->dev, dma_addr)) {
 234                 dev_err(dev->dev, "dma map failed\n");
 235                 return;
 236         }
 237         dma->buf_mapped = true;
 238         at91_twi_irq_restore(dev);
 239         sg_dma_len(&dma->sg) = dev->buf_len;
 240         sg_dma_address(&dma->sg) = dma_addr;
 241
 242         txdesc = dmaengine_prep_slave_sg(chan_tx, &dma->sg, 1, DMA_MEM_TO_DEV,
 243                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 244         if (!txdesc) {
 245                 dev_err(dev->dev, "dma prep slave sg failed\n");
 246                 goto error;
 247         }
 248
 249         txdesc->callback = at91_twi_write_data_dma_callback;
 250         txdesc->callback_param = dev;
 251
 252         dma->xfer_in_progress = true;
 253         dmaengine_submit(txdesc);
 254         dma_async_issue_pending(chan_tx);
 255
 256         return;
 257
 258 error:
 259         at91_twi_dma_cleanup(dev);
 260 }
 261
 262 static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
 263 {
 264         if (dev->buf_len <= 0)
 265                 return;
 266
 267         *dev->buf = at91_twi_read(dev, AT91_TWI_RHR) & 0xff;
 268         --dev->buf_len;
 269
 270         /* handle I2C_SMBUS_BLOCK_DATA */
 271         if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) {
 272                 dev->msg->flags &= ~I2C_M_RECV_LEN;
 273                 dev->buf_len += *dev->buf;
 274                 dev->msg->len = dev->buf_len + 1;
 275                 dev_dbg(dev->dev, "received block length %d\n", dev->buf_len);
 276         }
 277
 278         /* send stop if second but last byte has been read */
 279         if (dev->buf_len == 1)
 280                 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
 281
 282         dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len);
 283
 284         ++dev->buf;
 285 }
 286
 287 static void at91_twi_read_data_dma_callback(void *data)
 288 {
 289         struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
 290
 291         dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg),
 292                          dev->buf_len, DMA_DEV_TO_MEM);
 293
 294         /* The last two bytes have to be read without using dma */
 295         dev->buf += dev->buf_len - 2;
 296         dev->buf_len = 2;
 297         at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_RXRDY);
 298 }
 299
 300 static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
 301 {
 302         dma_addr_t dma_addr;
 303         struct dma_async_tx_descriptor *rxdesc;
 304         struct at91_twi_dma *dma = &dev->dma;
 305         struct dma_chan *chan_rx = dma->chan_rx;
 306
 307         dma->direction = DMA_FROM_DEVICE;
 308
 309         /* Keep in mind that we won't use dma to read the last two bytes */
 310         at91_twi_irq_save(dev);
 311         dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len - 2,
 312                                   DMA_FROM_DEVICE);
 313         if (dma_mapping_error(dev->dev, dma_addr)) {
 314                 dev_err(dev->dev, "dma map failed\n");
 315                 return;
 316         }
 317         dma->buf_mapped = true;
 318         at91_twi_irq_restore(dev);
 319         dma->sg.dma_address = dma_addr;
 320         sg_dma_len(&dma->sg) = dev->buf_len - 2;
 321
 322         rxdesc = dmaengine_prep_slave_sg(chan_rx, &dma->sg, 1, DMA_DEV_TO_MEM,
 323                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 324         if (!rxdesc) {
 325                 dev_err(dev->dev, "dma prep slave sg failed\n");
 326                 goto error;
 327         }
 328
 329         rxdesc->callback = at91_twi_read_data_dma_callback;
 330         rxdesc->callback_param = dev;
 331
 332         dma->xfer_in_progress = true;
 333         dmaengine_submit(rxdesc);
 334         dma_async_issue_pending(dma->chan_rx);
 335
 336         return;
 337
 338 error:
 339         at91_twi_dma_cleanup(dev);
 340 }
 341
 342 static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
 343 {
 344         struct at91_twi_dev *dev = dev_id;
 345         const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
 346         const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
 347
 348         if (!irqstatus)
 349                 return IRQ_NONE;
 350         else if (irqstatus & AT91_TWI_RXRDY)
 351                 at91_twi_read_next_byte(dev);
 352         else if (irqstatus & AT91_TWI_TXRDY)
 353                 at91_twi_write_next_byte(dev);
 354
 355         /* catch error flags */
 356         dev->transfer_status |= status;
 357
 358         if (irqstatus & AT91_TWI_TXCOMP) {
 359                 at91_disable_twi_interrupts(dev);
 360                 complete(&dev->cmd_complete);
 361         }
 362
 363         return IRQ_HANDLED;
 364 }
 365
 366 static int at91_do_twi_transfer(struct at91_twi_dev *dev)
 367 {
 368         int ret;
 369         bool has_unre_flag = dev->pdata->has_unre_flag;
 370
 371         dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
 372                 (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
 373
 374         reinit_completion(&dev->cmd_complete);
 375         dev->transfer_status = 0;
 376
 377         if (!dev->buf_len) {
 378                 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
 379                 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
 380         } else if (dev->msg->flags & I2C_M_RD) {
 381                 unsigned start_flags = AT91_TWI_START;
 382
 383                 if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) {
 384                         dev_err(dev->dev, "RXRDY still set!");
 385                         at91_twi_read(dev, AT91_TWI_RHR);
 386                 }
 387
 388                 /* if only one byte is to be read, immediately stop transfer */
 389                 if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN))
 390                         start_flags |= AT91_TWI_STOP;
 391                 at91_twi_write(dev, AT91_TWI_CR, start_flags);
 392                 /*
 393                  * When using dma, the last byte has to be read manually in
 394                  * order to not send the stop command too late and then
 395                  * to receive extra data. In practice, there are some issues
 396                  * if you use the dma to read n-1 bytes because of latency.
 397                  * Reading n-2 bytes with dma and the two last ones manually
 398                  * seems to be the best solution.
 399                  */
 400                 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
 401                         at91_twi_read_data_dma(dev);
 402                         /*
 403                          * It is important to enable TXCOMP irq here because
 404                          * doing it only when transferring the last two bytes
 405                          * will mask NACK errors since TXCOMP is set when a
 406                          * NACK occurs.
 407                          */
 408                         at91_twi_write(dev, AT91_TWI_IER,
 409                                AT91_TWI_TXCOMP);
 410                 } else
 411                         at91_twi_write(dev, AT91_TWI_IER,
 412                                AT91_TWI_TXCOMP | AT91_TWI_RXRDY);
 413         } else {
 414                 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
 415                         at91_twi_write_data_dma(dev);
 416                         at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
 417                 } else {
 418                         at91_twi_write_next_byte(dev);
 419                         at91_twi_write(dev, AT91_TWI_IER,
 420                                 AT91_TWI_TXCOMP | AT91_TWI_TXRDY);
 421                 }
 422         }
 423
 424         ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
 425                                                         dev->adapter.timeout);
 426         if (ret == 0) {
 427                 dev_err(dev->dev, "controller timed out\n");
 428                 at91_init_twi_bus(dev);
 429                 ret = -ETIMEDOUT;
 430                 goto error;
 431         }
 432         if (dev->transfer_status & AT91_TWI_NACK) {
 433                 dev_dbg(dev->dev, "received nack\n");
 434                 ret = -EREMOTEIO;
 435                 goto error;
 436         }
 437         if (dev->transfer_status & AT91_TWI_OVRE) {
 438                 dev_err(dev->dev, "overrun while reading\n");
 439                 ret = -EIO;
 440                 goto error;
 441         }
 442         if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
 443                 dev_err(dev->dev, "underrun while writing\n");
 444                 ret = -EIO;
 445                 goto error;
 446         }
 447         dev_dbg(dev->dev, "transfer complete\n");
 448
 449         return 0;
 450
 451 error:
 452         at91_twi_dma_cleanup(dev);
 453         return ret;
 454 }
 455
 456 static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
 457 {
 458         struct at91_twi_dev *dev = i2c_get_adapdata(adap);
 459         int ret;
 460         unsigned int_addr_flag = 0;
 461         struct i2c_msg *m_start = msg;
 462
 463         dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
 464
 465         /*
 466          * The hardware can handle at most two messages concatenated by a
 467          * repeated start via it's internal address feature.
 468          */
 469         if (num > 2) {
 470                 dev_err(dev->dev,
 471                         "cannot handle more than two concatenated messages.\n");
 472                 return 0;
 473         } else if (num == 2) {
 474                 int internal_address = 0;
 475                 int i;
 476
 477                 if (msg->flags & I2C_M_RD) {
 478                         dev_err(dev->dev, "first transfer must be write.\n");
 479                         return -EINVAL;
 480                 }
 481                 if (msg->len > 3) {
 482                         dev_err(dev->dev, "first message size must be <= 3.\n");
 483                         return -EINVAL;
 484                 }
 485
 486                 /* 1st msg is put into the internal address, start with 2nd */
 487                 m_start = &msg[1];
 488                 for (i = 0; i < msg->len; ++i) {
 489                         const unsigned addr = msg->buf[msg->len - 1 - i];
 490
 491                         internal_address |= addr << (8 * i);
 492                         int_addr_flag += AT91_TWI_IADRSZ_1;
 493                 }
 494                 at91_twi_write(dev, AT91_TWI_IADR, internal_address);
 495         }
 496
 497         at91_twi_write(dev, AT91_TWI_MMR, (m_start->addr << 16) | int_addr_flag
 498                        | ((m_start->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0));
 499
 500         dev->buf_len = m_start->len;
 501         dev->buf = m_start->buf;
 502         dev->msg = m_start;
 503
 504         ret = at91_do_twi_transfer(dev);
 505
 506         return (ret < 0) ? ret : num;
 507 }
 508
 509 static u32 at91_twi_func(struct i2c_adapter *adapter)
 510 {
 511         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
 512                 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
 513 }
 514
 515 static struct i2c_algorithm at91_twi_algorithm = {
 516         .master_xfer    = at91_twi_xfer,
 517         .functionality  = at91_twi_func,
 518 };
 519
 520 static struct at91_twi_pdata at91rm9200_config = {
 521         .clk_max_div = 5,
 522         .clk_offset = 3,
 523         .has_unre_flag = true,
 524         .has_dma_support = false,
 525 };
 526
 527 static struct at91_twi_pdata at91sam9261_config = {
 528         .clk_max_div = 5,
 529         .clk_offset = 4,
 530         .has_unre_flag = false,
 531         .has_dma_support = false,
 532 };
 533
 534 static struct at91_twi_pdata at91sam9260_config = {
 535         .clk_max_div = 7,
 536         .clk_offset = 4,
 537         .has_unre_flag = false,
 538         .has_dma_support = false,
 539 };
 540
 541 static struct at91_twi_pdata at91sam9g20_config = {
 542         .clk_max_div = 7,
 543         .clk_offset = 4,
 544         .has_unre_flag = false,
 545         .has_dma_support = false,
 546 };
 547
 548 static struct at91_twi_pdata at91sam9g10_config = {
 549         .clk_max_div = 7,
 550         .clk_offset = 4,
 551         .has_unre_flag = false,
 552         .has_dma_support = false,
 553 };
 554
 555 static const struct platform_device_id at91_twi_devtypes[] = {
 556         {
 557                 .name = "i2c-at91rm9200",
 558                 .driver_data = (unsigned long) &at91rm9200_config,
 559         }, {
 560                 .name = "i2c-at91sam9261",
 561                 .driver_data = (unsigned long) &at91sam9261_config,
 562         }, {
 563                 .name = "i2c-at91sam9260",
 564                 .driver_data = (unsigned long) &at91sam9260_config,
 565         }, {
 566                 .name = "i2c-at91sam9g20",
 567                 .driver_data = (unsigned long) &at91sam9g20_config,
 568         }, {
 569                 .name = "i2c-at91sam9g10",
 570                 .driver_data = (unsigned long) &at91sam9g10_config,
 571         }, {
 572                 /* sentinel */
 573         }
 574 };
 575
 576 #if defined(CONFIG_OF)
 577 static struct at91_twi_pdata at91sam9x5_config = {
 578         .clk_max_div = 7,
 579         .clk_offset = 4,
 580         .has_unre_flag = false,
 581         .has_dma_support = true,
 582 };
 583
 584 static const struct of_device_id atmel_twi_dt_ids[] = {
 585         {
 586                 .compatible = "atmel,at91rm9200-i2c",
 587                 .data = &at91rm9200_config,
 588         } , {
 589                 .compatible = "atmel,at91sam9260-i2c",
 590                 .data = &at91sam9260_config,
 591         } , {
 592                 .compatible = "atmel,at91sam9g20-i2c",
 593                 .data = &at91sam9g20_config,
 594         } , {
 595                 .compatible = "atmel,at91sam9g10-i2c",
 596                 .data = &at91sam9g10_config,
 597         }, {
 598                 .compatible = "atmel,at91sam9x5-i2c",
 599                 .data = &at91sam9x5_config,
 600         }, {
 601                 /* sentinel */
 602         }
 603 };
 604 MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
 605 #endif
 606
 607 static bool filter(struct dma_chan *chan, void *pdata)
 608 {
 609         struct at91_twi_pdata *sl_pdata = pdata;
 610         struct at_dma_slave *sl;
 611
 612         if (!sl_pdata)
 613                 return false;
 614
 615         sl = &sl_pdata->dma_slave;
 616         if (sl && (sl->dma_dev == chan->device->dev)) {
 617                 chan->private = sl;
 618                 return true;
 619         } else {
 620                 return false;
 621         }
 622 }
 623
 624 static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
 625 {
 626         int ret = 0;
 627         struct at91_twi_pdata *pdata = dev->pdata;
 628         struct dma_slave_config slave_config;
 629         struct at91_twi_dma *dma = &dev->dma;
 630         dma_cap_mask_t mask;
 631
 632         memset(&slave_config, 0, sizeof(slave_config));
 633         slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
 634         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 635         slave_config.src_maxburst = 1;
 636         slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR;
 637         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 638         slave_config.dst_maxburst = 1;
 639         slave_config.device_fc = false;
 640
 641         dma_cap_zero(mask);
 642         dma_cap_set(DMA_SLAVE, mask);
 643
 644         dma->chan_tx = dma_request_slave_channel_compat(mask, filter, pdata,
 645                                                         dev->dev, "tx");
 646         if (!dma->chan_tx) {
 647                 dev_err(dev->dev, "can't get a DMA channel for tx\n");
 648                 ret = -EBUSY;
 649                 goto error;
 650         }
 651
 652         dma->chan_rx = dma_request_slave_channel_compat(mask, filter, pdata,
 653                                                         dev->dev, "rx");
 654         if (!dma->chan_rx) {
 655                 dev_err(dev->dev, "can't get a DMA channel for rx\n");
 656                 ret = -EBUSY;
 657                 goto error;
 658         }
 659
 660         slave_config.direction = DMA_MEM_TO_DEV;
 661         if (dmaengine_slave_config(dma->chan_tx, &slave_config)) {
 662                 dev_err(dev->dev, "failed to configure tx channel\n");
 663                 ret = -EINVAL;
 664                 goto error;
 665         }
 666
 667         slave_config.direction = DMA_DEV_TO_MEM;
 668         if (dmaengine_slave_config(dma->chan_rx, &slave_config)) {
 669                 dev_err(dev->dev, "failed to configure rx channel\n");
 670                 ret = -EINVAL;
 671                 goto error;
 672         }
 673
 674         sg_init_table(&dma->sg, 1);
 675         dma->buf_mapped = false;
 676         dma->xfer_in_progress = false;
 677
 678         dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n",
 679                  dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
 680
 681         return ret;
 682
 683 error:
 684         dev_info(dev->dev, "can't use DMA\n");
 685         if (dma->chan_rx)
 686                 dma_release_channel(dma->chan_rx);
 687         if (dma->chan_tx)
 688                 dma_release_channel(dma->chan_tx);
 689         return ret;
 690 }
 691
 692 static struct at91_twi_pdata *at91_twi_get_driver_data(
 693                                         struct platform_device *pdev)
 694 {
 695         if (pdev->dev.of_node) {
 696                 const struct of_device_id *match;
 697                 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
 698                 if (!match)
 699                         return NULL;
 700                 return (struct at91_twi_pdata *)match->data;
 701         }
 702         return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
 703 }
 704
 705 static int at91_twi_probe(struct platform_device *pdev)
 706 {
 707         struct at91_twi_dev *dev;
 708         struct resource *mem;
 709         int rc;
 710         u32 phy_addr;
 711
 712         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
 713         if (!dev)
 714                 return -ENOMEM;
 715         init_completion(&dev->cmd_complete);
 716         dev->dev = &pdev->dev;
 717
 718         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 719         if (!mem)
 720                 return -ENODEV;
 721         phy_addr = mem->start;
 722
 723         dev->pdata = at91_twi_get_driver_data(pdev);
 724         if (!dev->pdata)
 725                 return -ENODEV;
 726
 727         dev->base = devm_ioremap_resource(&pdev->dev, mem);
 728         if (IS_ERR(dev->base))
 729                 return PTR_ERR(dev->base);
 730
 731         dev->irq = platform_get_irq(pdev, 0);
 732         if (dev->irq < 0)
 733                 return dev->irq;
 734
 735         rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
 736                          dev_name(dev->dev), dev);
 737         if (rc) {
 738                 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
 739                 return rc;
 740         }
 741
 742         platform_set_drvdata(pdev, dev);
 743
 744         dev->clk = devm_clk_get(dev->dev, NULL);
 745         if (IS_ERR(dev->clk)) {
 746                 dev_err(dev->dev, "no clock defined\n");
 747                 return -ENODEV;
 748         }
 749         clk_prepare_enable(dev->clk);
 750
 751         if (dev->pdata->has_dma_support) {
 752                 if (at91_twi_configure_dma(dev, phy_addr) == 0)
 753                         dev->use_dma = true;
 754         }
 755
 756         at91_calc_twi_clock(dev, TWI_CLK_HZ);
 757         at91_init_twi_bus(dev);
 758
 759         snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
 760         i2c_set_adapdata(&dev->adapter, dev);
 761         dev->adapter.owner = THIS_MODULE;
 762         dev->adapter.class = I2C_CLASS_HWMON;
 763         dev->adapter.algo = &at91_twi_algorithm;
 764         dev->adapter.dev.parent = dev->dev;
 765         dev->adapter.nr = pdev->id;
 766         dev->adapter.timeout = AT91_I2C_TIMEOUT;
 767         dev->adapter.dev.of_node = pdev->dev.of_node;
 768
 769         rc = i2c_add_numbered_adapter(&dev->adapter);
 770         if (rc) {
 771                 dev_err(dev->dev, "Adapter %s registration failed\n",
 772                         dev->adapter.name);
 773                 clk_disable_unprepare(dev->clk);
 774                 return rc;
 775         }
 776
 777         dev_info(dev->dev, "AT91 i2c bus driver.\n");
 778         return 0;
 779 }
 780
 781 static int at91_twi_remove(struct platform_device *pdev)
 782 {
 783         struct at91_twi_dev *dev = platform_get_drvdata(pdev);
 784
 785         i2c_del_adapter(&dev->adapter);
 786         clk_disable_unprepare(dev->clk);
 787
 788         return 0;
 789 }
 790
 791 #ifdef CONFIG_PM
 792
 793 static int at91_twi_runtime_suspend(struct device *dev)
 794 {
 795         struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
 796
 797         clk_disable(twi_dev->clk);
 798
 799         return 0;
 800 }
 801
 802 static int at91_twi_runtime_resume(struct device *dev)
 803 {
 804         struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
 805
 806         return clk_enable(twi_dev->clk);
 807 }
 808
 809 static const struct dev_pm_ops at91_twi_pm = {
 810         .runtime_suspend        = at91_twi_runtime_suspend,
 811         .runtime_resume         = at91_twi_runtime_resume,
 812 };
 813
 814 #define at91_twi_pm_ops (&at91_twi_pm)
 815 #else
 816 #define at91_twi_pm_ops NULL
 817 #endif
 818
 819 static struct platform_driver at91_twi_driver = {
 820         .probe          = at91_twi_probe,
 821         .remove         = at91_twi_remove,
 822         .id_table       = at91_twi_devtypes,
 823         .driver         = {
 824                 .name   = "at91_i2c",
 825                 .owner  = THIS_MODULE,
 826                 .of_match_table = of_match_ptr(atmel_twi_dt_ids),
 827                 .pm     = at91_twi_pm_ops,
 828         },
 829 };
 830
 831 static int __init at91_twi_init(void)
 832 {
 833         return platform_driver_register(&at91_twi_driver);
 834 }
 835
 836 static void __exit at91_twi_exit(void)
 837 {
 838         platform_driver_unregister(&at91_twi_driver);
 839 }
 840
 841 subsys_initcall(at91_twi_init);
 842 module_exit(at91_twi_exit);
 843
 844 MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
 845 MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
 846 MODULE_LICENSE("GPL");
 847 MODULE_ALIAS("platform:at91_i2c");