2 # I2C subsystem configuration
10 This is a stand-in for an option to enable I2C support. In fact this
11 simply enables building of the I2C directory for U-Boot. The actual
12 I2C feature is enabled by DM_I2C (for driver model) and
13 the #define CONFIG_SYS_I2C_LEGACY (for the legacy I2C stack).
15 So at present there is no need to ever disable this option.
19 Enable support for the I2C (Inter-Integrated Circuit) bus in U-Boot.
20 I2C works with a clock and data line which can be driven by a
21 one or more masters or slaves. It is a fairly complex bus but is
22 widely used as it only needs two lines for communication. Speeds of
23 400kbps are typical but up to 3.4Mbps is supported by some
24 hardware. Enable this option to build the drivers in drivers/i2c as
25 part of a U-Boot build.
30 bool "Enable Driver Model for I2C drivers"
33 Enable driver model for I2C. The I2C uclass interface: probe, read,
34 write and speed, is implemented with the bus drivers operations,
35 which provide methods for bus setting and data transfer. Each chip
36 device (bus child) info is kept as parent plat. The interface
37 is defined in include/i2c.h.
40 bool "Enable Driver Model for I2C drivers in SPL"
41 depends on SPL_DM && DM_I2C
44 Enable driver model for I2C. The I2C uclass interface: probe, read,
45 write and speed, is implemented with the bus drivers operations,
46 which provide methods for bus setting and data transfer. Each chip
47 device (bus child) info is kept as parent platdata. The interface
48 is defined in include/i2c.h.
51 bool "Enable Driver Model for I2C drivers in VPL"
52 depends on VPL_DM && DM_I2C
55 Enable driver model for I2C. The I2C uclass interface: probe, read,
56 write and speed, is implemented with the bus drivers operations,
57 which provide methods for bus setting and data transfer. Each chip
58 device (bus child) info is kept as parent platdata. The interface
59 is defined in include/i2c.h.
62 bool "Enable legacy I2C subsystem and drivers"
65 Enable the legacy I2C subsystem and drivers. While this is
66 deprecated in U-Boot itself, this can be useful in some situations
69 config SPL_SYS_I2C_LEGACY
70 bool "Enable legacy I2C subsystem and drivers in SPL"
71 depends on SUPPORT_SPL && !SPL_DM_I2C
73 Enable the legacy I2C subsystem and drivers in SPL. This is useful
74 in some size constrained situations.
76 config TPL_SYS_I2C_LEGACY
77 bool "Enable legacy I2C subsystem and drivers in TPL"
78 depends on SUPPORT_TPL && !SPL_DM_I2C
80 Enable the legacy I2C subsystem and drivers in TPL. This is useful
81 in some size constrained situations.
83 config SYS_I2C_EARLY_INIT
84 bool "Enable legacy I2C subsystem early in boot"
85 depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC
87 Add the function prototype for i2c_early_init_f which is called in
90 config I2C_CROS_EC_TUNNEL
91 tristate "Chrome OS EC tunnel I2C bus"
94 This provides an I2C bus that will tunnel i2c commands through to
95 the other side of the Chrome OS EC to the I2C bus connected there.
96 This will work whatever the interface used to talk to the EC (SPI,
97 I2C or LPC). Some Chromebooks use this when the hardware design
98 does not allow direct access to the main PMIC from the AP.
100 config I2C_CROS_EC_LDO
101 bool "Provide access to LDOs on the Chrome OS EC"
104 On many Chromebooks the main PMIC is inaccessible to the AP. This is
105 often dealt with by using an I2C pass-through interface provided by
106 the EC. On some unfortunate models (e.g. Spring) the pass-through
107 is not available, and an LDO message is available instead. This
108 option enables a driver which provides very basic access to those
109 regulators, via the EC. We implement this as an I2C bus which
110 emulates just the TPS65090 messages we know about. This is done to
111 avoid duplicating the logic in the TPS65090 regulator driver for
112 enabling/disabling an LDO.
114 config I2C_SET_DEFAULT_BUS_NUM
115 bool "Set default I2C bus number"
118 Set default number of I2C bus to be accessed. This option provides
119 behaviour similar to old (i.e. pre DM) I2C bus driver.
121 config I2C_DEFAULT_BUS_NUMBER
122 hex "I2C default bus number"
123 depends on I2C_SET_DEFAULT_BUS_NUM
126 Number of default I2C bus to use
129 bool "Enable Driver Model for software emulated I2C bus driver"
130 depends on DM_I2C && DM_GPIO
132 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
133 configuration is given by the device tree. Kernel-style device tree
134 bindings are supported.
135 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
137 config SPL_DM_I2C_GPIO
138 bool "Enable Driver Model for software emulated I2C bus driver in SPL"
139 depends on SPL_DM && DM_I2C_GPIO && SPL_DM_GPIO && SPL_GPIO
142 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
143 configuration is given by the device tree. Kernel-style device tree
144 bindings are supported.
145 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
148 bool "Atmel I2C driver"
149 depends on DM_I2C && ARCH_AT91
151 Add support for the Atmel I2C driver. A serious problem is that there
152 is no documented way to issue repeated START conditions for more than
153 two messages, as needed to support combined I2C messages. Use the
154 i2c-gpio driver unless your system can cope with this limitation.
155 Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
158 bool "Broadcom I2C driver"
162 Add support for Broadcom I2C driver.
163 Say yes here to to enable the Broadco I2C driver.
166 bool "Freescale I2C bus driver"
168 Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
171 if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
172 config SYS_FSL_I2C_OFFSET
173 hex "Offset from the IMMR of the address of the first I2C controller"
175 config SYS_FSL_HAS_I2C2_OFFSET
176 bool "Support a second I2C controller"
178 config SYS_FSL_I2C2_OFFSET
179 hex "Offset from the IMMR of the address of the second I2C controller"
180 depends on SYS_FSL_HAS_I2C2_OFFSET
182 config SYS_FSL_HAS_I2C3_OFFSET
183 bool "Support a third I2C controller"
185 config SYS_FSL_I2C3_OFFSET
186 hex "Offset from the IMMR of the address of the third I2C controller"
187 depends on SYS_FSL_HAS_I2C3_OFFSET
189 config SYS_FSL_HAS_I2C4_OFFSET
190 bool "Support a fourth I2C controller"
192 config SYS_FSL_I2C4_OFFSET
193 hex "Offset from the IMMR of the address of the fourth I2C controller"
194 depends on SYS_FSL_HAS_I2C4_OFFSET
197 config SYS_I2C_CADENCE
198 tristate "Cadence I2C Controller"
201 Say yes here to select Cadence I2C Host Controller. This controller is
202 e.g. used by Xilinx Zynq.
205 tristate "Cortina-Access I2C Controller"
206 depends on DM_I2C && CORTINA_PLATFORM
208 Add support for the Cortina Access I2C host controller.
209 Say yes here to select Cortina-Access I2C Host Controller.
211 config SYS_I2C_DAVINCI
212 bool "Davinci I2C Controller"
213 depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
215 Say yes here to add support for Davinci and Keystone I2C controller
218 bool "Designware I2C Controller"
220 Say yes here to select the Designware I2C Host Controller. This
221 controller is used in various SoCs, e.g. the ST SPEAr, Altera
222 SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
224 config SYS_I2C_ASPEED
225 bool "Aspeed I2C Controller"
226 depends on DM_I2C && ARCH_ASPEED
228 Say yes here to select Aspeed I2C Host Controller. The driver
229 supports AST2500 and AST2400 controllers, but is very limited.
230 Only single master mode is supported and only byte-by-byte
231 synchronous reads and writes are supported, no Pool Buffers or DMA.
234 bool "Intel I2C/SMBUS driver"
237 Add support for the Intel SMBUS driver. So far this driver is just
238 a stub which perhaps some basic init. There is no implementation of
239 the I2C API meaning that any I2C operations will immediately fail
242 config SYS_I2C_IMX_LPI2C
243 bool "NXP i.MX LPI2C driver"
245 Add support for the NXP i.MX LPI2C driver.
247 config SYS_I2C_LPC32XX
248 bool "LPC32XX I2C driver"
249 depends on ARCH_LPC32XX
251 Enable support for the LPC32xx I2C driver.
254 bool "Amlogic Meson I2C driver"
255 depends on DM_I2C && ARCH_MESON
257 Add support for the I2C controller available in Amlogic Meson
258 SoCs. The controller supports programmable bus speed including
259 standard (100kbits/s) and fast (400kbit/s) speed and allows the
260 software to define a flexible format of the bit streams. It has an
261 internal buffer holding up to 8 bytes for transfers and supports
262 both 7-bit and 10-bit addresses.
264 config SYS_I2C_MICROCHIP
265 bool "Microchip I2C driver"
267 Add support for the Microchip I2C driver. This is operating on
268 standard mode up to 100 kbits/s and fast mode up to 400 kbits/s.
271 bool "NXP MXC I2C driver"
273 Add support for the NXP I2C driver. This supports up to four bus
274 channels and operating on standard mode up to 100 kbits/s and fast
275 mode up to 400 kbits/s.
277 if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
278 config SYS_I2C_MXC_I2C1
281 Add support for NXP MXC I2C Controller 1.
282 Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
284 config SYS_I2C_MXC_I2C2
287 Add support for NXP MXC I2C Controller 2.
288 Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
290 config SYS_I2C_MXC_I2C3
293 Add support for NXP MXC I2C Controller 3.
294 Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
296 config SYS_I2C_MXC_I2C4
299 Add support for NXP MXC I2C Controller 4.
300 Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
302 config SYS_I2C_MXC_I2C5
305 Add support for NXP MXC I2C Controller 5.
306 Required for SoCs which have I2C MXC controller 5 eg LX2160A
308 config SYS_I2C_MXC_I2C6
311 Add support for NXP MXC I2C Controller 6.
312 Required for SoCs which have I2C MXC controller 6 eg LX2160A
314 config SYS_I2C_MXC_I2C7
317 Add support for NXP MXC I2C Controller 7.
318 Required for SoCs which have I2C MXC controller 7 eg LX2160A
320 config SYS_I2C_MXC_I2C8
323 Add support for NXP MXC I2C Controller 8.
324 Required for SoCs which have I2C MXC controller 8 eg LX2160A
328 config SYS_MXC_I2C1_SPEED
329 int "I2C Channel 1 speed"
330 default 40000000 if TARGET_LS2080A_EMU
333 MXC I2C Channel 1 speed
335 config SYS_MXC_I2C1_SLAVE
343 config SYS_MXC_I2C2_SPEED
344 int "I2C Channel 2 speed"
345 default 40000000 if TARGET_LS2080A_EMU
348 MXC I2C Channel 2 speed
350 config SYS_MXC_I2C2_SLAVE
358 config SYS_MXC_I2C3_SPEED
359 int "I2C Channel 3 speed"
362 MXC I2C Channel 3 speed
364 config SYS_MXC_I2C3_SLAVE
372 config SYS_MXC_I2C4_SPEED
373 int "I2C Channel 4 speed"
376 MXC I2C Channel 4 speed
378 config SYS_MXC_I2C4_SLAVE
386 config SYS_MXC_I2C5_SPEED
387 int "I2C Channel 5 speed"
390 MXC I2C Channel 5 speed
392 config SYS_MXC_I2C5_SLAVE
400 config SYS_MXC_I2C6_SPEED
401 int "I2C Channel 6 speed"
404 MXC I2C Channel 6 speed
406 config SYS_MXC_I2C6_SLAVE
414 config SYS_MXC_I2C7_SPEED
415 int "I2C Channel 7 speed"
418 MXC I2C Channel 7 speed
420 config SYS_MXC_I2C7_SLAVE
428 config SYS_MXC_I2C8_SPEED
429 int "I2C Channel 8 speed"
432 MXC I2C Channel 8 speed
434 config SYS_MXC_I2C8_SLAVE
441 config SYS_I2C_NEXELL
442 bool "Nexell I2C driver"
445 Add support for the Nexell I2C driver. This is used with various
446 Nexell parts such as S5Pxx18 series SoCs. All chips
447 have several I2C ports and all are provided, controlled by the
450 config SYS_I2C_OCORES
451 bool "ocores I2C driver"
454 Add support for ocores I2C controller. For details see
455 https://opencores.org/projects/i2c
457 config SYS_I2C_OMAP24XX
458 bool "TI OMAP2+ I2C driver"
459 depends on ARCH_OMAP2PLUS || ARCH_K3
461 Add support for the OMAP2+ I2C driver.
463 config SYS_I2C_RCAR_I2C
464 bool "Renesas RCar I2C driver"
465 depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
467 Support for Renesas RCar I2C controller.
469 config SYS_I2C_RCAR_IIC
470 bool "Renesas RCar Gen3 IIC driver"
471 depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
473 Support for Renesas RCar Gen3 IIC controller.
475 config SYS_I2C_ROCKCHIP
476 bool "Rockchip I2C driver"
479 Add support for the Rockchip I2C driver. This is used with various
480 Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
481 have several I2C ports and all are provided, controlled by the
484 config SYS_I2C_SANDBOX
485 bool "Sandbox I2C driver"
486 depends on SANDBOX && DM_I2C
488 Enable I2C support for sandbox. This is an emulation of a real I2C
489 bus. Devices can be attached to the bus using the device tree
490 which specifies the driver to use. See sandbox.dts as an example.
493 bool "Legacy SuperH I2C interface"
494 depends on ARCH_RMOBILE && SYS_I2C_LEGACY
496 Enable the legacy SuperH I2C interface.
499 config SYS_I2C_SH_NUM_CONTROLLERS
503 config SYS_I2C_SH_BASE0
507 config SYS_I2C_SH_BASE1
511 config SYS_I2C_SH_BASE2
515 config SYS_I2C_SH_BASE3
519 config SYS_I2C_SH_BASE4
527 config SH_I2C_DATA_HIGH
531 config SH_I2C_DATA_LOW
541 bool "Legacy software I2C interface"
543 Enable the legacy software defined I2C interface
545 config SYS_I2C_SOFT_SPEED
546 int "Software I2C bus speed"
547 depends on SYS_I2C_SOFT
550 Speed of the software I2C bus
552 config SYS_I2C_SOFT_SLAVE
553 hex "Software I2C slave address"
554 depends on SYS_I2C_SOFT
557 Slave address of the software I2C bus
559 config SYS_I2C_OCTEON
560 bool "Octeon II/III/TX/TX2 I2C driver"
561 depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
564 Add support for the Marvell Octeon I2C driver. This is used with
565 various Octeon parts such as Octeon II/III and OcteonTX/TX2. All
566 chips have several I2C ports and all are provided, controlled by
569 config SYS_I2C_S3C24X0
570 bool "Samsung I2C driver"
571 depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C
573 Support for Samsung I2C controller as Samsung SoCs.
575 config SYS_I2C_STM32F7
576 bool "STMicroelectronics STM32F7 I2C support"
577 depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
579 Enable this option to add support for STM32 I2C controller
580 introduced with STM32F7/H7 SoCs. This I2C controller supports :
581 _ Slave and master modes
582 _ Multimaster capability
583 _ Standard-mode (up to 100 kHz)
584 _ Fast-mode (up to 400 kHz)
585 _ Fast-mode Plus (up to 1 MHz)
586 _ 7-bit and 10-bit addressing mode
587 _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
588 _ All 7-bit addresses acknowledge mode
590 _ Programmable setup and hold times
591 _ Easy to use event management
592 _ Optional clock stretching
595 config SYS_I2C_SUN6I_P2WI
596 bool "Allwinner sun6i P2WI controller"
597 depends on ARCH_SUNXI
599 Support for the P2WI (Push/Pull 2 Wire Interface) controller embedded
600 in the Allwinner A31 and A31s SOCs. This interface is used to connect
601 to specific devices like the X-Powers AXP221 PMIC.
603 config SYS_I2C_SUN8I_RSB
604 bool "Allwinner sun8i Reduced Serial Bus controller"
605 depends on ARCH_SUNXI
607 Support for Allwinner's Reduced Serial Bus (RSB) controller. This
608 controller is responsible for communicating with various RSB based
609 devices, such as X-Powers AXPxxx PMICs and AC100/AC200 CODEC ICs.
611 config SYS_I2C_SYNQUACER
612 bool "Socionext SynQuacer I2C controller"
613 depends on ARCH_SYNQUACER && DM_I2C
615 Support for Socionext Synquacer I2C controller. This I2C controller
616 will be used for RTC and LS-connector on DeveloperBox.
619 bool "NVIDIA Tegra internal I2C controller"
620 depends on ARCH_TEGRA
622 Support for NVIDIA I2C controller available in Tegra SoCs.
624 config SYS_I2C_UNIPHIER
625 bool "UniPhier I2C driver"
626 depends on ARCH_UNIPHIER && DM_I2C
629 Support for UniPhier I2C controller driver. This I2C controller
630 is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
632 config SYS_I2C_UNIPHIER_F
633 bool "UniPhier FIFO-builtin I2C driver"
634 depends on ARCH_UNIPHIER && DM_I2C
637 Support for UniPhier FIFO-builtin I2C controller driver.
638 This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
640 config SYS_I2C_VERSATILE
641 bool "Arm Ltd Versatile I2C bus driver"
642 depends on DM_I2C && TARGET_VEXPRESS64_JUNO
644 Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
645 controller is present in the development boards manufactured by Arm Ltd.
648 bool "Marvell PXA (Armada 3720) I2C driver"
650 Support for PXA based I2C controller used on Armada 3720 SoC.
651 In Linux, this driver is called i2c-pxa.
653 config SYS_I2C_MVTWSI
654 bool "Marvell I2C driver"
656 Support for Marvell I2C controllers as used on the orion5x and
657 kirkwood SoC families.
659 config TEGRA186_BPMP_I2C
660 bool "Enable Tegra186 BPMP-based I2C driver"
661 depends on TEGRA186_BPMP
663 Support for Tegra I2C controllers managed by the BPMP (Boot and
664 Power Management Processor). On Tegra186, some I2C controllers are
665 directly controlled by the main CPU, whereas others are controlled
666 by the BPMP, and can only be accessed by the main CPU via IPC
667 requests to the BPMP. This driver covers the latter case.
670 hex "I2C Slave address channel (all buses)"
671 depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
674 I2C Slave address channel 0 for all buses in the legacy drivers.
675 Many boards/controllers/drivers don't support an I2C slave
676 interface so provide a default slave address for them for use in
677 common code. A real value for CONFIG_SYS_I2C_SLAVE should be
678 defined for any board which does support a slave interface and
679 this default used otherwise.
682 int "I2C Slave channel 0 speed (all buses)"
683 depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
686 I2C Slave speed channel 0 for all buses in the legacy drivers.
688 config SYS_I2C_BUS_MAX
690 depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA
692 default 3 if OMAP34XX || AM33XX || AM43XX
693 default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
694 default 5 if OMAP54XX
696 Define the maximum number of available I2C buses.
698 config SYS_I2C_XILINX_XIIC
699 bool "Xilinx AXI I2C driver"
702 Support for Xilinx AXI I2C controller.
705 bool "gdsys IHS I2C driver"
708 Support for gdsys IHS I2C driver on FPGA bus.
710 source "drivers/i2c/muxes/Kconfig"