1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 MaxLinear, Inc.
5 * This driver is a hardware monitoring driver for PVT controller
6 * (MR75203) which is used to configure & control Moortec embedded
7 * analog IP to enable multiple embedded temperature sensor(TS),
8 * voltage monitor(VM) & process detector(PD) modules.
10 #include <linux/bits.h>
11 #include <linux/clk.h>
12 #include <linux/hwmon.h>
13 #include <linux/module.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/mutex.h>
16 #include <linux/platform_device.h>
17 #include <linux/property.h>
18 #include <linux/regmap.h>
19 #include <linux/reset.h>
20 #include <linux/units.h>
22 /* PVT Common register */
23 #define PVT_IP_CONFIG 0x04
24 #define TS_NUM_MSK GENMASK(4, 0)
26 #define PD_NUM_MSK GENMASK(12, 8)
28 #define VM_NUM_MSK GENMASK(20, 16)
30 #define CH_NUM_MSK GENMASK(31, 24)
33 /* Macro Common Register */
34 #define CLK_SYNTH 0x00
35 #define CLK_SYNTH_LO_SFT 0
36 #define CLK_SYNTH_HI_SFT 8
37 #define CLK_SYNTH_HOLD_SFT 16
38 #define CLK_SYNTH_EN BIT(24)
39 #define CLK_SYS_CYCLES_MAX 514
40 #define CLK_SYS_CYCLES_MIN 2
42 #define SDIF_DISABLE 0x04
44 #define SDIF_STAT 0x08
45 #define SDIF_BUSY BIT(0)
46 #define SDIF_LOCK BIT(1)
49 #define SDIF_PROG BIT(31)
50 #define SDIF_WRN_W BIT(27)
51 #define SDIF_WRN_R 0x00
52 #define SDIF_ADDR_SFT 24
54 #define SDIF_HALT 0x10
55 #define SDIF_CTRL 0x14
56 #define SDIF_SMPL_CTRL 0x20
58 /* TS & PD Individual Macro Register */
59 #define COM_REG_SIZE 0x40
61 #define SDIF_DONE(n) (COM_REG_SIZE + 0x14 + 0x40 * (n))
62 #define SDIF_SMPL_DONE BIT(0)
64 #define SDIF_DATA(n) (COM_REG_SIZE + 0x18 + 0x40 * (n))
65 #define SAMPLE_DATA_MSK GENMASK(15, 0)
67 #define HILO_RESET(n) (COM_REG_SIZE + 0x2c + 0x40 * (n))
69 /* VM Individual Macro Register */
70 #define VM_COM_REG_SIZE 0x200
71 #define VM_SDIF_DONE(n) (VM_COM_REG_SIZE + 0x34 + 0x200 * (n))
72 #define VM_SDIF_DATA(n) (VM_COM_REG_SIZE + 0x40 + 0x200 * (n))
74 /* SDA Slave Register */
76 #define IP_RST_REL BIT(1)
77 #define IP_RUN_CONT BIT(3)
78 #define IP_AUTO BIT(8)
79 #define IP_VM_MODE BIT(10)
82 #define CFG0_MODE_2 BIT(0)
83 #define CFG0_PARALLEL_OUT 0
85 #define CFG1_VOL_MEAS_MODE 0
86 #define CFG1_PARALLEL_OUT 0
92 #define VM_CH_INIT BIT(20)
93 #define VM_CH_REQ BIT(21)
96 #define POWER_DELAY_CYCLE_256 0x100
97 #define POWER_DELAY_CYCLE_64 0x40
99 #define PVT_POLL_DELAY_US 20
100 #define PVT_POLL_TIMEOUT_US 20000
101 #define PVT_H_CONST 100000
102 #define PVT_CAL5_CONST 2047
103 #define PVT_G_CONST 40000
104 #define PVT_CONV_BITS 10
105 #define PVT_N_CONST 90
106 #define PVT_R_CONST 245805
109 struct regmap *c_map;
110 struct regmap *t_map;
111 struct regmap *p_map;
112 struct regmap *v_map;
114 struct reset_control *rst;
122 static umode_t pvt_is_visible(const void *data, enum hwmon_sensor_types type,
123 u32 attr, int channel)
127 if (attr == hwmon_temp_input)
131 if (attr == hwmon_in_input)
140 static int pvt_read_temp(struct device *dev, u32 attr, int channel, long *val)
142 struct pvt_device *pvt = dev_get_drvdata(dev);
143 struct regmap *t_map = pvt->t_map;
149 case hwmon_temp_input:
150 ret = regmap_read_poll_timeout(t_map, SDIF_DONE(channel),
151 stat, stat & SDIF_SMPL_DONE,
153 PVT_POLL_TIMEOUT_US);
157 ret = regmap_read(t_map, SDIF_DATA(channel), &nbs);
161 nbs &= SAMPLE_DATA_MSK;
164 * Convert the register value to
165 * degrees centigrade temperature
167 tmp = nbs * PVT_H_CONST;
168 do_div(tmp, PVT_CAL5_CONST);
169 *val = tmp - PVT_G_CONST - pvt->ip_freq;
177 static int pvt_read_in(struct device *dev, u32 attr, int channel, long *val)
179 struct pvt_device *pvt = dev_get_drvdata(dev);
180 struct regmap *v_map = pvt->v_map;
185 if (channel >= pvt->v_num)
188 vm_idx = pvt->vm_idx[channel];
192 ret = regmap_read_poll_timeout(v_map, VM_SDIF_DONE(vm_idx),
193 stat, stat & SDIF_SMPL_DONE,
195 PVT_POLL_TIMEOUT_US);
199 ret = regmap_read(v_map, VM_SDIF_DATA(vm_idx), &n);
203 n &= SAMPLE_DATA_MSK;
204 /* Convert the N bitstream count into voltage */
205 *val = (PVT_N_CONST * n - PVT_R_CONST) >> PVT_CONV_BITS;
213 static int pvt_read(struct device *dev, enum hwmon_sensor_types type,
214 u32 attr, int channel, long *val)
218 return pvt_read_temp(dev, attr, channel, val);
220 return pvt_read_in(dev, attr, channel, val);
226 static struct hwmon_channel_info pvt_temp = {
230 static struct hwmon_channel_info pvt_in = {
234 static const struct hwmon_ops pvt_hwmon_ops = {
235 .is_visible = pvt_is_visible,
239 static struct hwmon_chip_info pvt_chip_info = {
240 .ops = &pvt_hwmon_ops,
243 static int pvt_init(struct pvt_device *pvt)
245 u16 sys_freq, key, middle, low = 4, high = 8;
246 struct regmap *t_map = pvt->t_map;
247 struct regmap *p_map = pvt->p_map;
248 struct regmap *v_map = pvt->v_map;
249 u32 t_num = pvt->t_num;
250 u32 p_num = pvt->p_num;
251 u32 v_num = pvt->v_num;
255 sys_freq = clk_get_rate(pvt->clk) / HZ_PER_MHZ;
256 while (high >= low) {
257 middle = (low + high + 1) / 2;
258 key = DIV_ROUND_CLOSEST(sys_freq, middle);
259 if (key > CLK_SYS_CYCLES_MAX) {
262 } else if (key < CLK_SYS_CYCLES_MIN) {
271 * The system supports 'clk_sys' to 'clk_ip' frequency ratios
274 key = clamp_val(key, CLK_SYS_CYCLES_MIN, CLK_SYS_CYCLES_MAX) - 2;
276 clk_synth = ((key + 1) >> 1) << CLK_SYNTH_LO_SFT |
277 (key >> 1) << CLK_SYNTH_HI_SFT |
278 (key >> 1) << CLK_SYNTH_HOLD_SFT | CLK_SYNTH_EN;
280 pvt->ip_freq = sys_freq * 100 / (key + 2);
283 ret = regmap_write(t_map, SDIF_SMPL_CTRL, 0x0);
287 ret = regmap_write(t_map, SDIF_HALT, 0x0);
291 ret = regmap_write(t_map, CLK_SYNTH, clk_synth);
295 ret = regmap_write(t_map, SDIF_DISABLE, 0x0);
299 ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
300 val, !(val & SDIF_BUSY),
302 PVT_POLL_TIMEOUT_US);
306 val = CFG0_MODE_2 | CFG0_PARALLEL_OUT | CFG0_12_BIT |
307 IP_CFG << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG;
308 ret = regmap_write(t_map, SDIF_W, val);
312 ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
313 val, !(val & SDIF_BUSY),
315 PVT_POLL_TIMEOUT_US);
319 val = POWER_DELAY_CYCLE_256 | IP_TMR << SDIF_ADDR_SFT |
320 SDIF_WRN_W | SDIF_PROG;
321 ret = regmap_write(t_map, SDIF_W, val);
325 ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
326 val, !(val & SDIF_BUSY),
328 PVT_POLL_TIMEOUT_US);
332 val = IP_RST_REL | IP_RUN_CONT | IP_AUTO |
333 IP_CTRL << SDIF_ADDR_SFT |
334 SDIF_WRN_W | SDIF_PROG;
335 ret = regmap_write(t_map, SDIF_W, val);
341 ret = regmap_write(p_map, SDIF_HALT, 0x0);
345 ret = regmap_write(p_map, SDIF_DISABLE, BIT(p_num) - 1);
349 ret = regmap_write(p_map, CLK_SYNTH, clk_synth);
355 ret = regmap_write(v_map, SDIF_SMPL_CTRL, 0x0);
359 ret = regmap_write(v_map, SDIF_HALT, 0x0);
363 ret = regmap_write(v_map, CLK_SYNTH, clk_synth);
367 ret = regmap_write(v_map, SDIF_DISABLE, 0x0);
371 ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
372 val, !(val & SDIF_BUSY),
374 PVT_POLL_TIMEOUT_US);
378 val = CFG1_VOL_MEAS_MODE | CFG1_PARALLEL_OUT |
379 CFG1_14_BIT | IP_CFG << SDIF_ADDR_SFT |
380 SDIF_WRN_W | SDIF_PROG;
381 ret = regmap_write(v_map, SDIF_W, val);
385 ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
386 val, !(val & SDIF_BUSY),
388 PVT_POLL_TIMEOUT_US);
392 val = POWER_DELAY_CYCLE_64 | IP_TMR << SDIF_ADDR_SFT |
393 SDIF_WRN_W | SDIF_PROG;
394 ret = regmap_write(v_map, SDIF_W, val);
398 ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
399 val, !(val & SDIF_BUSY),
401 PVT_POLL_TIMEOUT_US);
405 val = IP_RST_REL | IP_RUN_CONT | IP_AUTO | IP_VM_MODE |
406 IP_CTRL << SDIF_ADDR_SFT |
407 SDIF_WRN_W | SDIF_PROG;
408 ret = regmap_write(v_map, SDIF_W, val);
416 static struct regmap_config pvt_regmap_config = {
422 static int pvt_get_regmap(struct platform_device *pdev, char *reg_name,
423 struct pvt_device *pvt)
425 struct device *dev = &pdev->dev;
426 struct regmap **reg_map;
427 void __iomem *io_base;
429 if (!strcmp(reg_name, "common"))
430 reg_map = &pvt->c_map;
431 else if (!strcmp(reg_name, "ts"))
432 reg_map = &pvt->t_map;
433 else if (!strcmp(reg_name, "pd"))
434 reg_map = &pvt->p_map;
435 else if (!strcmp(reg_name, "vm"))
436 reg_map = &pvt->v_map;
440 io_base = devm_platform_ioremap_resource_byname(pdev, reg_name);
442 return PTR_ERR(io_base);
444 pvt_regmap_config.name = reg_name;
445 *reg_map = devm_regmap_init_mmio(dev, io_base, &pvt_regmap_config);
446 if (IS_ERR(*reg_map)) {
447 dev_err(dev, "failed to init register map\n");
448 return PTR_ERR(*reg_map);
454 static void pvt_clk_disable(void *data)
456 struct pvt_device *pvt = data;
458 clk_disable_unprepare(pvt->clk);
461 static int pvt_clk_enable(struct device *dev, struct pvt_device *pvt)
465 ret = clk_prepare_enable(pvt->clk);
469 return devm_add_action_or_reset(dev, pvt_clk_disable, pvt);
472 static void pvt_reset_control_assert(void *data)
474 struct pvt_device *pvt = data;
476 reset_control_assert(pvt->rst);
479 static int pvt_reset_control_deassert(struct device *dev, struct pvt_device *pvt)
483 ret = reset_control_deassert(pvt->rst);
487 return devm_add_action_or_reset(dev, pvt_reset_control_assert, pvt);
490 static int mr75203_probe(struct platform_device *pdev)
492 const struct hwmon_channel_info **pvt_info;
493 u32 ts_num, vm_num, pd_num, val, index, i;
494 struct device *dev = &pdev->dev;
495 u32 *temp_config, *in_config;
496 struct device *hwmon_dev;
497 struct pvt_device *pvt;
500 pvt = devm_kzalloc(dev, sizeof(*pvt), GFP_KERNEL);
504 ret = pvt_get_regmap(pdev, "common", pvt);
508 pvt->clk = devm_clk_get(dev, NULL);
509 if (IS_ERR(pvt->clk))
510 return dev_err_probe(dev, PTR_ERR(pvt->clk), "failed to get clock\n");
512 ret = pvt_clk_enable(dev, pvt);
514 dev_err(dev, "failed to enable clock\n");
518 pvt->rst = devm_reset_control_get_exclusive(dev, NULL);
519 if (IS_ERR(pvt->rst))
520 return dev_err_probe(dev, PTR_ERR(pvt->rst),
521 "failed to get reset control\n");
523 ret = pvt_reset_control_deassert(dev, pvt);
525 return dev_err_probe(dev, ret, "cannot deassert reset control\n");
527 ret = regmap_read(pvt->c_map, PVT_IP_CONFIG, &val);
531 ts_num = (val & TS_NUM_MSK) >> TS_NUM_SFT;
532 pd_num = (val & PD_NUM_MSK) >> PD_NUM_SFT;
533 vm_num = (val & VM_NUM_MSK) >> VM_NUM_SFT;
545 pvt_info = devm_kcalloc(dev, val + 2, sizeof(*pvt_info), GFP_KERNEL);
548 pvt_info[0] = HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ);
552 ret = pvt_get_regmap(pdev, "ts", pvt);
556 temp_config = devm_kcalloc(dev, ts_num + 1,
557 sizeof(*temp_config), GFP_KERNEL);
561 memset32(temp_config, HWMON_T_INPUT, ts_num);
562 pvt_temp.config = temp_config;
563 pvt_info[index++] = &pvt_temp;
567 ret = pvt_get_regmap(pdev, "pd", pvt);
575 ret = pvt_get_regmap(pdev, "vm", pvt);
579 pvt->vm_idx = devm_kcalloc(dev, vm_num, sizeof(*pvt->vm_idx),
584 ret = device_property_read_u8_array(dev, "intel,vm-map",
585 pvt->vm_idx, vm_num);
589 for (i = 0; i < vm_num; i++)
590 if (pvt->vm_idx[i] >= vm_num ||
591 pvt->vm_idx[i] == 0xff) {
598 * Incase intel,vm-map property is not defined, we assume
599 * incremental channel numbers.
601 for (i = num; i < vm_num; i++)
604 in_config = devm_kcalloc(dev, num + 1,
605 sizeof(*in_config), GFP_KERNEL);
609 memset32(in_config, HWMON_I_INPUT, num);
611 pvt_in.config = in_config;
613 pvt_info[index++] = &pvt_in;
618 dev_err(dev, "failed to init pvt: %d\n", ret);
622 pvt_chip_info.info = pvt_info;
623 hwmon_dev = devm_hwmon_device_register_with_info(dev, "pvt",
628 return PTR_ERR_OR_ZERO(hwmon_dev);
631 static const struct of_device_id moortec_pvt_of_match[] = {
632 { .compatible = "moortec,mr75203" },
635 MODULE_DEVICE_TABLE(of, moortec_pvt_of_match);
637 static struct platform_driver moortec_pvt_driver = {
639 .name = "moortec-pvt",
640 .of_match_table = moortec_pvt_of_match,
642 .probe = mr75203_probe,
644 module_platform_driver(moortec_pvt_driver);
646 MODULE_LICENSE("GPL v2");