1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/bitfield.h>
4 #include <linux/bits.h>
6 #include <linux/hwmon.h>
7 #include <linux/hwmon-sysfs.h>
9 #include <linux/regmap.h>
10 #include <linux/util_macros.h>
13 #define CR1_HYST BIT(5)
14 #define CR1_DRV GENMASK(4, 3)
15 #define CR1_TEMP_SRC GENMASK(1, 0)
17 #define CR2_STBY BIT(7)
18 #define CR2_ALERTS BIT(6)
19 #define CR2_DFC BIT(0)
23 #define REG_STATUS 0x5A
24 #define STATUS_ALARM_CRIT(ch) BIT(2 + 2 * (ch))
25 #define STATUS_ALARM_MAX(ch) BIT(3 + 2 * (ch))
26 #define STATUS_RDFA BIT(6)
28 #define REG_TACH(ch) (0x52 + (ch) * 2)
29 #define REG_TEMP_INPUT(ch) (0x56 + (ch) * 2)
30 #define REG_TEMP_MAX(ch) (0x06 + (ch) * 2)
31 #define REG_TEMP_CRIT(ch) (0x0A + (ch) * 2)
33 #define TEMP11_FROM_REG(reg) ((reg) / 32 * 125)
34 #define TEMP11_TO_REG(val) (DIV_ROUND_CLOSEST(clamp_val((val), -128000, \
39 #define REG_LUT(index) (0x20 + (index))
41 struct max31760_state {
42 struct regmap *regmap;
44 struct lut_attribute {
46 struct sensor_device_attribute sda;
49 struct attribute *attrs[LUT_SIZE + 2];
50 struct attribute_group group;
51 const struct attribute_group *groups[2];
54 static bool max31760_volatile_reg(struct device *dev, unsigned int reg)
59 static const struct regmap_config regmap_config = {
63 .cache_type = REGCACHE_RBTREE,
64 .volatile_reg = max31760_volatile_reg,
67 static const int max31760_pwm_freq[] = {33, 150, 1500, 25000};
69 static int tach_to_rpm(u16 tach)
74 return 60 * 100000 / tach / 2;
77 static int max31760_read(struct device *dev, enum hwmon_sensor_types type,
78 u32 attr, int channel, long *val)
80 struct max31760_state *state = dev_get_drvdata(dev);
82 unsigned int reg_temp;
90 case hwmon_temp_fault:
91 ret = regmap_read(state->regmap, REG_STATUS, ®val);
95 *val = FIELD_GET(STATUS_RDFA, regval);
98 case hwmon_temp_max_alarm:
99 ret = regmap_read(state->regmap, REG_STATUS, ®val);
104 *val = FIELD_GET(STATUS_ALARM_MAX(1), regval);
106 *val = FIELD_GET(STATUS_ALARM_MAX(0), regval);
109 case hwmon_temp_crit_alarm:
110 ret = regmap_read(state->regmap, REG_STATUS, ®val);
115 *val = FIELD_GET(STATUS_ALARM_CRIT(1), regval);
117 *val = FIELD_GET(STATUS_ALARM_CRIT(0), regval);
120 case hwmon_temp_input:
121 reg_temp = REG_TEMP_INPUT(channel);
124 reg_temp = REG_TEMP_MAX(channel);
126 case hwmon_temp_crit:
127 reg_temp = REG_TEMP_CRIT(channel);
133 ret = regmap_bulk_read(state->regmap, reg_temp, reg, 2);
137 temp = (reg[0] << 8) | reg[1];
139 *val = TEMP11_FROM_REG(temp);
144 case hwmon_fan_input:
145 ret = regmap_bulk_read(state->regmap, REG_TACH(channel), reg, 2);
149 *val = tach_to_rpm(reg[0] * 256 + reg[1]);
152 case hwmon_fan_fault:
153 ret = regmap_read(state->regmap, REG_STATUS, ®val);
158 *val = FIELD_GET(BIT(1), regval);
160 *val = FIELD_GET(BIT(0), regval);
163 case hwmon_fan_enable:
164 ret = regmap_read(state->regmap, REG_CR3, ®val);
169 *val = FIELD_GET(BIT(1), regval);
171 *val = FIELD_GET(BIT(0), regval);
179 case hwmon_pwm_input:
180 ret = regmap_read(state->regmap, REG_PWMV, ®val);
188 ret = regmap_read(state->regmap, REG_CR1, ®val);
192 regval = FIELD_GET(CR1_DRV, regval);
193 if (regval >= ARRAY_SIZE(max31760_pwm_freq))
196 *val = max31760_pwm_freq[regval];
199 case hwmon_pwm_enable:
200 ret = regmap_read(state->regmap, REG_CR2, ®val);
204 *val = 2 - FIELD_GET(CR2_DFC, regval);
207 case hwmon_pwm_auto_channels_temp:
208 ret = regmap_read(state->regmap, REG_CR1, ®val);
212 switch (FIELD_GET(CR1_TEMP_SRC, regval)) {
236 static int max31760_write(struct device *dev, enum hwmon_sensor_types type,
237 u32 attr, int channel, long val)
239 struct max31760_state *state = dev_get_drvdata(dev);
240 unsigned int pwm_index;
241 unsigned int reg_temp;
249 reg_temp = REG_TEMP_MAX(channel);
251 case hwmon_temp_crit:
252 reg_temp = REG_TEMP_CRIT(channel);
258 temp = TEMP11_TO_REG(val);
259 reg_val[0] = temp >> 8;
260 reg_val[1] = temp & 0xFF;
262 return regmap_bulk_write(state->regmap, reg_temp, reg_val, 2);
265 case hwmon_fan_enable:
267 return regmap_clear_bits(state->regmap, REG_CR3, BIT(channel));
270 return regmap_set_bits(state->regmap, REG_CR3, BIT(channel));
278 case hwmon_pwm_input:
279 if (val < 0 || val > 255)
282 return regmap_write(state->regmap, REG_PWMR, val);
283 case hwmon_pwm_enable:
285 return regmap_set_bits(state->regmap, REG_CR2, CR2_DFC);
288 return regmap_clear_bits(state->regmap, REG_CR2, CR2_DFC);
292 pwm_index = find_closest(val, max31760_pwm_freq,
293 ARRAY_SIZE(max31760_pwm_freq));
295 return regmap_update_bits(state->regmap,
297 FIELD_PREP(CR1_DRV, pwm_index));
298 case hwmon_pwm_auto_channels_temp:
312 return regmap_update_bits(state->regmap, REG_CR1, CR1_TEMP_SRC, val);
321 static const struct hwmon_channel_info * const max31760_info[] = {
322 HWMON_CHANNEL_INFO(chip,
323 HWMON_C_REGISTER_TZ),
324 HWMON_CHANNEL_INFO(fan,
325 HWMON_F_INPUT | HWMON_F_FAULT | HWMON_F_ENABLE,
326 HWMON_F_INPUT | HWMON_F_FAULT | HWMON_F_ENABLE),
327 HWMON_CHANNEL_INFO(temp,
328 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | HWMON_T_FAULT |
329 HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
330 HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT |
331 HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_LABEL),
332 HWMON_CHANNEL_INFO(pwm,
333 HWMON_PWM_ENABLE | HWMON_PWM_FREQ | HWMON_PWM_INPUT |
334 HWMON_PWM_AUTO_CHANNELS_TEMP),
338 static umode_t max31760_is_visible(const void *data,
339 enum hwmon_sensor_types type,
340 u32 attr, int channel)
345 case hwmon_temp_input:
346 case hwmon_temp_max_alarm:
347 case hwmon_temp_crit_alarm:
348 case hwmon_temp_fault:
349 case hwmon_temp_label:
352 case hwmon_temp_crit:
359 case hwmon_fan_input:
360 case hwmon_fan_fault:
362 case hwmon_fan_enable:
369 case hwmon_pwm_enable:
370 case hwmon_pwm_input:
372 case hwmon_pwm_auto_channels_temp:
382 static int max31760_read_string(struct device *dev,
383 enum hwmon_sensor_types type,
384 u32 attr, int channel, const char **str)
388 if (attr != hwmon_temp_label)
391 *str = channel ? "local" : "remote";
399 static const struct hwmon_ops max31760_hwmon_ops = {
400 .is_visible = max31760_is_visible,
401 .read = max31760_read,
402 .write = max31760_write,
403 .read_string = max31760_read_string
406 static const struct hwmon_chip_info max31760_chip_info = {
407 .ops = &max31760_hwmon_ops,
408 .info = max31760_info,
411 static ssize_t lut_show(struct device *dev,
412 struct device_attribute *devattr, char *buf)
414 struct sensor_device_attribute *sda = to_sensor_dev_attr(devattr);
415 struct max31760_state *state = dev_get_drvdata(dev);
419 ret = regmap_read(state->regmap, REG_LUT(sda->index), ®val);
423 return sysfs_emit(buf, "%d\n", regval);
426 static ssize_t lut_store(struct device *dev,
427 struct device_attribute *devattr,
428 const char *buf, size_t count)
430 struct sensor_device_attribute *sda = to_sensor_dev_attr(devattr);
431 struct max31760_state *state = dev_get_drvdata(dev);
435 ret = kstrtou8(buf, 10, &pwm);
439 ret = regmap_write(state->regmap, REG_LUT(sda->index), pwm);
446 static ssize_t pwm1_auto_point_temp_hyst_show(struct device *dev,
447 struct device_attribute *attr,
450 struct max31760_state *state = dev_get_drvdata(dev);
454 ret = regmap_read(state->regmap, REG_CR1, ®val);
458 return sysfs_emit(buf, "%d\n", (1 + (int)FIELD_GET(CR1_HYST, regval)) * 2000);
461 static ssize_t pwm1_auto_point_temp_hyst_store(struct device *dev,
462 struct device_attribute *attr,
466 struct max31760_state *state = dev_get_drvdata(dev);
470 ret = kstrtou32(buf, 10, &hyst);
475 ret = regmap_clear_bits(state->regmap, REG_CR1, CR1_HYST);
477 ret = regmap_set_bits(state->regmap, REG_CR1, CR1_HYST);
485 static DEVICE_ATTR_RW(pwm1_auto_point_temp_hyst);
487 static void max31760_create_lut_nodes(struct max31760_state *state)
490 struct sensor_device_attribute *sda;
491 struct lut_attribute *lut;
493 for (i = 0; i < LUT_SIZE; ++i) {
494 lut = &state->lut[i];
497 snprintf(lut->name, sizeof(lut->name),
498 "pwm1_auto_point%d_pwm", i + 1);
500 sda->dev_attr.attr.mode = 0644;
502 sda->dev_attr.show = lut_show;
503 sda->dev_attr.store = lut_store;
504 sda->dev_attr.attr.name = lut->name;
506 sysfs_attr_init(&sda->dev_attr.attr);
508 state->attrs[i] = &sda->dev_attr.attr;
511 state->attrs[i] = &dev_attr_pwm1_auto_point_temp_hyst.attr;
513 state->group.attrs = state->attrs;
514 state->groups[0] = &state->group;
517 static int max31760_probe(struct i2c_client *client)
519 struct device *dev = &client->dev;
520 struct max31760_state *state;
521 struct device *hwmon_dev;
524 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
528 state->regmap = devm_regmap_init_i2c(client, ®map_config);
529 if (IS_ERR(state->regmap))
530 return dev_err_probe(dev,
531 PTR_ERR(state->regmap),
532 "regmap initialization failed\n");
534 dev_set_drvdata(dev, state);
536 /* Set alert output to comparator mode */
537 ret = regmap_set_bits(state->regmap, REG_CR2, CR2_ALERTS);
539 return dev_err_probe(dev, ret, "cannot write register\n");
541 max31760_create_lut_nodes(state);
543 hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
548 return PTR_ERR_OR_ZERO(hwmon_dev);
551 static const struct of_device_id max31760_of_match[] = {
552 {.compatible = "adi,max31760"},
555 MODULE_DEVICE_TABLE(of, max31760_of_match);
557 static const struct i2c_device_id max31760_id[] = {
561 MODULE_DEVICE_TABLE(i2c, max31760_id);
563 static int max31760_suspend(struct device *dev)
565 struct max31760_state *state = dev_get_drvdata(dev);
567 return regmap_set_bits(state->regmap, REG_CR2, CR2_STBY);
570 static int max31760_resume(struct device *dev)
572 struct max31760_state *state = dev_get_drvdata(dev);
574 return regmap_clear_bits(state->regmap, REG_CR2, CR2_STBY);
577 static DEFINE_SIMPLE_DEV_PM_OPS(max31760_pm_ops, max31760_suspend,
580 static struct i2c_driver max31760_driver = {
581 .class = I2C_CLASS_HWMON,
584 .of_match_table = max31760_of_match,
585 .pm = pm_ptr(&max31760_pm_ops)
587 .probe = max31760_probe,
588 .id_table = max31760_id
590 module_i2c_driver(max31760_driver);
592 MODULE_AUTHOR("Ibrahim Tilki <Ibrahim.Tilki@analog.com>");
593 MODULE_DESCRIPTION("Analog Devices MAX31760 Fan Speed Controller");
594 MODULE_SOFTDEP("pre: regmap_i2c");
595 MODULE_VERSION("1.0");
596 MODULE_LICENSE("GPL");