drivers/gpu/ipu-v3/ipu-dc.c

   1 /*
   2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
   3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15
  16 #include <linux/export.h>
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/errno.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23
  24 #include <video/imx-ipu-v3.h>
  25 #include "ipu-prv.h"
  26
  27 #define DC_MAP_CONF_PTR(n)      (0x108 + ((n) & ~0x1) * 2)
  28 #define DC_MAP_CONF_VAL(n)      (0x144 + ((n) & ~0x1) * 2)
  29
  30 #define DC_EVT_NF               0
  31 #define DC_EVT_NL               1
  32 #define DC_EVT_EOF              2
  33 #define DC_EVT_NFIELD           3
  34 #define DC_EVT_EOL              4
  35 #define DC_EVT_EOFIELD          5
  36 #define DC_EVT_NEW_ADDR         6
  37 #define DC_EVT_NEW_CHAN         7
  38 #define DC_EVT_NEW_DATA         8
  39
  40 #define DC_EVT_NEW_ADDR_W_0     0
  41 #define DC_EVT_NEW_ADDR_W_1     1
  42 #define DC_EVT_NEW_CHAN_W_0     2
  43 #define DC_EVT_NEW_CHAN_W_1     3
  44 #define DC_EVT_NEW_DATA_W_0     4
  45 #define DC_EVT_NEW_DATA_W_1     5
  46 #define DC_EVT_NEW_ADDR_R_0     6
  47 #define DC_EVT_NEW_ADDR_R_1     7
  48 #define DC_EVT_NEW_CHAN_R_0     8
  49 #define DC_EVT_NEW_CHAN_R_1     9
  50 #define DC_EVT_NEW_DATA_R_0     10
  51 #define DC_EVT_NEW_DATA_R_1     11
  52
  53 #define DC_WR_CH_CONF           0x0
  54 #define DC_WR_CH_ADDR           0x4
  55 #define DC_RL_CH(evt)           (8 + ((evt) & ~0x1) * 2)
  56
  57 #define DC_GEN                  0xd4
  58 #define DC_DISP_CONF1(disp)     (0xd8 + (disp) * 4)
  59 #define DC_DISP_CONF2(disp)     (0xe8 + (disp) * 4)
  60 #define DC_STAT                 0x1c8
  61
  62 #define WROD(lf)                (0x18 | ((lf) << 1))
  63 #define WRG                     0x01
  64 #define WCLK                    0xc9
  65
  66 #define SYNC_WAVE 0
  67 #define NULL_WAVE (-1)
  68
  69 #define DC_GEN_SYNC_1_6_SYNC    (2 << 1)
  70 #define DC_GEN_SYNC_PRIORITY_1  (1 << 7)
  71
  72 #define DC_WR_CH_CONF_WORD_SIZE_8               (0 << 0)
  73 #define DC_WR_CH_CONF_WORD_SIZE_16              (1 << 0)
  74 #define DC_WR_CH_CONF_WORD_SIZE_24              (2 << 0)
  75 #define DC_WR_CH_CONF_WORD_SIZE_32              (3 << 0)
  76 #define DC_WR_CH_CONF_DISP_ID_PARALLEL(i)       (((i) & 0x1) << 3)
  77 #define DC_WR_CH_CONF_DISP_ID_SERIAL            (2 << 3)
  78 #define DC_WR_CH_CONF_DISP_ID_ASYNC             (3 << 4)
  79 #define DC_WR_CH_CONF_FIELD_MODE                (1 << 9)
  80 #define DC_WR_CH_CONF_PROG_TYPE_NORMAL          (4 << 5)
  81 #define DC_WR_CH_CONF_PROG_TYPE_MASK            (7 << 5)
  82 #define DC_WR_CH_CONF_PROG_DI_ID                (1 << 2)
  83 #define DC_WR_CH_CONF_PROG_DISP_ID(i)           (((i) & 0x1) << 3)
  84
  85 #define IPU_DC_NUM_CHANNELS     10
  86
  87 struct ipu_dc_priv;
  88
  89 enum ipu_dc_map {
  90         IPU_DC_MAP_RGB24,
  91         IPU_DC_MAP_RGB565,
  92         IPU_DC_MAP_GBR24, /* TVEv2 */
  93         IPU_DC_MAP_BGR666,
  94         IPU_DC_MAP_LVDS666,
  95         IPU_DC_MAP_BGR24,
  96 };
  97
  98 struct ipu_dc {
  99         /* The display interface number assigned to this dc channel */
 100         unsigned int            di;
 101         void __iomem            *base;
 102         struct ipu_dc_priv      *priv;
 103         int                     chno;
 104         bool                    in_use;
 105 };
 106
 107 struct ipu_dc_priv {
 108         void __iomem            *dc_reg;
 109         void __iomem            *dc_tmpl_reg;
 110         struct ipu_soc          *ipu;
 111         struct device           *dev;
 112         struct ipu_dc           channels[IPU_DC_NUM_CHANNELS];
 113         struct mutex            mutex;
 114         struct completion       comp;
 115         int                     dc_irq;
 116         int                     dp_irq;
 117         int                     use_count;
 118 };
 119
 120 static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
 121 {
 122         u32 reg;
 123
 124         reg = readl(dc->base + DC_RL_CH(event));
 125         reg &= ~(0xffff << (16 * (event & 0x1)));
 126         reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
 127         writel(reg, dc->base + DC_RL_CH(event));
 128 }
 129
 130 static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
 131                 int map, int wave, int glue, int sync, int stop)
 132 {
 133         struct ipu_dc_priv *priv = dc->priv;
 134         u32 reg1, reg2;
 135
 136         if (opcode == WCLK) {
 137                 reg1 = (operand << 20) & 0xfff00000;
 138                 reg2 = operand >> 12 | opcode << 1 | stop << 9;
 139         } else if (opcode == WRG) {
 140                 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
 141                 reg2 = operand >> 17 | opcode << 7 | stop << 9;
 142         } else {
 143                 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
 144                 reg2 = operand >> 12 | opcode << 4 | stop << 9;
 145         }
 146         writel(reg1, priv->dc_tmpl_reg + word * 8);
 147         writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
 148 }
 149
 150 static int ipu_bus_format_to_map(u32 fmt)
 151 {
 152         switch (fmt) {
 153         case MEDIA_BUS_FMT_RGB888_1X24:
 154                 return IPU_DC_MAP_RGB24;
 155         case MEDIA_BUS_FMT_RGB565_1X16:
 156                 return IPU_DC_MAP_RGB565;
 157         case MEDIA_BUS_FMT_GBR888_1X24:
 158                 return IPU_DC_MAP_GBR24;
 159         case MEDIA_BUS_FMT_RGB666_1X18:
 160                 return IPU_DC_MAP_BGR666;
 161         case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
 162                 return IPU_DC_MAP_LVDS666;
 163         case MEDIA_BUS_FMT_BGR888_1X24:
 164                 return IPU_DC_MAP_BGR24;
 165         default:
 166                 return -EINVAL;
 167         }
 168 }
 169
 170 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
 171                 u32 bus_format, u32 width)
 172 {
 173         struct ipu_dc_priv *priv = dc->priv;
 174         u32 reg = 0;
 175         int map;
 176
 177         dc->di = ipu_di_get_num(di);
 178
 179         map = ipu_bus_format_to_map(bus_format);
 180         if (map < 0) {
 181                 dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
 182                 return map;
 183         }
 184
 185         if (interlaced) {
 186                 dc_link_event(dc, DC_EVT_NL, 0, 3);
 187                 dc_link_event(dc, DC_EVT_EOL, 0, 2);
 188                 dc_link_event(dc, DC_EVT_NEW_DATA, 0, 1);
 189
 190                 /* Init template microcode */
 191                 dc_write_tmpl(dc, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
 192         } else {
 193                 if (dc->di) {
 194                         dc_link_event(dc, DC_EVT_NL, 2, 3);
 195                         dc_link_event(dc, DC_EVT_EOL, 3, 2);
 196                         dc_link_event(dc, DC_EVT_NEW_DATA, 1, 1);
 197                         /* Init template microcode */
 198                         dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
 199                         dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
 200                         dc_write_tmpl(dc, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
 201                         dc_write_tmpl(dc, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
 202                 } else {
 203                         dc_link_event(dc, DC_EVT_NL, 5, 3);
 204                         dc_link_event(dc, DC_EVT_EOL, 6, 2);
 205                         dc_link_event(dc, DC_EVT_NEW_DATA, 8, 1);
 206                         /* Init template microcode */
 207                         dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
 208                         dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
 209                         dc_write_tmpl(dc, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1);
 210                         dc_write_tmpl(dc, 8, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
 211                 }
 212         }
 213         dc_link_event(dc, DC_EVT_NF, 0, 0);
 214         dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
 215         dc_link_event(dc, DC_EVT_EOF, 0, 0);
 216         dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
 217         dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
 218         dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
 219
 220         reg = readl(dc->base + DC_WR_CH_CONF);
 221         if (interlaced)
 222                 reg |= DC_WR_CH_CONF_FIELD_MODE;
 223         else
 224                 reg &= ~DC_WR_CH_CONF_FIELD_MODE;
 225         writel(reg, dc->base + DC_WR_CH_CONF);
 226
 227         writel(0x0, dc->base + DC_WR_CH_ADDR);
 228         writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
 229
 230         return 0;
 231 }
 232 EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
 233
 234 void ipu_dc_enable(struct ipu_soc *ipu)
 235 {
 236         struct ipu_dc_priv *priv = ipu->dc_priv;
 237
 238         mutex_lock(&priv->mutex);
 239
 240         if (!priv->use_count)
 241                 ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
 242
 243         priv->use_count++;
 244
 245         mutex_unlock(&priv->mutex);
 246 }
 247 EXPORT_SYMBOL_GPL(ipu_dc_enable);
 248
 249 void ipu_dc_enable_channel(struct ipu_dc *dc)
 250 {
 251         int di;
 252         u32 reg;
 253
 254         di = dc->di;
 255
 256         reg = readl(dc->base + DC_WR_CH_CONF);
 257         reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
 258         writel(reg, dc->base + DC_WR_CH_CONF);
 259 }
 260 EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
 261
 262 static irqreturn_t dc_irq_handler(int irq, void *dev_id)
 263 {
 264         struct ipu_dc *dc = dev_id;
 265         u32 reg;
 266
 267         reg = readl(dc->base + DC_WR_CH_CONF);
 268         reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 269         writel(reg, dc->base + DC_WR_CH_CONF);
 270
 271         /* The Freescale BSP kernel clears DIx_COUNTER_RELEASE here */
 272
 273         complete(&dc->priv->comp);
 274         return IRQ_HANDLED;
 275 }
 276
 277 void ipu_dc_disable_channel(struct ipu_dc *dc)
 278 {
 279         struct ipu_dc_priv *priv = dc->priv;
 280         int irq;
 281         unsigned long ret;
 282         u32 val;
 283
 284         /* TODO: Handle MEM_FG_SYNC differently from MEM_BG_SYNC */
 285         if (dc->chno == 1)
 286                 irq = priv->dc_irq;
 287         else if (dc->chno == 5)
 288                 irq = priv->dp_irq;
 289         else
 290                 return;
 291
 292         init_completion(&priv->comp);
 293         enable_irq(irq);
 294         ret = wait_for_completion_timeout(&priv->comp, msecs_to_jiffies(50));
 295         disable_irq(irq);
 296         if (ret == 0) {
 297                 dev_warn(priv->dev, "DC stop timeout after 50 ms\n");
 298
 299                 val = readl(dc->base + DC_WR_CH_CONF);
 300                 val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
 301                 writel(val, dc->base + DC_WR_CH_CONF);
 302         }
 303 }
 304 EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
 305
 306 void ipu_dc_disable(struct ipu_soc *ipu)
 307 {
 308         struct ipu_dc_priv *priv = ipu->dc_priv;
 309
 310         mutex_lock(&priv->mutex);
 311
 312         priv->use_count--;
 313         if (!priv->use_count)
 314                 ipu_module_disable(priv->ipu, IPU_CONF_DC_EN);
 315
 316         if (priv->use_count < 0)
 317                 priv->use_count = 0;
 318
 319         mutex_unlock(&priv->mutex);
 320 }
 321 EXPORT_SYMBOL_GPL(ipu_dc_disable);
 322
 323 static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
 324                 int byte_num, int offset, int mask)
 325 {
 326         int ptr = map * 3 + byte_num;
 327         u32 reg;
 328
 329         reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
 330         reg &= ~(0xffff << (16 * (ptr & 0x1)));
 331         reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
 332         writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
 333
 334         reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
 335         reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
 336         reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
 337         writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
 338 }
 339
 340 static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
 341 {
 342         u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
 343
 344         writel(reg & ~(0xffff << (16 * (map & 0x1))),
 345                      priv->dc_reg + DC_MAP_CONF_PTR(map));
 346 }
 347
 348 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
 349 {
 350         struct ipu_dc_priv *priv = ipu->dc_priv;
 351         struct ipu_dc *dc;
 352
 353         if (channel >= IPU_DC_NUM_CHANNELS)
 354                 return ERR_PTR(-ENODEV);
 355
 356         dc = &priv->channels[channel];
 357
 358         mutex_lock(&priv->mutex);
 359
 360         if (dc->in_use) {
 361                 mutex_unlock(&priv->mutex);
 362                 return ERR_PTR(-EBUSY);
 363         }
 364
 365         dc->in_use = true;
 366
 367         mutex_unlock(&priv->mutex);
 368
 369         return dc;
 370 }
 371 EXPORT_SYMBOL_GPL(ipu_dc_get);
 372
 373 void ipu_dc_put(struct ipu_dc *dc)
 374 {
 375         struct ipu_dc_priv *priv = dc->priv;
 376
 377         mutex_lock(&priv->mutex);
 378         dc->in_use = false;
 379         mutex_unlock(&priv->mutex);
 380 }
 381 EXPORT_SYMBOL_GPL(ipu_dc_put);
 382
 383 int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
 384                 unsigned long base, unsigned long template_base)
 385 {
 386         struct ipu_dc_priv *priv;
 387         static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
 388                 0x78, 0, 0x94, 0xb4};
 389         int i, ret;
 390
 391         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 392         if (!priv)
 393                 return -ENOMEM;
 394
 395         mutex_init(&priv->mutex);
 396
 397         priv->dev = dev;
 398         priv->ipu = ipu;
 399         priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
 400         priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
 401         if (!priv->dc_reg || !priv->dc_tmpl_reg)
 402                 return -ENOMEM;
 403
 404         for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
 405                 priv->channels[i].chno = i;
 406                 priv->channels[i].priv = priv;
 407                 priv->channels[i].base = priv->dc_reg + channel_offsets[i];
 408         }
 409
 410         priv->dc_irq = ipu_map_irq(ipu, IPU_IRQ_DC_FC_1);
 411         if (!priv->dc_irq)
 412                 return -EINVAL;
 413         ret = devm_request_irq(dev, priv->dc_irq, dc_irq_handler, 0, NULL,
 414                                &priv->channels[1]);
 415         if (ret < 0)
 416                 return ret;
 417         disable_irq(priv->dc_irq);
 418         priv->dp_irq = ipu_map_irq(ipu, IPU_IRQ_DP_SF_END);
 419         if (!priv->dp_irq)
 420                 return -EINVAL;
 421         ret = devm_request_irq(dev, priv->dp_irq, dc_irq_handler, 0, NULL,
 422                                &priv->channels[5]);
 423         if (ret < 0)
 424                 return ret;
 425         disable_irq(priv->dp_irq);
 426
 427         writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
 428                         DC_WR_CH_CONF_PROG_DI_ID,
 429                         priv->channels[1].base + DC_WR_CH_CONF);
 430         writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
 431                         priv->channels[5].base + DC_WR_CH_CONF);
 432
 433         writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1,
 434                 priv->dc_reg + DC_GEN);
 435
 436         ipu->dc_priv = priv;
 437
 438         dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
 439                         base, template_base);
 440
 441         /* rgb24 */
 442         ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
 443         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
 444         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
 445         ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
 446
 447         /* rgb565 */
 448         ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
 449         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
 450         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
 451         ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
 452
 453         /* gbr24 */
 454         ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
 455         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
 456         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
 457         ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
 458
 459         /* bgr666 */
 460         ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
 461         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
 462         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
 463         ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
 464
 465         /* lvds666 */
 466         ipu_dc_map_clear(priv, IPU_DC_MAP_LVDS666);
 467         ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 0, 5, 0xfc); /* blue */
 468         ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 1, 13, 0xfc); /* green */
 469         ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 2, 21, 0xfc); /* red */
 470
 471         /* bgr24 */
 472         ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
 473         ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
 474         ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
 475         ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
 476
 477         return 0;
 478 }
 479
 480 void ipu_dc_exit(struct ipu_soc *ipu)
 481 {
 482 }