2 * Copyright (C) 2012-2014 Mentor Graphics Inc.
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 #include <linux/export.h>
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/videodev2.h>
24 #include <uapi/linux/v4l2-mediabus.h>
25 #include <linux/clk.h>
26 #include <linux/clk-provider.h>
27 #include <linux/clkdev.h>
35 struct clk *clk_ipu; /* IPU bus clock */
41 /* CSI Register Offsets */
42 #define CSI_SENS_CONF 0x0000
43 #define CSI_SENS_FRM_SIZE 0x0004
44 #define CSI_ACT_FRM_SIZE 0x0008
45 #define CSI_OUT_FRM_CTRL 0x000c
46 #define CSI_TST_CTRL 0x0010
47 #define CSI_CCIR_CODE_1 0x0014
48 #define CSI_CCIR_CODE_2 0x0018
49 #define CSI_CCIR_CODE_3 0x001c
50 #define CSI_MIPI_DI 0x0020
51 #define CSI_SKIP 0x0024
52 #define CSI_CPD_CTRL 0x0028
53 #define CSI_CPD_RC(n) (0x002c + ((n)*4))
54 #define CSI_CPD_RS(n) (0x004c + ((n)*4))
55 #define CSI_CPD_GRC(n) (0x005c + ((n)*4))
56 #define CSI_CPD_GRS(n) (0x007c + ((n)*4))
57 #define CSI_CPD_GBC(n) (0x008c + ((n)*4))
58 #define CSI_CPD_GBS(n) (0x00Ac + ((n)*4))
59 #define CSI_CPD_BC(n) (0x00Bc + ((n)*4))
60 #define CSI_CPD_BS(n) (0x00Dc + ((n)*4))
61 #define CSI_CPD_OFFSET1 0x00ec
62 #define CSI_CPD_OFFSET2 0x00f0
64 /* CSI Register Fields */
65 #define CSI_SENS_CONF_DATA_FMT_SHIFT 8
66 #define CSI_SENS_CONF_DATA_FMT_MASK 0x00000700
67 #define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 0L
68 #define CSI_SENS_CONF_DATA_FMT_YUV422_YUYV 1L
69 #define CSI_SENS_CONF_DATA_FMT_YUV422_UYVY 2L
70 #define CSI_SENS_CONF_DATA_FMT_BAYER 3L
71 #define CSI_SENS_CONF_DATA_FMT_RGB565 4L
72 #define CSI_SENS_CONF_DATA_FMT_RGB555 5L
73 #define CSI_SENS_CONF_DATA_FMT_RGB444 6L
74 #define CSI_SENS_CONF_DATA_FMT_JPEG 7L
76 #define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
77 #define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
78 #define CSI_SENS_CONF_DATA_POL_SHIFT 2
79 #define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
80 #define CSI_SENS_CONF_SENS_PRTCL_MASK 0x00000070
81 #define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
82 #define CSI_SENS_CONF_PACK_TIGHT_SHIFT 7
83 #define CSI_SENS_CONF_DATA_WIDTH_SHIFT 11
84 #define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
85 #define CSI_SENS_CONF_DIVRATIO_SHIFT 16
87 #define CSI_SENS_CONF_DIVRATIO_MASK 0x00ff0000
88 #define CSI_SENS_CONF_DATA_DEST_SHIFT 24
89 #define CSI_SENS_CONF_DATA_DEST_MASK 0x07000000
90 #define CSI_SENS_CONF_JPEG8_EN_SHIFT 27
91 #define CSI_SENS_CONF_JPEG_EN_SHIFT 28
92 #define CSI_SENS_CONF_FORCE_EOF_SHIFT 29
93 #define CSI_SENS_CONF_DATA_EN_POL_SHIFT 31
95 #define CSI_DATA_DEST_IC 2
96 #define CSI_DATA_DEST_IDMAC 4
98 #define CSI_CCIR_ERR_DET_EN 0x01000000
99 #define CSI_HORI_DOWNSIZE_EN 0x80000000
100 #define CSI_VERT_DOWNSIZE_EN 0x40000000
101 #define CSI_TEST_GEN_MODE_EN 0x01000000
103 #define CSI_HSC_MASK 0x1fff0000
104 #define CSI_HSC_SHIFT 16
105 #define CSI_VSC_MASK 0x00000fff
106 #define CSI_VSC_SHIFT 0
108 #define CSI_TEST_GEN_R_MASK 0x000000ff
109 #define CSI_TEST_GEN_R_SHIFT 0
110 #define CSI_TEST_GEN_G_MASK 0x0000ff00
111 #define CSI_TEST_GEN_G_SHIFT 8
112 #define CSI_TEST_GEN_B_MASK 0x00ff0000
113 #define CSI_TEST_GEN_B_SHIFT 16
115 #define CSI_MAX_RATIO_SKIP_SMFC_MASK 0x00000007
116 #define CSI_MAX_RATIO_SKIP_SMFC_SHIFT 0
117 #define CSI_SKIP_SMFC_MASK 0x000000f8
118 #define CSI_SKIP_SMFC_SHIFT 3
119 #define CSI_ID_2_SKIP_MASK 0x00000300
120 #define CSI_ID_2_SKIP_SHIFT 8
122 #define CSI_COLOR_FIRST_ROW_MASK 0x00000002
123 #define CSI_COLOR_FIRST_COMP_MASK 0x00000001
125 /* MIPI CSI-2 data types */
126 #define MIPI_DT_YUV420 0x18 /* YYY.../UYVY.... */
127 #define MIPI_DT_YUV420_LEGACY 0x1a /* UYY.../VYY... */
128 #define MIPI_DT_YUV422 0x1e /* UYVY... */
129 #define MIPI_DT_RGB444 0x20
130 #define MIPI_DT_RGB555 0x21
131 #define MIPI_DT_RGB565 0x22
132 #define MIPI_DT_RGB666 0x23
133 #define MIPI_DT_RGB888 0x24
134 #define MIPI_DT_RAW6 0x28
135 #define MIPI_DT_RAW7 0x29
136 #define MIPI_DT_RAW8 0x2a
137 #define MIPI_DT_RAW10 0x2b
138 #define MIPI_DT_RAW12 0x2c
139 #define MIPI_DT_RAW14 0x2d
142 * Bitfield of CSI bus signal polarities and modes.
144 struct ipu_csi_bus_config {
145 unsigned data_width:4;
147 unsigned ext_vsync:1;
148 unsigned vsync_pol:1;
149 unsigned hsync_pol:1;
150 unsigned pixclk_pol:1;
152 unsigned sens_clksrc:1;
153 unsigned pack_tight:1;
154 unsigned force_eof:1;
155 unsigned data_en_pol:1;
162 * Enumeration of CSI data bus widths.
164 enum ipu_csi_data_width {
165 IPU_CSI_DATA_WIDTH_4 = 0,
166 IPU_CSI_DATA_WIDTH_8 = 1,
167 IPU_CSI_DATA_WIDTH_10 = 3,
168 IPU_CSI_DATA_WIDTH_12 = 5,
169 IPU_CSI_DATA_WIDTH_16 = 9,
173 * Enumeration of CSI clock modes.
175 enum ipu_csi_clk_mode {
176 IPU_CSI_CLK_MODE_GATED_CLK,
177 IPU_CSI_CLK_MODE_NONGATED_CLK,
178 IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
179 IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
180 IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
181 IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
182 IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
183 IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
186 static inline u32 ipu_csi_read(struct ipu_csi *csi, unsigned offset)
188 return readl(csi->base + offset);
191 static inline void ipu_csi_write(struct ipu_csi *csi, u32 value,
194 writel(value, csi->base + offset);
198 * Set mclk division ratio for generating test mode mclk. Only used
199 * for test generator.
201 static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk,
207 div_ratio = (ipu_clk / pixel_clk) - 1;
209 if (div_ratio > 0xFF || div_ratio < 0) {
210 dev_err(csi->ipu->dev,
211 "value of pixel_clk extends normal range\n");
215 temp = ipu_csi_read(csi, CSI_SENS_CONF);
216 temp &= ~CSI_SENS_CONF_DIVRATIO_MASK;
217 ipu_csi_write(csi, temp | (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT),
224 * Find the CSI data format and data width for the given V4L2 media
225 * bus pixel format code.
227 static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code)
230 case MEDIA_BUS_FMT_BGR565_2X8_BE:
231 case MEDIA_BUS_FMT_BGR565_2X8_LE:
232 case MEDIA_BUS_FMT_RGB565_2X8_BE:
233 case MEDIA_BUS_FMT_RGB565_2X8_LE:
234 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565;
235 cfg->mipi_dt = MIPI_DT_RGB565;
236 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
238 case MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE:
239 case MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE:
240 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB444;
241 cfg->mipi_dt = MIPI_DT_RGB444;
242 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
244 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
245 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
246 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555;
247 cfg->mipi_dt = MIPI_DT_RGB555;
248 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
250 case MEDIA_BUS_FMT_UYVY8_2X8:
251 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
252 cfg->mipi_dt = MIPI_DT_YUV422;
253 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
255 case MEDIA_BUS_FMT_YUYV8_2X8:
256 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
257 cfg->mipi_dt = MIPI_DT_YUV422;
258 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
260 case MEDIA_BUS_FMT_UYVY8_1X16:
261 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
262 cfg->mipi_dt = MIPI_DT_YUV422;
263 cfg->data_width = IPU_CSI_DATA_WIDTH_16;
265 case MEDIA_BUS_FMT_YUYV8_1X16:
266 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
267 cfg->mipi_dt = MIPI_DT_YUV422;
268 cfg->data_width = IPU_CSI_DATA_WIDTH_16;
270 case MEDIA_BUS_FMT_SBGGR8_1X8:
271 case MEDIA_BUS_FMT_SGBRG8_1X8:
272 case MEDIA_BUS_FMT_SGRBG8_1X8:
273 case MEDIA_BUS_FMT_SRGGB8_1X8:
274 case MEDIA_BUS_FMT_Y8_1X8:
275 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
276 cfg->mipi_dt = MIPI_DT_RAW8;
277 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
279 case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
280 case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
281 case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
282 case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
283 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
284 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
285 case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE:
286 case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE:
287 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
288 cfg->mipi_dt = MIPI_DT_RAW10;
289 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
291 case MEDIA_BUS_FMT_SBGGR10_1X10:
292 case MEDIA_BUS_FMT_SGBRG10_1X10:
293 case MEDIA_BUS_FMT_SGRBG10_1X10:
294 case MEDIA_BUS_FMT_SRGGB10_1X10:
295 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
296 cfg->mipi_dt = MIPI_DT_RAW10;
297 cfg->data_width = IPU_CSI_DATA_WIDTH_10;
299 case MEDIA_BUS_FMT_SBGGR12_1X12:
300 case MEDIA_BUS_FMT_SGBRG12_1X12:
301 case MEDIA_BUS_FMT_SGRBG12_1X12:
302 case MEDIA_BUS_FMT_SRGGB12_1X12:
303 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
304 cfg->mipi_dt = MIPI_DT_RAW12;
305 cfg->data_width = IPU_CSI_DATA_WIDTH_12;
307 case MEDIA_BUS_FMT_JPEG_1X8:
309 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_JPEG;
310 cfg->mipi_dt = MIPI_DT_RAW8;
311 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
321 * Fill a CSI bus config struct from mbus_config and mbus_framefmt.
323 static void fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg,
324 struct v4l2_mbus_config *mbus_cfg,
325 struct v4l2_mbus_framefmt *mbus_fmt)
327 memset(csicfg, 0, sizeof(*csicfg));
329 mbus_code_to_bus_cfg(csicfg, mbus_fmt->code);
331 switch (mbus_cfg->type) {
332 case V4L2_MBUS_PARALLEL:
333 csicfg->ext_vsync = 1;
334 csicfg->vsync_pol = (mbus_cfg->flags &
335 V4L2_MBUS_VSYNC_ACTIVE_LOW) ? 1 : 0;
336 csicfg->hsync_pol = (mbus_cfg->flags &
337 V4L2_MBUS_HSYNC_ACTIVE_LOW) ? 1 : 0;
338 csicfg->pixclk_pol = (mbus_cfg->flags &
339 V4L2_MBUS_PCLK_SAMPLE_FALLING) ? 1 : 0;
340 csicfg->clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
342 case V4L2_MBUS_BT656:
343 csicfg->ext_vsync = 0;
344 if (V4L2_FIELD_HAS_BOTH(mbus_fmt->field))
345 csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
347 csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
351 * MIPI CSI-2 requires non gated clock mode, all other
352 * parameters are not applicable for MIPI CSI-2 bus.
354 csicfg->clk_mode = IPU_CSI_CLK_MODE_NONGATED_CLK;
357 /* will never get here, keep compiler quiet */
362 int ipu_csi_init_interface(struct ipu_csi *csi,
363 struct v4l2_mbus_config *mbus_cfg,
364 struct v4l2_mbus_framefmt *mbus_fmt)
366 struct ipu_csi_bus_config cfg;
368 u32 width, height, data = 0;
370 fill_csi_bus_cfg(&cfg, mbus_cfg, mbus_fmt);
372 /* set default sensor frame width and height */
373 width = mbus_fmt->width;
374 height = mbus_fmt->height;
376 /* Set the CSI_SENS_CONF register remaining fields */
377 data |= cfg.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
378 cfg.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
379 cfg.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
380 cfg.vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
381 cfg.hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
382 cfg.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
383 cfg.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
384 cfg.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
385 cfg.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT |
386 cfg.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT |
387 cfg.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT;
389 spin_lock_irqsave(&csi->lock, flags);
391 ipu_csi_write(csi, data, CSI_SENS_CONF);
393 /* Set CCIR registers */
395 switch (cfg.clk_mode) {
396 case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
397 ipu_csi_write(csi, 0x40030, CSI_CCIR_CODE_1);
398 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
400 case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
401 if (mbus_fmt->width == 720 && mbus_fmt->height == 576) {
405 * Field0BlankEnd = 0x6, Field0BlankStart = 0x2,
406 * Field0ActiveEnd = 0x4, Field0ActiveStart = 0
407 * Field1BlankEnd = 0x7, Field1BlankStart = 0x3,
408 * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1
410 height = 625; /* framelines for PAL */
412 ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN,
414 ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2);
415 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
416 } else if (mbus_fmt->width == 720 && mbus_fmt->height == 480) {
420 * Field0BlankEnd = 0x7, Field0BlankStart = 0x3,
421 * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1
422 * Field1BlankEnd = 0x6, Field1BlankStart = 0x2,
423 * Field1ActiveEnd = 0x4, Field1ActiveStart = 0
425 height = 525; /* framelines for NTSC */
427 ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN,
429 ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2);
430 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
432 dev_err(csi->ipu->dev,
433 "Unsupported CCIR656 interlaced video mode\n");
434 spin_unlock_irqrestore(&csi->lock, flags);
438 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
439 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
440 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
441 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
442 ipu_csi_write(csi, 0x40030 | CSI_CCIR_ERR_DET_EN,
444 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
446 case IPU_CSI_CLK_MODE_GATED_CLK:
447 case IPU_CSI_CLK_MODE_NONGATED_CLK:
448 ipu_csi_write(csi, 0, CSI_CCIR_CODE_1);
452 /* Setup sensor frame size */
453 ipu_csi_write(csi, (width - 1) | ((height - 1) << 16),
456 dev_dbg(csi->ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
457 ipu_csi_read(csi, CSI_SENS_CONF));
458 dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
459 ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
461 spin_unlock_irqrestore(&csi->lock, flags);
465 EXPORT_SYMBOL_GPL(ipu_csi_init_interface);
467 bool ipu_csi_is_interlaced(struct ipu_csi *csi)
472 spin_lock_irqsave(&csi->lock, flags);
474 (ipu_csi_read(csi, CSI_SENS_CONF) &
475 CSI_SENS_CONF_SENS_PRTCL_MASK) >>
476 CSI_SENS_CONF_SENS_PRTCL_SHIFT;
477 spin_unlock_irqrestore(&csi->lock, flags);
479 switch (sensor_protocol) {
480 case IPU_CSI_CLK_MODE_GATED_CLK:
481 case IPU_CSI_CLK_MODE_NONGATED_CLK:
482 case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
483 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
484 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
486 case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
487 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
488 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
491 dev_err(csi->ipu->dev,
492 "CSI %d sensor protocol unsupported\n", csi->id);
496 EXPORT_SYMBOL_GPL(ipu_csi_is_interlaced);
498 void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w)
503 spin_lock_irqsave(&csi->lock, flags);
505 reg = ipu_csi_read(csi, CSI_ACT_FRM_SIZE);
506 w->width = (reg & 0xFFFF) + 1;
507 w->height = (reg >> 16 & 0xFFFF) + 1;
509 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
510 w->left = (reg & CSI_HSC_MASK) >> CSI_HSC_SHIFT;
511 w->top = (reg & CSI_VSC_MASK) >> CSI_VSC_SHIFT;
513 spin_unlock_irqrestore(&csi->lock, flags);
515 EXPORT_SYMBOL_GPL(ipu_csi_get_window);
517 void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w)
522 spin_lock_irqsave(&csi->lock, flags);
524 ipu_csi_write(csi, (w->width - 1) | ((w->height - 1) << 16),
527 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
528 reg &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
529 reg |= ((w->top << CSI_VSC_SHIFT) | (w->left << CSI_HSC_SHIFT));
530 ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
532 spin_unlock_irqrestore(&csi->lock, flags);
534 EXPORT_SYMBOL_GPL(ipu_csi_set_window);
536 void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
537 u32 r_value, u32 g_value, u32 b_value,
541 u32 ipu_clk = clk_get_rate(csi->clk_ipu);
544 spin_lock_irqsave(&csi->lock, flags);
546 temp = ipu_csi_read(csi, CSI_TST_CTRL);
549 temp &= ~CSI_TEST_GEN_MODE_EN;
550 ipu_csi_write(csi, temp, CSI_TST_CTRL);
552 /* Set sensb_mclk div_ratio */
553 ipu_csi_set_testgen_mclk(csi, pix_clk, ipu_clk);
555 temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK |
556 CSI_TEST_GEN_B_MASK);
557 temp |= CSI_TEST_GEN_MODE_EN;
558 temp |= (r_value << CSI_TEST_GEN_R_SHIFT) |
559 (g_value << CSI_TEST_GEN_G_SHIFT) |
560 (b_value << CSI_TEST_GEN_B_SHIFT);
561 ipu_csi_write(csi, temp, CSI_TST_CTRL);
564 spin_unlock_irqrestore(&csi->lock, flags);
566 EXPORT_SYMBOL_GPL(ipu_csi_set_test_generator);
568 int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
569 struct v4l2_mbus_framefmt *mbus_fmt)
571 struct ipu_csi_bus_config cfg;
578 mbus_code_to_bus_cfg(&cfg, mbus_fmt->code);
580 spin_lock_irqsave(&csi->lock, flags);
582 temp = ipu_csi_read(csi, CSI_MIPI_DI);
583 temp &= ~(0xff << (vc * 8));
584 temp |= (cfg.mipi_dt << (vc * 8));
585 ipu_csi_write(csi, temp, CSI_MIPI_DI);
587 spin_unlock_irqrestore(&csi->lock, flags);
591 EXPORT_SYMBOL_GPL(ipu_csi_set_mipi_datatype);
593 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
594 u32 max_ratio, u32 id)
599 if (max_ratio > 5 || id > 3)
602 spin_lock_irqsave(&csi->lock, flags);
604 temp = ipu_csi_read(csi, CSI_SKIP);
605 temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK |
607 temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) |
608 (id << CSI_ID_2_SKIP_SHIFT) |
609 (skip << CSI_SKIP_SMFC_SHIFT);
610 ipu_csi_write(csi, temp, CSI_SKIP);
612 spin_unlock_irqrestore(&csi->lock, flags);
616 EXPORT_SYMBOL_GPL(ipu_csi_set_skip_smfc);
618 int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest)
621 u32 csi_sens_conf, dest;
623 if (csi_dest == IPU_CSI_DEST_IDMAC)
624 dest = CSI_DATA_DEST_IDMAC;
626 dest = CSI_DATA_DEST_IC; /* IC or VDIC */
628 spin_lock_irqsave(&csi->lock, flags);
630 csi_sens_conf = ipu_csi_read(csi, CSI_SENS_CONF);
631 csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK;
632 csi_sens_conf |= (dest << CSI_SENS_CONF_DATA_DEST_SHIFT);
633 ipu_csi_write(csi, csi_sens_conf, CSI_SENS_CONF);
635 spin_unlock_irqrestore(&csi->lock, flags);
639 EXPORT_SYMBOL_GPL(ipu_csi_set_dest);
641 int ipu_csi_enable(struct ipu_csi *csi)
643 ipu_module_enable(csi->ipu, csi->module);
647 EXPORT_SYMBOL_GPL(ipu_csi_enable);
649 int ipu_csi_disable(struct ipu_csi *csi)
651 ipu_module_disable(csi->ipu, csi->module);
655 EXPORT_SYMBOL_GPL(ipu_csi_disable);
657 struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id)
660 struct ipu_csi *csi, *ret;
663 return ERR_PTR(-EINVAL);
665 csi = ipu->csi_priv[id];
668 spin_lock_irqsave(&csi->lock, flags);
671 ret = ERR_PTR(-EBUSY);
677 spin_unlock_irqrestore(&csi->lock, flags);
680 EXPORT_SYMBOL_GPL(ipu_csi_get);
682 void ipu_csi_put(struct ipu_csi *csi)
686 spin_lock_irqsave(&csi->lock, flags);
688 spin_unlock_irqrestore(&csi->lock, flags);
690 EXPORT_SYMBOL_GPL(ipu_csi_put);
692 int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
693 unsigned long base, u32 module, struct clk *clk_ipu)
700 csi = devm_kzalloc(dev, sizeof(*csi), GFP_KERNEL);
704 ipu->csi_priv[id] = csi;
706 spin_lock_init(&csi->lock);
707 csi->module = module;
709 csi->clk_ipu = clk_ipu;
710 csi->base = devm_ioremap(dev, base, PAGE_SIZE);
714 dev_dbg(dev, "CSI%d base: 0x%08lx remapped to %p\n",
715 id, base, csi->base);
721 void ipu_csi_exit(struct ipu_soc *ipu, int id)
725 void ipu_csi_dump(struct ipu_csi *csi)
727 dev_dbg(csi->ipu->dev, "CSI_SENS_CONF: %08x\n",
728 ipu_csi_read(csi, CSI_SENS_CONF));
729 dev_dbg(csi->ipu->dev, "CSI_SENS_FRM_SIZE: %08x\n",
730 ipu_csi_read(csi, CSI_SENS_FRM_SIZE));
731 dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE: %08x\n",
732 ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
733 dev_dbg(csi->ipu->dev, "CSI_OUT_FRM_CTRL: %08x\n",
734 ipu_csi_read(csi, CSI_OUT_FRM_CTRL));
735 dev_dbg(csi->ipu->dev, "CSI_TST_CTRL: %08x\n",
736 ipu_csi_read(csi, CSI_TST_CTRL));
737 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_1: %08x\n",
738 ipu_csi_read(csi, CSI_CCIR_CODE_1));
739 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_2: %08x\n",
740 ipu_csi_read(csi, CSI_CCIR_CODE_2));
741 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_3: %08x\n",
742 ipu_csi_read(csi, CSI_CCIR_CODE_3));
743 dev_dbg(csi->ipu->dev, "CSI_MIPI_DI: %08x\n",
744 ipu_csi_read(csi, CSI_MIPI_DI));
745 dev_dbg(csi->ipu->dev, "CSI_SKIP: %08x\n",
746 ipu_csi_read(csi, CSI_SKIP));
748 EXPORT_SYMBOL_GPL(ipu_csi_dump);