drivers/gpu/ipu-v3/ipu-cpmem.c

   1 /*
   2  * Copyright (C) 2012 Mentor Graphics Inc.
   3  * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12 #include <linux/types.h>
  13 #include <linux/bitrev.h>
  14 #include <linux/io.h>
  15 #include <linux/sizes.h>
  16 #include <drm/drm_fourcc.h>
  17 #include "ipu-prv.h"
  18
  19 struct ipu_cpmem_word {
  20         u32 data[5];
  21         u32 res[3];
  22 };
  23
  24 struct ipu_ch_param {
  25         struct ipu_cpmem_word word[2];
  26 };
  27
  28 struct ipu_cpmem {
  29         struct ipu_ch_param __iomem *base;
  30         u32 module;
  31         spinlock_t lock;
  32         int use_count;
  33         struct ipu_soc *ipu;
  34 };
  35
  36 #define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
  37
  38 #define IPU_FIELD_UBO           IPU_CPMEM_WORD(0, 46, 22)
  39 #define IPU_FIELD_VBO           IPU_CPMEM_WORD(0, 68, 22)
  40 #define IPU_FIELD_IOX           IPU_CPMEM_WORD(0, 90, 4)
  41 #define IPU_FIELD_RDRW          IPU_CPMEM_WORD(0, 94, 1)
  42 #define IPU_FIELD_SO            IPU_CPMEM_WORD(0, 113, 1)
  43 #define IPU_FIELD_SLY           IPU_CPMEM_WORD(1, 102, 14)
  44 #define IPU_FIELD_SLUV          IPU_CPMEM_WORD(1, 128, 14)
  45
  46 #define IPU_FIELD_XV            IPU_CPMEM_WORD(0, 0, 10)
  47 #define IPU_FIELD_YV            IPU_CPMEM_WORD(0, 10, 9)
  48 #define IPU_FIELD_XB            IPU_CPMEM_WORD(0, 19, 13)
  49 #define IPU_FIELD_YB            IPU_CPMEM_WORD(0, 32, 12)
  50 #define IPU_FIELD_NSB_B         IPU_CPMEM_WORD(0, 44, 1)
  51 #define IPU_FIELD_CF            IPU_CPMEM_WORD(0, 45, 1)
  52 #define IPU_FIELD_SX            IPU_CPMEM_WORD(0, 46, 12)
  53 #define IPU_FIELD_SY            IPU_CPMEM_WORD(0, 58, 11)
  54 #define IPU_FIELD_NS            IPU_CPMEM_WORD(0, 69, 10)
  55 #define IPU_FIELD_SDX           IPU_CPMEM_WORD(0, 79, 7)
  56 #define IPU_FIELD_SM            IPU_CPMEM_WORD(0, 86, 10)
  57 #define IPU_FIELD_SCC           IPU_CPMEM_WORD(0, 96, 1)
  58 #define IPU_FIELD_SCE           IPU_CPMEM_WORD(0, 97, 1)
  59 #define IPU_FIELD_SDY           IPU_CPMEM_WORD(0, 98, 7)
  60 #define IPU_FIELD_SDRX          IPU_CPMEM_WORD(0, 105, 1)
  61 #define IPU_FIELD_SDRY          IPU_CPMEM_WORD(0, 106, 1)
  62 #define IPU_FIELD_BPP           IPU_CPMEM_WORD(0, 107, 3)
  63 #define IPU_FIELD_DEC_SEL       IPU_CPMEM_WORD(0, 110, 2)
  64 #define IPU_FIELD_DIM           IPU_CPMEM_WORD(0, 112, 1)
  65 #define IPU_FIELD_BNDM          IPU_CPMEM_WORD(0, 114, 3)
  66 #define IPU_FIELD_BM            IPU_CPMEM_WORD(0, 117, 2)
  67 #define IPU_FIELD_ROT           IPU_CPMEM_WORD(0, 119, 1)
  68 #define IPU_FIELD_ROT_HF_VF     IPU_CPMEM_WORD(0, 119, 3)
  69 #define IPU_FIELD_HF            IPU_CPMEM_WORD(0, 120, 1)
  70 #define IPU_FIELD_VF            IPU_CPMEM_WORD(0, 121, 1)
  71 #define IPU_FIELD_THE           IPU_CPMEM_WORD(0, 122, 1)
  72 #define IPU_FIELD_CAP           IPU_CPMEM_WORD(0, 123, 1)
  73 #define IPU_FIELD_CAE           IPU_CPMEM_WORD(0, 124, 1)
  74 #define IPU_FIELD_FW            IPU_CPMEM_WORD(0, 125, 13)
  75 #define IPU_FIELD_FH            IPU_CPMEM_WORD(0, 138, 12)
  76 #define IPU_FIELD_EBA0          IPU_CPMEM_WORD(1, 0, 29)
  77 #define IPU_FIELD_EBA1          IPU_CPMEM_WORD(1, 29, 29)
  78 #define IPU_FIELD_ILO           IPU_CPMEM_WORD(1, 58, 20)
  79 #define IPU_FIELD_NPB           IPU_CPMEM_WORD(1, 78, 7)
  80 #define IPU_FIELD_PFS           IPU_CPMEM_WORD(1, 85, 4)
  81 #define IPU_FIELD_ALU           IPU_CPMEM_WORD(1, 89, 1)
  82 #define IPU_FIELD_ALBM          IPU_CPMEM_WORD(1, 90, 3)
  83 #define IPU_FIELD_ID            IPU_CPMEM_WORD(1, 93, 2)
  84 #define IPU_FIELD_TH            IPU_CPMEM_WORD(1, 95, 7)
  85 #define IPU_FIELD_SL            IPU_CPMEM_WORD(1, 102, 14)
  86 #define IPU_FIELD_WID0          IPU_CPMEM_WORD(1, 116, 3)
  87 #define IPU_FIELD_WID1          IPU_CPMEM_WORD(1, 119, 3)
  88 #define IPU_FIELD_WID2          IPU_CPMEM_WORD(1, 122, 3)
  89 #define IPU_FIELD_WID3          IPU_CPMEM_WORD(1, 125, 3)
  90 #define IPU_FIELD_OFS0          IPU_CPMEM_WORD(1, 128, 5)
  91 #define IPU_FIELD_OFS1          IPU_CPMEM_WORD(1, 133, 5)
  92 #define IPU_FIELD_OFS2          IPU_CPMEM_WORD(1, 138, 5)
  93 #define IPU_FIELD_OFS3          IPU_CPMEM_WORD(1, 143, 5)
  94 #define IPU_FIELD_SXYS          IPU_CPMEM_WORD(1, 148, 1)
  95 #define IPU_FIELD_CRE           IPU_CPMEM_WORD(1, 149, 1)
  96 #define IPU_FIELD_DEC_SEL2      IPU_CPMEM_WORD(1, 150, 1)
  97
  98 static inline struct ipu_ch_param __iomem *
  99 ipu_get_cpmem(struct ipuv3_channel *ch)
 100 {
 101         struct ipu_cpmem *cpmem = ch->ipu->cpmem_priv;
 102
 103         return cpmem->base + ch->num;
 104 }
 105
 106 static void ipu_ch_param_write_field(struct ipuv3_channel *ch, u32 wbs, u32 v)
 107 {
 108         struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
 109         u32 bit = (wbs >> 8) % 160;
 110         u32 size = wbs & 0xff;
 111         u32 word = (wbs >> 8) / 160;
 112         u32 i = bit / 32;
 113         u32 ofs = bit % 32;
 114         u32 mask = (1 << size) - 1;
 115         u32 val;
 116
 117         pr_debug("%s %d %d %d\n", __func__, word, bit , size);
 118
 119         val = readl(&base->word[word].data[i]);
 120         val &= ~(mask << ofs);
 121         val |= v << ofs;
 122         writel(val, &base->word[word].data[i]);
 123
 124         if ((bit + size - 1) / 32 > i) {
 125                 val = readl(&base->word[word].data[i + 1]);
 126                 val &= ~(mask >> (ofs ? (32 - ofs) : 0));
 127                 val |= v >> (ofs ? (32 - ofs) : 0);
 128                 writel(val, &base->word[word].data[i + 1]);
 129         }
 130 }
 131
 132 static u32 ipu_ch_param_read_field(struct ipuv3_channel *ch, u32 wbs)
 133 {
 134         struct ipu_ch_param __iomem *base = ipu_get_cpmem(ch);
 135         u32 bit = (wbs >> 8) % 160;
 136         u32 size = wbs & 0xff;
 137         u32 word = (wbs >> 8) / 160;
 138         u32 i = bit / 32;
 139         u32 ofs = bit % 32;
 140         u32 mask = (1 << size) - 1;
 141         u32 val = 0;
 142
 143         pr_debug("%s %d %d %d\n", __func__, word, bit , size);
 144
 145         val = (readl(&base->word[word].data[i]) >> ofs) & mask;
 146
 147         if ((bit + size - 1) / 32 > i) {
 148                 u32 tmp;
 149
 150                 tmp = readl(&base->word[word].data[i + 1]);
 151                 tmp &= mask >> (ofs ? (32 - ofs) : 0);
 152                 val |= tmp << (ofs ? (32 - ofs) : 0);
 153         }
 154
 155         return val;
 156 }
 157
 158 /*
 159  * The V4L2 spec defines packed RGB formats in memory byte order, which from
 160  * point of view of the IPU corresponds to little-endian words with the first
 161  * component in the least significant bits.
 162  * The DRM pixel formats and IPU internal representation are ordered the other
 163  * way around, with the first named component ordered at the most significant
 164  * bits. Further, V4L2 formats are not well defined:
 165  *     https://linuxtv.org/downloads/v4l-dvb-apis/packed-rgb.html
 166  * We choose the interpretation which matches GStreamer behavior.
 167  */
 168 static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat)
 169 {
 170         switch (pixelformat) {
 171         case V4L2_PIX_FMT_RGB565:
 172                 /*
 173                  * Here we choose the 'corrected' interpretation of RGBP, a
 174                  * little-endian 16-bit word with the red component at the most
 175                  * significant bits:
 176                  * g[2:0]b[4:0] r[4:0]g[5:3] <=> [16:0] R:G:B
 177                  */
 178                 return DRM_FORMAT_RGB565;
 179         case V4L2_PIX_FMT_BGR24:
 180                 /* B G R <=> [24:0] R:G:B */
 181                 return DRM_FORMAT_RGB888;
 182         case V4L2_PIX_FMT_RGB24:
 183                 /* R G B <=> [24:0] B:G:R */
 184                 return DRM_FORMAT_BGR888;
 185         case V4L2_PIX_FMT_BGR32:
 186                 /* B G R A <=> [32:0] A:B:G:R */
 187                 return DRM_FORMAT_XRGB8888;
 188         case V4L2_PIX_FMT_RGB32:
 189                 /* R G B A <=> [32:0] A:B:G:R */
 190                 return DRM_FORMAT_XBGR8888;
 191         case V4L2_PIX_FMT_UYVY:
 192                 return DRM_FORMAT_UYVY;
 193         case V4L2_PIX_FMT_YUYV:
 194                 return DRM_FORMAT_YUYV;
 195         case V4L2_PIX_FMT_YUV420:
 196                 return DRM_FORMAT_YUV420;
 197         case V4L2_PIX_FMT_YUV422P:
 198                 return DRM_FORMAT_YUV422;
 199         case V4L2_PIX_FMT_YVU420:
 200                 return DRM_FORMAT_YVU420;
 201         case V4L2_PIX_FMT_NV12:
 202                 return DRM_FORMAT_NV12;
 203         case V4L2_PIX_FMT_NV16:
 204                 return DRM_FORMAT_NV16;
 205         }
 206
 207         return -EINVAL;
 208 }
 209
 210 void ipu_cpmem_zero(struct ipuv3_channel *ch)
 211 {
 212         struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch);
 213         void __iomem *base = p;
 214         int i;
 215
 216         for (i = 0; i < sizeof(*p) / sizeof(u32); i++)
 217                 writel(0, base + i * sizeof(u32));
 218 }
 219 EXPORT_SYMBOL_GPL(ipu_cpmem_zero);
 220
 221 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres)
 222 {
 223         ipu_ch_param_write_field(ch, IPU_FIELD_FW, xres - 1);
 224         ipu_ch_param_write_field(ch, IPU_FIELD_FH, yres - 1);
 225 }
 226 EXPORT_SYMBOL_GPL(ipu_cpmem_set_resolution);
 227
 228 void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch)
 229 {
 230         ipu_ch_param_write_field(ch, IPU_FIELD_RDRW, 1);
 231 }
 232 EXPORT_SYMBOL_GPL(ipu_cpmem_skip_odd_chroma_rows);
 233
 234 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride)
 235 {
 236         ipu_ch_param_write_field(ch, IPU_FIELD_SLY, stride - 1);
 237 }
 238 EXPORT_SYMBOL_GPL(ipu_cpmem_set_stride);
 239
 240 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch)
 241 {
 242         struct ipu_soc *ipu = ch->ipu;
 243         u32 val;
 244
 245         if (ipu->ipu_type == IPUV3EX)
 246                 ipu_ch_param_write_field(ch, IPU_FIELD_ID, 1);
 247
 248         val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(ch->num));
 249         val |= 1 << (ch->num % 32);
 250         ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(ch->num));
 251 };
 252 EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority);
 253
 254 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf)
 255 {
 256         if (bufnum)
 257                 ipu_ch_param_write_field(ch, IPU_FIELD_EBA1, buf >> 3);
 258         else
 259                 ipu_ch_param_write_field(ch, IPU_FIELD_EBA0, buf >> 3);
 260 }
 261 EXPORT_SYMBOL_GPL(ipu_cpmem_set_buffer);
 262
 263 void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off)
 264 {
 265         ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_off / 8);
 266         ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_off / 8);
 267 }
 268 EXPORT_SYMBOL_GPL(ipu_cpmem_set_uv_offset);
 269
 270 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride)
 271 {
 272         u32 ilo, sly;
 273
 274         if (stride < 0) {
 275                 stride = -stride;
 276                 ilo = 0x100000 - (stride / 8);
 277         } else {
 278                 ilo = stride / 8;
 279         }
 280
 281         sly = (stride * 2) - 1;
 282
 283         ipu_ch_param_write_field(ch, IPU_FIELD_SO, 1);
 284         ipu_ch_param_write_field(ch, IPU_FIELD_ILO, ilo);
 285         ipu_ch_param_write_field(ch, IPU_FIELD_SLY, sly);
 286 };
 287 EXPORT_SYMBOL_GPL(ipu_cpmem_interlaced_scan);
 288
 289 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id)
 290 {
 291         id &= 0x3;
 292         ipu_ch_param_write_field(ch, IPU_FIELD_ID, id);
 293 }
 294 EXPORT_SYMBOL_GPL(ipu_cpmem_set_axi_id);
 295
 296 int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch)
 297 {
 298         return ipu_ch_param_read_field(ch, IPU_FIELD_NPB) + 1;
 299 }
 300 EXPORT_SYMBOL_GPL(ipu_cpmem_get_burstsize);
 301
 302 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize)
 303 {
 304         ipu_ch_param_write_field(ch, IPU_FIELD_NPB, burstsize - 1);
 305 };
 306 EXPORT_SYMBOL_GPL(ipu_cpmem_set_burstsize);
 307
 308 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch)
 309 {
 310         ipu_ch_param_write_field(ch, IPU_FIELD_BM, 1);
 311 }
 312 EXPORT_SYMBOL_GPL(ipu_cpmem_set_block_mode);
 313
 314 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
 315                             enum ipu_rotate_mode rot)
 316 {
 317         u32 temp_rot = bitrev8(rot) >> 5;
 318
 319         ipu_ch_param_write_field(ch, IPU_FIELD_ROT_HF_VF, temp_rot);
 320 }
 321 EXPORT_SYMBOL_GPL(ipu_cpmem_set_rotation);
 322
 323 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
 324                              const struct ipu_rgb *rgb)
 325 {
 326         int bpp = 0, npb = 0, ro, go, bo, to;
 327
 328         ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset;
 329         go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset;
 330         bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset;
 331         to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset;
 332
 333         ipu_ch_param_write_field(ch, IPU_FIELD_WID0, rgb->red.length - 1);
 334         ipu_ch_param_write_field(ch, IPU_FIELD_OFS0, ro);
 335         ipu_ch_param_write_field(ch, IPU_FIELD_WID1, rgb->green.length - 1);
 336         ipu_ch_param_write_field(ch, IPU_FIELD_OFS1, go);
 337         ipu_ch_param_write_field(ch, IPU_FIELD_WID2, rgb->blue.length - 1);
 338         ipu_ch_param_write_field(ch, IPU_FIELD_OFS2, bo);
 339
 340         if (rgb->transp.length) {
 341                 ipu_ch_param_write_field(ch, IPU_FIELD_WID3,
 342                                 rgb->transp.length - 1);
 343                 ipu_ch_param_write_field(ch, IPU_FIELD_OFS3, to);
 344         } else {
 345                 ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7);
 346                 ipu_ch_param_write_field(ch, IPU_FIELD_OFS3,
 347                                 rgb->bits_per_pixel);
 348         }
 349
 350         switch (rgb->bits_per_pixel) {
 351         case 32:
 352                 bpp = 0;
 353                 npb = 15;
 354                 break;
 355         case 24:
 356                 bpp = 1;
 357                 npb = 19;
 358                 break;
 359         case 16:
 360                 bpp = 3;
 361                 npb = 31;
 362                 break;
 363         case 8:
 364                 bpp = 5;
 365                 npb = 63;
 366                 break;
 367         default:
 368                 return -EINVAL;
 369         }
 370         ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
 371         ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
 372         ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 7); /* rgb mode */
 373
 374         return 0;
 375 }
 376 EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb);
 377
 378 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width)
 379 {
 380         int bpp = 0, npb = 0;
 381
 382         switch (width) {
 383         case 32:
 384                 bpp = 0;
 385                 npb = 15;
 386                 break;
 387         case 24:
 388                 bpp = 1;
 389                 npb = 19;
 390                 break;
 391         case 16:
 392                 bpp = 3;
 393                 npb = 31;
 394                 break;
 395         case 8:
 396                 bpp = 5;
 397                 npb = 63;
 398                 break;
 399         default:
 400                 return -EINVAL;
 401         }
 402
 403         ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp);
 404         ipu_ch_param_write_field(ch, IPU_FIELD_NPB, npb);
 405         ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 6); /* raw mode */
 406
 407         return 0;
 408 }
 409 EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough);
 410
 411 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format)
 412 {
 413         switch (pixel_format) {
 414         case V4L2_PIX_FMT_UYVY:
 415                 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
 416                 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);/* pix fmt */
 417                 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
 418                 break;
 419         case V4L2_PIX_FMT_YUYV:
 420                 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3); /* bits/pixel */
 421                 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);/* pix fmt */
 422                 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);/* burst size */
 423                 break;
 424         }
 425 }
 426 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved);
 427
 428 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
 429                                    unsigned int uv_stride,
 430                                    unsigned int u_offset, unsigned int v_offset)
 431 {
 432         ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, uv_stride - 1);
 433         ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
 434         ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8);
 435 }
 436 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full);
 437
 438 static const struct ipu_rgb def_xrgb_32 = {
 439         .red    = { .offset = 16, .length = 8, },
 440         .green  = { .offset =  8, .length = 8, },
 441         .blue   = { .offset =  0, .length = 8, },
 442         .transp = { .offset = 24, .length = 8, },
 443         .bits_per_pixel = 32,
 444 };
 445
 446 static const struct ipu_rgb def_xbgr_32 = {
 447         .red    = { .offset =  0, .length = 8, },
 448         .green  = { .offset =  8, .length = 8, },
 449         .blue   = { .offset = 16, .length = 8, },
 450         .transp = { .offset = 24, .length = 8, },
 451         .bits_per_pixel = 32,
 452 };
 453
 454 static const struct ipu_rgb def_rgbx_32 = {
 455         .red    = { .offset = 24, .length = 8, },
 456         .green  = { .offset = 16, .length = 8, },
 457         .blue   = { .offset =  8, .length = 8, },
 458         .transp = { .offset =  0, .length = 8, },
 459         .bits_per_pixel = 32,
 460 };
 461
 462 static const struct ipu_rgb def_bgrx_32 = {
 463         .red    = { .offset =  8, .length = 8, },
 464         .green  = { .offset = 16, .length = 8, },
 465         .blue   = { .offset = 24, .length = 8, },
 466         .transp = { .offset =  0, .length = 8, },
 467         .bits_per_pixel = 32,
 468 };
 469
 470 static const struct ipu_rgb def_rgb_24 = {
 471         .red    = { .offset = 16, .length = 8, },
 472         .green  = { .offset =  8, .length = 8, },
 473         .blue   = { .offset =  0, .length = 8, },
 474         .transp = { .offset =  0, .length = 0, },
 475         .bits_per_pixel = 24,
 476 };
 477
 478 static const struct ipu_rgb def_bgr_24 = {
 479         .red    = { .offset =  0, .length = 8, },
 480         .green  = { .offset =  8, .length = 8, },
 481         .blue   = { .offset = 16, .length = 8, },
 482         .transp = { .offset =  0, .length = 0, },
 483         .bits_per_pixel = 24,
 484 };
 485
 486 static const struct ipu_rgb def_rgb_16 = {
 487         .red    = { .offset = 11, .length = 5, },
 488         .green  = { .offset =  5, .length = 6, },
 489         .blue   = { .offset =  0, .length = 5, },
 490         .transp = { .offset =  0, .length = 0, },
 491         .bits_per_pixel = 16,
 492 };
 493
 494 static const struct ipu_rgb def_bgr_16 = {
 495         .red    = { .offset =  0, .length = 5, },
 496         .green  = { .offset =  5, .length = 6, },
 497         .blue   = { .offset = 11, .length = 5, },
 498         .transp = { .offset =  0, .length = 0, },
 499         .bits_per_pixel = 16,
 500 };
 501
 502 static const struct ipu_rgb def_argb_16 = {
 503         .red    = { .offset = 10, .length = 5, },
 504         .green  = { .offset =  5, .length = 5, },
 505         .blue   = { .offset =  0, .length = 5, },
 506         .transp = { .offset = 15, .length = 1, },
 507         .bits_per_pixel = 16,
 508 };
 509
 510 static const struct ipu_rgb def_argb_16_4444 = {
 511         .red    = { .offset =  8, .length = 4, },
 512         .green  = { .offset =  4, .length = 4, },
 513         .blue   = { .offset =  0, .length = 4, },
 514         .transp = { .offset = 12, .length = 4, },
 515         .bits_per_pixel = 16,
 516 };
 517
 518 static const struct ipu_rgb def_abgr_16 = {
 519         .red    = { .offset =  0, .length = 5, },
 520         .green  = { .offset =  5, .length = 5, },
 521         .blue   = { .offset = 10, .length = 5, },
 522         .transp = { .offset = 15, .length = 1, },
 523         .bits_per_pixel = 16,
 524 };
 525
 526 static const struct ipu_rgb def_rgba_16 = {
 527         .red    = { .offset = 11, .length = 5, },
 528         .green  = { .offset =  6, .length = 5, },
 529         .blue   = { .offset =  1, .length = 5, },
 530         .transp = { .offset =  0, .length = 1, },
 531         .bits_per_pixel = 16,
 532 };
 533
 534 static const struct ipu_rgb def_bgra_16 = {
 535         .red    = { .offset =  1, .length = 5, },
 536         .green  = { .offset =  6, .length = 5, },
 537         .blue   = { .offset = 11, .length = 5, },
 538         .transp = { .offset =  0, .length = 1, },
 539         .bits_per_pixel = 16,
 540 };
 541
 542 #define Y_OFFSET(pix, x, y)     ((x) + pix->width * (y))
 543 #define U_OFFSET(pix, x, y)     ((pix->width * pix->height) +           \
 544                                  (pix->width * (y) / 4) + (x) / 2)
 545 #define V_OFFSET(pix, x, y)     ((pix->width * pix->height) +           \
 546                                  (pix->width * pix->height / 4) +       \
 547                                  (pix->width * (y) / 4) + (x) / 2)
 548 #define U2_OFFSET(pix, x, y)    ((pix->width * pix->height) +           \
 549                                  (pix->width * (y) / 2) + (x) / 2)
 550 #define V2_OFFSET(pix, x, y)    ((pix->width * pix->height) +           \
 551                                  (pix->width * pix->height / 2) +       \
 552                                  (pix->width * (y) / 2) + (x) / 2)
 553 #define UV_OFFSET(pix, x, y)    ((pix->width * pix->height) +   \
 554                                  (pix->width * (y) / 2) + (x))
 555 #define UV2_OFFSET(pix, x, y)   ((pix->width * pix->height) +   \
 556                                  (pix->width * y) + (x))
 557
 558 #define NUM_ALPHA_CHANNELS      7
 559
 560 /* See Table 37-12. Alpha channels mapping. */
 561 static int ipu_channel_albm(int ch_num)
 562 {
 563         switch (ch_num) {
 564         case IPUV3_CHANNEL_G_MEM_IC_PRP_VF:     return 0;
 565         case IPUV3_CHANNEL_G_MEM_IC_PP:         return 1;
 566         case IPUV3_CHANNEL_MEM_FG_SYNC:         return 2;
 567         case IPUV3_CHANNEL_MEM_FG_ASYNC:        return 3;
 568         case IPUV3_CHANNEL_MEM_BG_SYNC:         return 4;
 569         case IPUV3_CHANNEL_MEM_BG_ASYNC:        return 5;
 570         case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB: return 6;
 571         default:
 572                 return -EINVAL;
 573         }
 574 }
 575
 576 static void ipu_cpmem_set_separate_alpha(struct ipuv3_channel *ch)
 577 {
 578         struct ipu_soc *ipu = ch->ipu;
 579         int albm;
 580         u32 val;
 581
 582         albm = ipu_channel_albm(ch->num);
 583         if (albm < 0)
 584                 return;
 585
 586         ipu_ch_param_write_field(ch, IPU_FIELD_ALU, 1);
 587         ipu_ch_param_write_field(ch, IPU_FIELD_ALBM, albm);
 588         ipu_ch_param_write_field(ch, IPU_FIELD_CRE, 1);
 589
 590         val = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
 591         val |= BIT(ch->num);
 592         ipu_idmac_write(ipu, val, IDMAC_SEP_ALPHA);
 593 }
 594
 595 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc)
 596 {
 597         switch (drm_fourcc) {
 598         case DRM_FORMAT_YUV420:
 599         case DRM_FORMAT_YVU420:
 600                 /* pix format */
 601                 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 2);
 602                 /* burst size */
 603                 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
 604                 break;
 605         case DRM_FORMAT_YUV422:
 606         case DRM_FORMAT_YVU422:
 607                 /* pix format */
 608                 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 1);
 609                 /* burst size */
 610                 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
 611                 break;
 612         case DRM_FORMAT_YUV444:
 613         case DRM_FORMAT_YVU444:
 614                 /* pix format */
 615                 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0);
 616                 /* burst size */
 617                 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
 618                 break;
 619         case DRM_FORMAT_NV12:
 620                 /* pix format */
 621                 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 4);
 622                 /* burst size */
 623                 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
 624                 break;
 625         case DRM_FORMAT_NV16:
 626                 /* pix format */
 627                 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 3);
 628                 /* burst size */
 629                 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
 630                 break;
 631         case DRM_FORMAT_UYVY:
 632                 /* bits/pixel */
 633                 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
 634                 /* pix format */
 635                 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0xA);
 636                 /* burst size */
 637                 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
 638                 break;
 639         case DRM_FORMAT_YUYV:
 640                 /* bits/pixel */
 641                 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, 3);
 642                 /* pix format */
 643                 ipu_ch_param_write_field(ch, IPU_FIELD_PFS, 0x8);
 644                 /* burst size */
 645                 ipu_ch_param_write_field(ch, IPU_FIELD_NPB, 31);
 646                 break;
 647         case DRM_FORMAT_ABGR8888:
 648         case DRM_FORMAT_XBGR8888:
 649                 ipu_cpmem_set_format_rgb(ch, &def_xbgr_32);
 650                 break;
 651         case DRM_FORMAT_ARGB8888:
 652         case DRM_FORMAT_XRGB8888:
 653                 ipu_cpmem_set_format_rgb(ch, &def_xrgb_32);
 654                 break;
 655         case DRM_FORMAT_RGBA8888:
 656         case DRM_FORMAT_RGBX8888:
 657         case DRM_FORMAT_RGBX8888_A8:
 658                 ipu_cpmem_set_format_rgb(ch, &def_rgbx_32);
 659                 break;
 660         case DRM_FORMAT_BGRA8888:
 661         case DRM_FORMAT_BGRX8888:
 662         case DRM_FORMAT_BGRX8888_A8:
 663                 ipu_cpmem_set_format_rgb(ch, &def_bgrx_32);
 664                 break;
 665         case DRM_FORMAT_BGR888:
 666         case DRM_FORMAT_BGR888_A8:
 667                 ipu_cpmem_set_format_rgb(ch, &def_bgr_24);
 668                 break;
 669         case DRM_FORMAT_RGB888:
 670         case DRM_FORMAT_RGB888_A8:
 671                 ipu_cpmem_set_format_rgb(ch, &def_rgb_24);
 672                 break;
 673         case DRM_FORMAT_RGB565:
 674         case DRM_FORMAT_RGB565_A8:
 675                 ipu_cpmem_set_format_rgb(ch, &def_rgb_16);
 676                 break;
 677         case DRM_FORMAT_BGR565:
 678         case DRM_FORMAT_BGR565_A8:
 679                 ipu_cpmem_set_format_rgb(ch, &def_bgr_16);
 680                 break;
 681         case DRM_FORMAT_ARGB1555:
 682                 ipu_cpmem_set_format_rgb(ch, &def_argb_16);
 683                 break;
 684         case DRM_FORMAT_ABGR1555:
 685                 ipu_cpmem_set_format_rgb(ch, &def_abgr_16);
 686                 break;
 687         case DRM_FORMAT_RGBA5551:
 688                 ipu_cpmem_set_format_rgb(ch, &def_rgba_16);
 689                 break;
 690         case DRM_FORMAT_BGRA5551:
 691                 ipu_cpmem_set_format_rgb(ch, &def_bgra_16);
 692                 break;
 693         case DRM_FORMAT_ARGB4444:
 694                 ipu_cpmem_set_format_rgb(ch, &def_argb_16_4444);
 695                 break;
 696         default:
 697                 return -EINVAL;
 698         }
 699
 700         switch (drm_fourcc) {
 701         case DRM_FORMAT_RGB565_A8:
 702         case DRM_FORMAT_BGR565_A8:
 703         case DRM_FORMAT_RGB888_A8:
 704         case DRM_FORMAT_BGR888_A8:
 705         case DRM_FORMAT_RGBX8888_A8:
 706         case DRM_FORMAT_BGRX8888_A8:
 707                 ipu_ch_param_write_field(ch, IPU_FIELD_WID3, 7);
 708                 ipu_cpmem_set_separate_alpha(ch);
 709                 break;
 710         default:
 711                 break;
 712         }
 713
 714         return 0;
 715 }
 716 EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt);
 717
 718 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
 719 {
 720         struct v4l2_pix_format *pix = &image->pix;
 721         int offset, u_offset, v_offset;
 722         int ret = 0;
 723
 724         pr_debug("%s: resolution: %dx%d stride: %d\n",
 725                  __func__, pix->width, pix->height,
 726                  pix->bytesperline);
 727
 728         ipu_cpmem_set_resolution(ch, image->rect.width, image->rect.height);
 729         ipu_cpmem_set_stride(ch, pix->bytesperline);
 730
 731         ipu_cpmem_set_fmt(ch, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat));
 732
 733         switch (pix->pixelformat) {
 734         case V4L2_PIX_FMT_YUV420:
 735                 offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
 736                 u_offset = U_OFFSET(pix, image->rect.left,
 737                                     image->rect.top) - offset;
 738                 v_offset = V_OFFSET(pix, image->rect.left,
 739                                     image->rect.top) - offset;
 740
 741                 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2,
 742                                               u_offset, v_offset);
 743                 break;
 744         case V4L2_PIX_FMT_YVU420:
 745                 offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
 746                 u_offset = U_OFFSET(pix, image->rect.left,
 747                                     image->rect.top) - offset;
 748                 v_offset = V_OFFSET(pix, image->rect.left,
 749                                     image->rect.top) - offset;
 750
 751                 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2,
 752                                               v_offset, u_offset);
 753                 break;
 754         case V4L2_PIX_FMT_YUV422P:
 755                 offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
 756                 u_offset = U2_OFFSET(pix, image->rect.left,
 757                                      image->rect.top) - offset;
 758                 v_offset = V2_OFFSET(pix, image->rect.left,
 759                                      image->rect.top) - offset;
 760
 761                 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2,
 762                                               u_offset, v_offset);
 763                 break;
 764         case V4L2_PIX_FMT_NV12:
 765                 offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
 766                 u_offset = UV_OFFSET(pix, image->rect.left,
 767                                      image->rect.top) - offset;
 768                 v_offset = 0;
 769
 770                 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline,
 771                                               u_offset, v_offset);
 772                 break;
 773         case V4L2_PIX_FMT_NV16:
 774                 offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
 775                 u_offset = UV2_OFFSET(pix, image->rect.left,
 776                                       image->rect.top) - offset;
 777                 v_offset = 0;
 778
 779                 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline,
 780                                               u_offset, v_offset);
 781                 break;
 782         case V4L2_PIX_FMT_UYVY:
 783         case V4L2_PIX_FMT_YUYV:
 784         case V4L2_PIX_FMT_RGB565:
 785                 offset = image->rect.left * 2 +
 786                         image->rect.top * pix->bytesperline;
 787                 break;
 788         case V4L2_PIX_FMT_RGB32:
 789         case V4L2_PIX_FMT_BGR32:
 790                 offset = image->rect.left * 4 +
 791                         image->rect.top * pix->bytesperline;
 792                 break;
 793         case V4L2_PIX_FMT_RGB24:
 794         case V4L2_PIX_FMT_BGR24:
 795                 offset = image->rect.left * 3 +
 796                         image->rect.top * pix->bytesperline;
 797                 break;
 798         case V4L2_PIX_FMT_SBGGR8:
 799         case V4L2_PIX_FMT_SGBRG8:
 800         case V4L2_PIX_FMT_SGRBG8:
 801         case V4L2_PIX_FMT_SRGGB8:
 802         case V4L2_PIX_FMT_GREY:
 803                 offset = image->rect.left + image->rect.top * pix->bytesperline;
 804                 break;
 805         case V4L2_PIX_FMT_SBGGR16:
 806         case V4L2_PIX_FMT_SGBRG16:
 807         case V4L2_PIX_FMT_SGRBG16:
 808         case V4L2_PIX_FMT_SRGGB16:
 809         case V4L2_PIX_FMT_Y16:
 810                 offset = image->rect.left * 2 +
 811                          image->rect.top * pix->bytesperline;
 812                 break;
 813         default:
 814                 /* This should not happen */
 815                 WARN_ON(1);
 816                 offset = 0;
 817                 ret = -EINVAL;
 818         }
 819
 820         ipu_cpmem_set_buffer(ch, 0, image->phys0 + offset);
 821         ipu_cpmem_set_buffer(ch, 1, image->phys1 + offset);
 822
 823         return ret;
 824 }
 825 EXPORT_SYMBOL_GPL(ipu_cpmem_set_image);
 826
 827 void ipu_cpmem_dump(struct ipuv3_channel *ch)
 828 {
 829         struct ipu_ch_param __iomem *p = ipu_get_cpmem(ch);
 830         struct ipu_soc *ipu = ch->ipu;
 831         int chno = ch->num;
 832
 833         dev_dbg(ipu->dev, "ch %d word 0 - %08X %08X %08X %08X %08X\n", chno,
 834                 readl(&p->word[0].data[0]),
 835                 readl(&p->word[0].data[1]),
 836                 readl(&p->word[0].data[2]),
 837                 readl(&p->word[0].data[3]),
 838                 readl(&p->word[0].data[4]));
 839         dev_dbg(ipu->dev, "ch %d word 1 - %08X %08X %08X %08X %08X\n", chno,
 840                 readl(&p->word[1].data[0]),
 841                 readl(&p->word[1].data[1]),
 842                 readl(&p->word[1].data[2]),
 843                 readl(&p->word[1].data[3]),
 844                 readl(&p->word[1].data[4]));
 845         dev_dbg(ipu->dev, "PFS 0x%x, ",
 846                  ipu_ch_param_read_field(ch, IPU_FIELD_PFS));
 847         dev_dbg(ipu->dev, "BPP 0x%x, ",
 848                 ipu_ch_param_read_field(ch, IPU_FIELD_BPP));
 849         dev_dbg(ipu->dev, "NPB 0x%x\n",
 850                  ipu_ch_param_read_field(ch, IPU_FIELD_NPB));
 851
 852         dev_dbg(ipu->dev, "FW %d, ",
 853                  ipu_ch_param_read_field(ch, IPU_FIELD_FW));
 854         dev_dbg(ipu->dev, "FH %d, ",
 855                  ipu_ch_param_read_field(ch, IPU_FIELD_FH));
 856         dev_dbg(ipu->dev, "EBA0 0x%x\n",
 857                  ipu_ch_param_read_field(ch, IPU_FIELD_EBA0) << 3);
 858         dev_dbg(ipu->dev, "EBA1 0x%x\n",
 859                  ipu_ch_param_read_field(ch, IPU_FIELD_EBA1) << 3);
 860         dev_dbg(ipu->dev, "Stride %d\n",
 861                  ipu_ch_param_read_field(ch, IPU_FIELD_SL));
 862         dev_dbg(ipu->dev, "scan_order %d\n",
 863                  ipu_ch_param_read_field(ch, IPU_FIELD_SO));
 864         dev_dbg(ipu->dev, "uv_stride %d\n",
 865                  ipu_ch_param_read_field(ch, IPU_FIELD_SLUV));
 866         dev_dbg(ipu->dev, "u_offset 0x%x\n",
 867                  ipu_ch_param_read_field(ch, IPU_FIELD_UBO) << 3);
 868         dev_dbg(ipu->dev, "v_offset 0x%x\n",
 869                  ipu_ch_param_read_field(ch, IPU_FIELD_VBO) << 3);
 870
 871         dev_dbg(ipu->dev, "Width0 %d+1, ",
 872                  ipu_ch_param_read_field(ch, IPU_FIELD_WID0));
 873         dev_dbg(ipu->dev, "Width1 %d+1, ",
 874                  ipu_ch_param_read_field(ch, IPU_FIELD_WID1));
 875         dev_dbg(ipu->dev, "Width2 %d+1, ",
 876                  ipu_ch_param_read_field(ch, IPU_FIELD_WID2));
 877         dev_dbg(ipu->dev, "Width3 %d+1, ",
 878                  ipu_ch_param_read_field(ch, IPU_FIELD_WID3));
 879         dev_dbg(ipu->dev, "Offset0 %d, ",
 880                  ipu_ch_param_read_field(ch, IPU_FIELD_OFS0));
 881         dev_dbg(ipu->dev, "Offset1 %d, ",
 882                  ipu_ch_param_read_field(ch, IPU_FIELD_OFS1));
 883         dev_dbg(ipu->dev, "Offset2 %d, ",
 884                  ipu_ch_param_read_field(ch, IPU_FIELD_OFS2));
 885         dev_dbg(ipu->dev, "Offset3 %d\n",
 886                  ipu_ch_param_read_field(ch, IPU_FIELD_OFS3));
 887 }
 888 EXPORT_SYMBOL_GPL(ipu_cpmem_dump);
 889
 890 int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base)
 891 {
 892         struct ipu_cpmem *cpmem;
 893
 894         cpmem = devm_kzalloc(dev, sizeof(*cpmem), GFP_KERNEL);
 895         if (!cpmem)
 896                 return -ENOMEM;
 897
 898         ipu->cpmem_priv = cpmem;
 899
 900         spin_lock_init(&cpmem->lock);
 901         cpmem->base = devm_ioremap(dev, base, SZ_128K);
 902         if (!cpmem->base)
 903                 return -ENOMEM;
 904
 905         dev_dbg(dev, "CPMEM base: 0x%08lx remapped to %p\n",
 906                 base, cpmem->base);
 907         cpmem->ipu = ipu;
 908
 909         return 0;
 910 }
 911
 912 void ipu_cpmem_exit(struct ipu_soc *ipu)
 913 {
 914 }