drivers/gpu/ipu-v3/ipu-common.c

   1 /*
   2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
   3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/export.h>
  17 #include <linux/types.h>
  18 #include <linux/reset.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/err.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/delay.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/clk.h>
  26 #include <linux/list.h>
  27 #include <linux/irq.h>
  28 #include <linux/irqchip/chained_irq.h>
  29 #include <linux/irqdomain.h>
  30 #include <linux/of_device.h>
  31 #include <linux/of_graph.h>
  32
  33 #include <drm/drm_fourcc.h>
  34
  35 #include <video/imx-ipu-v3.h>
  36 #include "ipu-prv.h"
  37
  38 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
  39 {
  40         return readl(ipu->cm_reg + offset);
  41 }
  42
  43 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
  44 {
  45         writel(value, ipu->cm_reg + offset);
  46 }
  47
  48 int ipu_get_num(struct ipu_soc *ipu)
  49 {
  50         return ipu->id;
  51 }
  52 EXPORT_SYMBOL_GPL(ipu_get_num);
  53
  54 void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync)
  55 {
  56         u32 val;
  57
  58         val = ipu_cm_read(ipu, IPU_SRM_PRI2);
  59         val &= ~DP_S_SRM_MODE_MASK;
  60         val |= sync ? DP_S_SRM_MODE_NEXT_FRAME :
  61                       DP_S_SRM_MODE_NOW;
  62         ipu_cm_write(ipu, val, IPU_SRM_PRI2);
  63 }
  64 EXPORT_SYMBOL_GPL(ipu_srm_dp_update);
  65
  66 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
  67 {
  68         switch (drm_fourcc) {
  69         case DRM_FORMAT_ARGB1555:
  70         case DRM_FORMAT_ABGR1555:
  71         case DRM_FORMAT_RGBA5551:
  72         case DRM_FORMAT_BGRA5551:
  73         case DRM_FORMAT_RGB565:
  74         case DRM_FORMAT_BGR565:
  75         case DRM_FORMAT_RGB888:
  76         case DRM_FORMAT_BGR888:
  77         case DRM_FORMAT_ARGB4444:
  78         case DRM_FORMAT_XRGB8888:
  79         case DRM_FORMAT_XBGR8888:
  80         case DRM_FORMAT_RGBX8888:
  81         case DRM_FORMAT_BGRX8888:
  82         case DRM_FORMAT_ARGB8888:
  83         case DRM_FORMAT_ABGR8888:
  84         case DRM_FORMAT_RGBA8888:
  85         case DRM_FORMAT_BGRA8888:
  86                 return IPUV3_COLORSPACE_RGB;
  87         case DRM_FORMAT_YUYV:
  88         case DRM_FORMAT_UYVY:
  89         case DRM_FORMAT_YUV420:
  90         case DRM_FORMAT_YVU420:
  91         case DRM_FORMAT_YUV422:
  92         case DRM_FORMAT_YVU422:
  93         case DRM_FORMAT_YUV444:
  94         case DRM_FORMAT_YVU444:
  95         case DRM_FORMAT_NV12:
  96         case DRM_FORMAT_NV21:
  97         case DRM_FORMAT_NV16:
  98         case DRM_FORMAT_NV61:
  99                 return IPUV3_COLORSPACE_YUV;
 100         default:
 101                 return IPUV3_COLORSPACE_UNKNOWN;
 102         }
 103 }
 104 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
 105
 106 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
 107 {
 108         switch (pixelformat) {
 109         case V4L2_PIX_FMT_YUV420:
 110         case V4L2_PIX_FMT_YVU420:
 111         case V4L2_PIX_FMT_YUV422P:
 112         case V4L2_PIX_FMT_UYVY:
 113         case V4L2_PIX_FMT_YUYV:
 114         case V4L2_PIX_FMT_NV12:
 115         case V4L2_PIX_FMT_NV21:
 116         case V4L2_PIX_FMT_NV16:
 117         case V4L2_PIX_FMT_NV61:
 118                 return IPUV3_COLORSPACE_YUV;
 119         case V4L2_PIX_FMT_RGB32:
 120         case V4L2_PIX_FMT_BGR32:
 121         case V4L2_PIX_FMT_RGB24:
 122         case V4L2_PIX_FMT_BGR24:
 123         case V4L2_PIX_FMT_RGB565:
 124                 return IPUV3_COLORSPACE_RGB;
 125         default:
 126                 return IPUV3_COLORSPACE_UNKNOWN;
 127         }
 128 }
 129 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
 130
 131 bool ipu_pixelformat_is_planar(u32 pixelformat)
 132 {
 133         switch (pixelformat) {
 134         case V4L2_PIX_FMT_YUV420:
 135         case V4L2_PIX_FMT_YVU420:
 136         case V4L2_PIX_FMT_YUV422P:
 137         case V4L2_PIX_FMT_NV12:
 138         case V4L2_PIX_FMT_NV21:
 139         case V4L2_PIX_FMT_NV16:
 140         case V4L2_PIX_FMT_NV61:
 141                 return true;
 142         }
 143
 144         return false;
 145 }
 146 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
 147
 148 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
 149 {
 150         switch (mbus_code & 0xf000) {
 151         case 0x1000:
 152                 return IPUV3_COLORSPACE_RGB;
 153         case 0x2000:
 154                 return IPUV3_COLORSPACE_YUV;
 155         default:
 156                 return IPUV3_COLORSPACE_UNKNOWN;
 157         }
 158 }
 159 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
 160
 161 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
 162 {
 163         switch (pixelformat) {
 164         case V4L2_PIX_FMT_YUV420:
 165         case V4L2_PIX_FMT_YVU420:
 166         case V4L2_PIX_FMT_YUV422P:
 167         case V4L2_PIX_FMT_NV12:
 168         case V4L2_PIX_FMT_NV21:
 169         case V4L2_PIX_FMT_NV16:
 170         case V4L2_PIX_FMT_NV61:
 171                 /*
 172                  * for the planar YUV formats, the stride passed to
 173                  * cpmem must be the stride in bytes of the Y plane.
 174                  * And all the planar YUV formats have an 8-bit
 175                  * Y component.
 176                  */
 177                 return (8 * pixel_stride) >> 3;
 178         case V4L2_PIX_FMT_RGB565:
 179         case V4L2_PIX_FMT_YUYV:
 180         case V4L2_PIX_FMT_UYVY:
 181                 return (16 * pixel_stride) >> 3;
 182         case V4L2_PIX_FMT_BGR24:
 183         case V4L2_PIX_FMT_RGB24:
 184                 return (24 * pixel_stride) >> 3;
 185         case V4L2_PIX_FMT_BGR32:
 186         case V4L2_PIX_FMT_RGB32:
 187                 return (32 * pixel_stride) >> 3;
 188         default:
 189                 break;
 190         }
 191
 192         return -EINVAL;
 193 }
 194 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
 195
 196 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
 197                             bool hflip, bool vflip)
 198 {
 199         u32 r90, vf, hf;
 200
 201         switch (degrees) {
 202         case 0:
 203                 vf = hf = r90 = 0;
 204                 break;
 205         case 90:
 206                 vf = hf = 0;
 207                 r90 = 1;
 208                 break;
 209         case 180:
 210                 vf = hf = 1;
 211                 r90 = 0;
 212                 break;
 213         case 270:
 214                 vf = hf = r90 = 1;
 215                 break;
 216         default:
 217                 return -EINVAL;
 218         }
 219
 220         hf ^= (u32)hflip;
 221         vf ^= (u32)vflip;
 222
 223         *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
 224         return 0;
 225 }
 226 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
 227
 228 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
 229                             bool hflip, bool vflip)
 230 {
 231         u32 r90, vf, hf;
 232
 233         r90 = ((u32)mode >> 2) & 0x1;
 234         hf = ((u32)mode >> 1) & 0x1;
 235         vf = ((u32)mode >> 0) & 0x1;
 236         hf ^= (u32)hflip;
 237         vf ^= (u32)vflip;
 238
 239         switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
 240         case IPU_ROTATE_NONE:
 241                 *degrees = 0;
 242                 break;
 243         case IPU_ROTATE_90_RIGHT:
 244                 *degrees = 90;
 245                 break;
 246         case IPU_ROTATE_180:
 247                 *degrees = 180;
 248                 break;
 249         case IPU_ROTATE_90_LEFT:
 250                 *degrees = 270;
 251                 break;
 252         default:
 253                 return -EINVAL;
 254         }
 255
 256         return 0;
 257 }
 258 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
 259
 260 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
 261 {
 262         struct ipuv3_channel *channel;
 263
 264         dev_dbg(ipu->dev, "%s %d\n", __func__, num);
 265
 266         if (num > 63)
 267                 return ERR_PTR(-ENODEV);
 268
 269         mutex_lock(&ipu->channel_lock);
 270
 271         channel = &ipu->channel[num];
 272
 273         if (channel->busy) {
 274                 channel = ERR_PTR(-EBUSY);
 275                 goto out;
 276         }
 277
 278         channel->busy = true;
 279         channel->num = num;
 280
 281 out:
 282         mutex_unlock(&ipu->channel_lock);
 283
 284         return channel;
 285 }
 286 EXPORT_SYMBOL_GPL(ipu_idmac_get);
 287
 288 void ipu_idmac_put(struct ipuv3_channel *channel)
 289 {
 290         struct ipu_soc *ipu = channel->ipu;
 291
 292         dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
 293
 294         mutex_lock(&ipu->channel_lock);
 295
 296         channel->busy = false;
 297
 298         mutex_unlock(&ipu->channel_lock);
 299 }
 300 EXPORT_SYMBOL_GPL(ipu_idmac_put);
 301
 302 #define idma_mask(ch)                   (1 << ((ch) & 0x1f))
 303
 304 /*
 305  * This is an undocumented feature, a write one to a channel bit in
 306  * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
 307  * internal current buffer pointer so that transfers start from buffer
 308  * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
 309  * only says these are read-only registers). This operation is required
 310  * for channel linking to work correctly, for instance video capture
 311  * pipelines that carry out image rotations will fail after the first
 312  * streaming unless this function is called for each channel before
 313  * re-enabling the channels.
 314  */
 315 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
 316 {
 317         struct ipu_soc *ipu = channel->ipu;
 318         unsigned int chno = channel->num;
 319
 320         ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
 321 }
 322
 323 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
 324                 bool doublebuffer)
 325 {
 326         struct ipu_soc *ipu = channel->ipu;
 327         unsigned long flags;
 328         u32 reg;
 329
 330         spin_lock_irqsave(&ipu->lock, flags);
 331
 332         reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 333         if (doublebuffer)
 334                 reg |= idma_mask(channel->num);
 335         else
 336                 reg &= ~idma_mask(channel->num);
 337         ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
 338
 339         __ipu_idmac_reset_current_buffer(channel);
 340
 341         spin_unlock_irqrestore(&ipu->lock, flags);
 342 }
 343 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
 344
 345 static const struct {
 346         int chnum;
 347         u32 reg;
 348         int shift;
 349 } idmac_lock_en_info[] = {
 350         { .chnum =  5, .reg = IDMAC_CH_LOCK_EN_1, .shift =  0, },
 351         { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift =  2, },
 352         { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift =  4, },
 353         { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift =  6, },
 354         { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift =  8, },
 355         { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
 356         { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
 357         { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
 358         { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
 359         { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
 360         { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
 361         { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift =  0, },
 362         { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift =  2, },
 363         { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift =  4, },
 364         { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift =  6, },
 365         { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift =  8, },
 366         { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
 367 };
 368
 369 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
 370 {
 371         struct ipu_soc *ipu = channel->ipu;
 372         unsigned long flags;
 373         u32 bursts, regval;
 374         int i;
 375
 376         switch (num_bursts) {
 377         case 0:
 378         case 1:
 379                 bursts = 0x00; /* locking disabled */
 380                 break;
 381         case 2:
 382                 bursts = 0x01;
 383                 break;
 384         case 4:
 385                 bursts = 0x02;
 386                 break;
 387         case 8:
 388                 bursts = 0x03;
 389                 break;
 390         default:
 391                 return -EINVAL;
 392         }
 393
 394         for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
 395                 if (channel->num == idmac_lock_en_info[i].chnum)
 396                         break;
 397         }
 398         if (i >= ARRAY_SIZE(idmac_lock_en_info))
 399                 return -EINVAL;
 400
 401         spin_lock_irqsave(&ipu->lock, flags);
 402
 403         regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
 404         regval &= ~(0x03 << idmac_lock_en_info[i].shift);
 405         regval |= (bursts << idmac_lock_en_info[i].shift);
 406         ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
 407
 408         spin_unlock_irqrestore(&ipu->lock, flags);
 409
 410         return 0;
 411 }
 412 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
 413
 414 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
 415 {
 416         unsigned long lock_flags;
 417         u32 val;
 418
 419         spin_lock_irqsave(&ipu->lock, lock_flags);
 420
 421         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 422
 423         if (mask & IPU_CONF_DI0_EN)
 424                 val |= IPU_DI0_COUNTER_RELEASE;
 425         if (mask & IPU_CONF_DI1_EN)
 426                 val |= IPU_DI1_COUNTER_RELEASE;
 427
 428         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 429
 430         val = ipu_cm_read(ipu, IPU_CONF);
 431         val |= mask;
 432         ipu_cm_write(ipu, val, IPU_CONF);
 433
 434         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 435
 436         return 0;
 437 }
 438 EXPORT_SYMBOL_GPL(ipu_module_enable);
 439
 440 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
 441 {
 442         unsigned long lock_flags;
 443         u32 val;
 444
 445         spin_lock_irqsave(&ipu->lock, lock_flags);
 446
 447         val = ipu_cm_read(ipu, IPU_CONF);
 448         val &= ~mask;
 449         ipu_cm_write(ipu, val, IPU_CONF);
 450
 451         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 452
 453         if (mask & IPU_CONF_DI0_EN)
 454                 val &= ~IPU_DI0_COUNTER_RELEASE;
 455         if (mask & IPU_CONF_DI1_EN)
 456                 val &= ~IPU_DI1_COUNTER_RELEASE;
 457
 458         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 459
 460         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 461
 462         return 0;
 463 }
 464 EXPORT_SYMBOL_GPL(ipu_module_disable);
 465
 466 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
 467 {
 468         struct ipu_soc *ipu = channel->ipu;
 469         unsigned int chno = channel->num;
 470
 471         return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
 472 }
 473 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
 474
 475 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
 476 {
 477         struct ipu_soc *ipu = channel->ipu;
 478         unsigned long flags;
 479         u32 reg = 0;
 480
 481         spin_lock_irqsave(&ipu->lock, flags);
 482         switch (buf_num) {
 483         case 0:
 484                 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
 485                 break;
 486         case 1:
 487                 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
 488                 break;
 489         case 2:
 490                 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
 491                 break;
 492         }
 493         spin_unlock_irqrestore(&ipu->lock, flags);
 494
 495         return ((reg & idma_mask(channel->num)) != 0);
 496 }
 497 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
 498
 499 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
 500 {
 501         struct ipu_soc *ipu = channel->ipu;
 502         unsigned int chno = channel->num;
 503         unsigned long flags;
 504
 505         spin_lock_irqsave(&ipu->lock, flags);
 506
 507         /* Mark buffer as ready. */
 508         if (buf_num == 0)
 509                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
 510         else
 511                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
 512
 513         spin_unlock_irqrestore(&ipu->lock, flags);
 514 }
 515 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
 516
 517 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
 518 {
 519         struct ipu_soc *ipu = channel->ipu;
 520         unsigned int chno = channel->num;
 521         unsigned long flags;
 522
 523         spin_lock_irqsave(&ipu->lock, flags);
 524
 525         ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
 526         switch (buf_num) {
 527         case 0:
 528                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
 529                 break;
 530         case 1:
 531                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
 532                 break;
 533         case 2:
 534                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
 535                 break;
 536         default:
 537                 break;
 538         }
 539         ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
 540
 541         spin_unlock_irqrestore(&ipu->lock, flags);
 542 }
 543 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
 544
 545 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
 546 {
 547         struct ipu_soc *ipu = channel->ipu;
 548         u32 val;
 549         unsigned long flags;
 550
 551         spin_lock_irqsave(&ipu->lock, flags);
 552
 553         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 554         val |= idma_mask(channel->num);
 555         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 556
 557         spin_unlock_irqrestore(&ipu->lock, flags);
 558
 559         return 0;
 560 }
 561 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
 562
 563 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
 564 {
 565         return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
 566 }
 567 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
 568
 569 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
 570 {
 571         struct ipu_soc *ipu = channel->ipu;
 572         unsigned long timeout;
 573
 574         timeout = jiffies + msecs_to_jiffies(ms);
 575         while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
 576                         idma_mask(channel->num)) {
 577                 if (time_after(jiffies, timeout))
 578                         return -ETIMEDOUT;
 579                 cpu_relax();
 580         }
 581
 582         return 0;
 583 }
 584 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
 585
 586 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
 587 {
 588         unsigned long timeout;
 589
 590         timeout = jiffies + msecs_to_jiffies(ms);
 591         ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
 592         while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
 593                 if (time_after(jiffies, timeout))
 594                         return -ETIMEDOUT;
 595                 cpu_relax();
 596         }
 597
 598         return 0;
 599 }
 600 EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
 601
 602 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
 603 {
 604         struct ipu_soc *ipu = channel->ipu;
 605         u32 val;
 606         unsigned long flags;
 607
 608         spin_lock_irqsave(&ipu->lock, flags);
 609
 610         /* Disable DMA channel(s) */
 611         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 612         val &= ~idma_mask(channel->num);
 613         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 614
 615         __ipu_idmac_reset_current_buffer(channel);
 616
 617         /* Set channel buffers NOT to be ready */
 618         ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
 619
 620         if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
 621                         idma_mask(channel->num)) {
 622                 ipu_cm_write(ipu, idma_mask(channel->num),
 623                              IPU_CHA_BUF0_RDY(channel->num));
 624         }
 625
 626         if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
 627                         idma_mask(channel->num)) {
 628                 ipu_cm_write(ipu, idma_mask(channel->num),
 629                              IPU_CHA_BUF1_RDY(channel->num));
 630         }
 631
 632         ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
 633
 634         /* Reset the double buffer */
 635         val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 636         val &= ~idma_mask(channel->num);
 637         ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
 638
 639         spin_unlock_irqrestore(&ipu->lock, flags);
 640
 641         return 0;
 642 }
 643 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
 644
 645 /*
 646  * The imx6 rev. D TRM says that enabling the WM feature will increase
 647  * a channel's priority. Refer to Table 36-8 Calculated priority value.
 648  * The sub-module that is the sink or source for the channel must enable
 649  * watermark signal for this to take effect (SMFC_WM for instance).
 650  */
 651 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
 652 {
 653         struct ipu_soc *ipu = channel->ipu;
 654         unsigned long flags;
 655         u32 val;
 656
 657         spin_lock_irqsave(&ipu->lock, flags);
 658
 659         val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
 660         if (enable)
 661                 val |= 1 << (channel->num % 32);
 662         else
 663                 val &= ~(1 << (channel->num % 32));
 664         ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
 665
 666         spin_unlock_irqrestore(&ipu->lock, flags);
 667 }
 668 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
 669
 670 static int ipu_memory_reset(struct ipu_soc *ipu)
 671 {
 672         unsigned long timeout;
 673
 674         ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
 675
 676         timeout = jiffies + msecs_to_jiffies(1000);
 677         while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
 678                 if (time_after(jiffies, timeout))
 679                         return -ETIME;
 680                 cpu_relax();
 681         }
 682
 683         return 0;
 684 }
 685
 686 /*
 687  * Set the source mux for the given CSI. Selects either parallel or
 688  * MIPI CSI2 sources.
 689  */
 690 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
 691 {
 692         unsigned long flags;
 693         u32 val, mask;
 694
 695         mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
 696                 IPU_CONF_CSI0_DATA_SOURCE;
 697
 698         spin_lock_irqsave(&ipu->lock, flags);
 699
 700         val = ipu_cm_read(ipu, IPU_CONF);
 701         if (mipi_csi2)
 702                 val |= mask;
 703         else
 704                 val &= ~mask;
 705         ipu_cm_write(ipu, val, IPU_CONF);
 706
 707         spin_unlock_irqrestore(&ipu->lock, flags);
 708 }
 709 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
 710
 711 /*
 712  * Set the source mux for the IC. Selects either CSI[01] or the VDI.
 713  */
 714 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
 715 {
 716         unsigned long flags;
 717         u32 val;
 718
 719         spin_lock_irqsave(&ipu->lock, flags);
 720
 721         val = ipu_cm_read(ipu, IPU_CONF);
 722         if (vdi) {
 723                 val |= IPU_CONF_IC_INPUT;
 724         } else {
 725                 val &= ~IPU_CONF_IC_INPUT;
 726                 if (csi_id == 1)
 727                         val |= IPU_CONF_CSI_SEL;
 728                 else
 729                         val &= ~IPU_CONF_CSI_SEL;
 730         }
 731         ipu_cm_write(ipu, val, IPU_CONF);
 732
 733         spin_unlock_irqrestore(&ipu->lock, flags);
 734 }
 735 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
 736
 737
 738 /* Frame Synchronization Unit Channel Linking */
 739
 740 struct fsu_link_reg_info {
 741         int chno;
 742         u32 reg;
 743         u32 mask;
 744         u32 val;
 745 };
 746
 747 struct fsu_link_info {
 748         struct fsu_link_reg_info src;
 749         struct fsu_link_reg_info sink;
 750 };
 751
 752 static const struct fsu_link_info fsu_link_info[] = {
 753         {
 754                 .src  = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2,
 755                           FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC },
 756                 .sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1,
 757                           FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC },
 758         }, {
 759                 .src =  { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2,
 760                           FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF },
 761                 .sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1,
 762                           FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF },
 763         }, {
 764                 .src =  { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2,
 765                           FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP },
 766                 .sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1,
 767                           FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP },
 768         }, {
 769                 .src =  { IPUV3_CHANNEL_CSI_DIRECT, 0 },
 770                 .sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1,
 771                           FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT },
 772         },
 773 };
 774
 775 static const struct fsu_link_info *find_fsu_link_info(int src, int sink)
 776 {
 777         int i;
 778
 779         for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) {
 780                 if (src == fsu_link_info[i].src.chno &&
 781                     sink == fsu_link_info[i].sink.chno)
 782                         return &fsu_link_info[i];
 783         }
 784
 785         return NULL;
 786 }
 787
 788 /*
 789  * Links a source channel to a sink channel in the FSU.
 790  */
 791 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch)
 792 {
 793         const struct fsu_link_info *link;
 794         u32 src_reg, sink_reg;
 795         unsigned long flags;
 796
 797         link = find_fsu_link_info(src_ch, sink_ch);
 798         if (!link)
 799                 return -EINVAL;
 800
 801         spin_lock_irqsave(&ipu->lock, flags);
 802
 803         if (link->src.mask) {
 804                 src_reg = ipu_cm_read(ipu, link->src.reg);
 805                 src_reg &= ~link->src.mask;
 806                 src_reg |= link->src.val;
 807                 ipu_cm_write(ipu, src_reg, link->src.reg);
 808         }
 809
 810         if (link->sink.mask) {
 811                 sink_reg = ipu_cm_read(ipu, link->sink.reg);
 812                 sink_reg &= ~link->sink.mask;
 813                 sink_reg |= link->sink.val;
 814                 ipu_cm_write(ipu, sink_reg, link->sink.reg);
 815         }
 816
 817         spin_unlock_irqrestore(&ipu->lock, flags);
 818         return 0;
 819 }
 820 EXPORT_SYMBOL_GPL(ipu_fsu_link);
 821
 822 /*
 823  * Unlinks source and sink channels in the FSU.
 824  */
 825 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch)
 826 {
 827         const struct fsu_link_info *link;
 828         u32 src_reg, sink_reg;
 829         unsigned long flags;
 830
 831         link = find_fsu_link_info(src_ch, sink_ch);
 832         if (!link)
 833                 return -EINVAL;
 834
 835         spin_lock_irqsave(&ipu->lock, flags);
 836
 837         if (link->src.mask) {
 838                 src_reg = ipu_cm_read(ipu, link->src.reg);
 839                 src_reg &= ~link->src.mask;
 840                 ipu_cm_write(ipu, src_reg, link->src.reg);
 841         }
 842
 843         if (link->sink.mask) {
 844                 sink_reg = ipu_cm_read(ipu, link->sink.reg);
 845                 sink_reg &= ~link->sink.mask;
 846                 ipu_cm_write(ipu, sink_reg, link->sink.reg);
 847         }
 848
 849         spin_unlock_irqrestore(&ipu->lock, flags);
 850         return 0;
 851 }
 852 EXPORT_SYMBOL_GPL(ipu_fsu_unlink);
 853
 854 /* Link IDMAC channels in the FSU */
 855 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink)
 856 {
 857         return ipu_fsu_link(src->ipu, src->num, sink->num);
 858 }
 859 EXPORT_SYMBOL_GPL(ipu_idmac_link);
 860
 861 /* Unlink IDMAC channels in the FSU */
 862 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink)
 863 {
 864         return ipu_fsu_unlink(src->ipu, src->num, sink->num);
 865 }
 866 EXPORT_SYMBOL_GPL(ipu_idmac_unlink);
 867
 868 struct ipu_devtype {
 869         const char *name;
 870         unsigned long cm_ofs;
 871         unsigned long cpmem_ofs;
 872         unsigned long srm_ofs;
 873         unsigned long tpm_ofs;
 874         unsigned long csi0_ofs;
 875         unsigned long csi1_ofs;
 876         unsigned long ic_ofs;
 877         unsigned long disp0_ofs;
 878         unsigned long disp1_ofs;
 879         unsigned long dc_tmpl_ofs;
 880         unsigned long vdi_ofs;
 881         enum ipuv3_type type;
 882 };
 883
 884 static struct ipu_devtype ipu_type_imx51 = {
 885         .name = "IPUv3EX",
 886         .cm_ofs = 0x1e000000,
 887         .cpmem_ofs = 0x1f000000,
 888         .srm_ofs = 0x1f040000,
 889         .tpm_ofs = 0x1f060000,
 890         .csi0_ofs = 0x1f030000,
 891         .csi1_ofs = 0x1f038000,
 892         .ic_ofs = 0x1e020000,
 893         .disp0_ofs = 0x1e040000,
 894         .disp1_ofs = 0x1e048000,
 895         .dc_tmpl_ofs = 0x1f080000,
 896         .vdi_ofs = 0x1e068000,
 897         .type = IPUV3EX,
 898 };
 899
 900 static struct ipu_devtype ipu_type_imx53 = {
 901         .name = "IPUv3M",
 902         .cm_ofs = 0x06000000,
 903         .cpmem_ofs = 0x07000000,
 904         .srm_ofs = 0x07040000,
 905         .tpm_ofs = 0x07060000,
 906         .csi0_ofs = 0x07030000,
 907         .csi1_ofs = 0x07038000,
 908         .ic_ofs = 0x06020000,
 909         .disp0_ofs = 0x06040000,
 910         .disp1_ofs = 0x06048000,
 911         .dc_tmpl_ofs = 0x07080000,
 912         .vdi_ofs = 0x06068000,
 913         .type = IPUV3M,
 914 };
 915
 916 static struct ipu_devtype ipu_type_imx6q = {
 917         .name = "IPUv3H",
 918         .cm_ofs = 0x00200000,
 919         .cpmem_ofs = 0x00300000,
 920         .srm_ofs = 0x00340000,
 921         .tpm_ofs = 0x00360000,
 922         .csi0_ofs = 0x00230000,
 923         .csi1_ofs = 0x00238000,
 924         .ic_ofs = 0x00220000,
 925         .disp0_ofs = 0x00240000,
 926         .disp1_ofs = 0x00248000,
 927         .dc_tmpl_ofs = 0x00380000,
 928         .vdi_ofs = 0x00268000,
 929         .type = IPUV3H,
 930 };
 931
 932 static const struct of_device_id imx_ipu_dt_ids[] = {
 933         { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
 934         { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
 935         { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
 936         { /* sentinel */ }
 937 };
 938 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
 939
 940 static int ipu_submodules_init(struct ipu_soc *ipu,
 941                 struct platform_device *pdev, unsigned long ipu_base,
 942                 struct clk *ipu_clk)
 943 {
 944         char *unit;
 945         int ret;
 946         struct device *dev = &pdev->dev;
 947         const struct ipu_devtype *devtype = ipu->devtype;
 948
 949         ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
 950         if (ret) {
 951                 unit = "cpmem";
 952                 goto err_cpmem;
 953         }
 954
 955         ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
 956                            IPU_CONF_CSI0_EN, ipu_clk);
 957         if (ret) {
 958                 unit = "csi0";
 959                 goto err_csi_0;
 960         }
 961
 962         ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
 963                            IPU_CONF_CSI1_EN, ipu_clk);
 964         if (ret) {
 965                 unit = "csi1";
 966                 goto err_csi_1;
 967         }
 968
 969         ret = ipu_ic_init(ipu, dev,
 970                           ipu_base + devtype->ic_ofs,
 971                           ipu_base + devtype->tpm_ofs);
 972         if (ret) {
 973                 unit = "ic";
 974                 goto err_ic;
 975         }
 976
 977         ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs,
 978                            IPU_CONF_VDI_EN | IPU_CONF_ISP_EN |
 979                            IPU_CONF_IC_INPUT);
 980         if (ret) {
 981                 unit = "vdi";
 982                 goto err_vdi;
 983         }
 984
 985         ret = ipu_image_convert_init(ipu, dev);
 986         if (ret) {
 987                 unit = "image_convert";
 988                 goto err_image_convert;
 989         }
 990
 991         ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
 992                           IPU_CONF_DI0_EN, ipu_clk);
 993         if (ret) {
 994                 unit = "di0";
 995                 goto err_di_0;
 996         }
 997
 998         ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
 999                         IPU_CONF_DI1_EN, ipu_clk);
1000         if (ret) {
1001                 unit = "di1";
1002                 goto err_di_1;
1003         }
1004
1005         ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
1006                         IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
1007         if (ret) {
1008                 unit = "dc_template";
1009                 goto err_dc;
1010         }
1011
1012         ret = ipu_dmfc_init(ipu, dev, ipu_base +
1013                         devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
1014         if (ret) {
1015                 unit = "dmfc";
1016                 goto err_dmfc;
1017         }
1018
1019         ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
1020         if (ret) {
1021                 unit = "dp";
1022                 goto err_dp;
1023         }
1024
1025         ret = ipu_smfc_init(ipu, dev, ipu_base +
1026                         devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
1027         if (ret) {
1028                 unit = "smfc";
1029                 goto err_smfc;
1030         }
1031
1032         return 0;
1033
1034 err_smfc:
1035         ipu_dp_exit(ipu);
1036 err_dp:
1037         ipu_dmfc_exit(ipu);
1038 err_dmfc:
1039         ipu_dc_exit(ipu);
1040 err_dc:
1041         ipu_di_exit(ipu, 1);
1042 err_di_1:
1043         ipu_di_exit(ipu, 0);
1044 err_di_0:
1045         ipu_image_convert_exit(ipu);
1046 err_image_convert:
1047         ipu_vdi_exit(ipu);
1048 err_vdi:
1049         ipu_ic_exit(ipu);
1050 err_ic:
1051         ipu_csi_exit(ipu, 1);
1052 err_csi_1:
1053         ipu_csi_exit(ipu, 0);
1054 err_csi_0:
1055         ipu_cpmem_exit(ipu);
1056 err_cpmem:
1057         dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
1058         return ret;
1059 }
1060
1061 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
1062 {
1063         unsigned long status;
1064         int i, bit, irq;
1065
1066         for (i = 0; i < num_regs; i++) {
1067
1068                 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
1069                 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
1070
1071                 for_each_set_bit(bit, &status, 32) {
1072                         irq = irq_linear_revmap(ipu->domain,
1073                                                 regs[i] * 32 + bit);
1074                         if (irq)
1075                                 generic_handle_irq(irq);
1076                 }
1077         }
1078 }
1079
1080 static void ipu_irq_handler(struct irq_desc *desc)
1081 {
1082         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1083         struct irq_chip *chip = irq_desc_get_chip(desc);
1084         const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
1085
1086         chained_irq_enter(chip, desc);
1087
1088         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1089
1090         chained_irq_exit(chip, desc);
1091 }
1092
1093 static void ipu_err_irq_handler(struct irq_desc *desc)
1094 {
1095         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1096         struct irq_chip *chip = irq_desc_get_chip(desc);
1097         const int int_reg[] = { 4, 5, 8, 9};
1098
1099         chained_irq_enter(chip, desc);
1100
1101         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1102
1103         chained_irq_exit(chip, desc);
1104 }
1105
1106 int ipu_map_irq(struct ipu_soc *ipu, int irq)
1107 {
1108         int virq;
1109
1110         virq = irq_linear_revmap(ipu->domain, irq);
1111         if (!virq)
1112                 virq = irq_create_mapping(ipu->domain, irq);
1113
1114         return virq;
1115 }
1116 EXPORT_SYMBOL_GPL(ipu_map_irq);
1117
1118 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
1119                 enum ipu_channel_irq irq_type)
1120 {
1121         return ipu_map_irq(ipu, irq_type + channel->num);
1122 }
1123 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
1124
1125 static void ipu_submodules_exit(struct ipu_soc *ipu)
1126 {
1127         ipu_smfc_exit(ipu);
1128         ipu_dp_exit(ipu);
1129         ipu_dmfc_exit(ipu);
1130         ipu_dc_exit(ipu);
1131         ipu_di_exit(ipu, 1);
1132         ipu_di_exit(ipu, 0);
1133         ipu_image_convert_exit(ipu);
1134         ipu_vdi_exit(ipu);
1135         ipu_ic_exit(ipu);
1136         ipu_csi_exit(ipu, 1);
1137         ipu_csi_exit(ipu, 0);
1138         ipu_cpmem_exit(ipu);
1139 }
1140
1141 static int platform_remove_devices_fn(struct device *dev, void *unused)
1142 {
1143         struct platform_device *pdev = to_platform_device(dev);
1144
1145         platform_device_unregister(pdev);
1146
1147         return 0;
1148 }
1149
1150 static void platform_device_unregister_children(struct platform_device *pdev)
1151 {
1152         device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
1153 }
1154
1155 struct ipu_platform_reg {
1156         struct ipu_client_platformdata pdata;
1157         const char *name;
1158 };
1159
1160 /* These must be in the order of the corresponding device tree port nodes */
1161 static struct ipu_platform_reg client_reg[] = {
1162         {
1163                 .pdata = {
1164                         .csi = 0,
1165                         .dma[0] = IPUV3_CHANNEL_CSI0,
1166                         .dma[1] = -EINVAL,
1167                 },
1168                 .name = "imx-ipuv3-csi",
1169         }, {
1170                 .pdata = {
1171                         .csi = 1,
1172                         .dma[0] = IPUV3_CHANNEL_CSI1,
1173                         .dma[1] = -EINVAL,
1174                 },
1175                 .name = "imx-ipuv3-csi",
1176         }, {
1177                 .pdata = {
1178                         .di = 0,
1179                         .dc = 5,
1180                         .dp = IPU_DP_FLOW_SYNC_BG,
1181                         .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
1182                         .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
1183                 },
1184                 .name = "imx-ipuv3-crtc",
1185         }, {
1186                 .pdata = {
1187                         .di = 1,
1188                         .dc = 1,
1189                         .dp = -EINVAL,
1190                         .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
1191                         .dma[1] = -EINVAL,
1192                 },
1193                 .name = "imx-ipuv3-crtc",
1194         },
1195 };
1196
1197 static DEFINE_MUTEX(ipu_client_id_mutex);
1198 static int ipu_client_id;
1199
1200 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
1201 {
1202         struct device *dev = ipu->dev;
1203         unsigned i;
1204         int id, ret;
1205
1206         mutex_lock(&ipu_client_id_mutex);
1207         id = ipu_client_id;
1208         ipu_client_id += ARRAY_SIZE(client_reg);
1209         mutex_unlock(&ipu_client_id_mutex);
1210
1211         for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
1212                 struct ipu_platform_reg *reg = &client_reg[i];
1213                 struct platform_device *pdev;
1214                 struct device_node *of_node;
1215
1216                 /* Associate subdevice with the corresponding port node */
1217                 of_node = of_graph_get_port_by_id(dev->of_node, i);
1218                 if (!of_node) {
1219                         dev_info(dev,
1220                                  "no port@%d node in %s, not using %s%d\n",
1221                                  i, dev->of_node->full_name,
1222                                  (i / 2) ? "DI" : "CSI", i % 2);
1223                         continue;
1224                 }
1225
1226                 pdev = platform_device_alloc(reg->name, id++);
1227                 if (!pdev) {
1228                         ret = -ENOMEM;
1229                         goto err_register;
1230                 }
1231
1232                 pdev->dev.parent = dev;
1233
1234                 reg->pdata.of_node = of_node;
1235                 ret = platform_device_add_data(pdev, &reg->pdata,
1236                                                sizeof(reg->pdata));
1237                 if (!ret)
1238                         ret = platform_device_add(pdev);
1239                 if (ret) {
1240                         platform_device_put(pdev);
1241                         goto err_register;
1242                 }
1243         }
1244
1245         return 0;
1246
1247 err_register:
1248         platform_device_unregister_children(to_platform_device(dev));
1249
1250         return ret;
1251 }
1252
1253
1254 static int ipu_irq_init(struct ipu_soc *ipu)
1255 {
1256         struct irq_chip_generic *gc;
1257         struct irq_chip_type *ct;
1258         unsigned long unused[IPU_NUM_IRQS / 32] = {
1259                 0x400100d0, 0xffe000fd,
1260                 0x400100d0, 0xffe000fd,
1261                 0x400100d0, 0xffe000fd,
1262                 0x4077ffff, 0xffe7e1fd,
1263                 0x23fffffe, 0x8880fff0,
1264                 0xf98fe7d0, 0xfff81fff,
1265                 0x400100d0, 0xffe000fd,
1266                 0x00000000,
1267         };
1268         int ret, i;
1269
1270         ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
1271                                             &irq_generic_chip_ops, ipu);
1272         if (!ipu->domain) {
1273                 dev_err(ipu->dev, "failed to add irq domain\n");
1274                 return -ENODEV;
1275         }
1276
1277         ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1278                                              handle_level_irq, 0, 0, 0);
1279         if (ret < 0) {
1280                 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1281                 irq_domain_remove(ipu->domain);
1282                 return ret;
1283         }
1284
1285         /* Mask and clear all interrupts */
1286         for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1287                 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
1288                 ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32));
1289         }
1290
1291         for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1292                 gc = irq_get_domain_generic_chip(ipu->domain, i);
1293                 gc->reg_base = ipu->cm_reg;
1294                 gc->unused = unused[i / 32];
1295                 ct = gc->chip_types;
1296                 ct->chip.irq_ack = irq_gc_ack_set_bit;
1297                 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1298                 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1299                 ct->regs.ack = IPU_INT_STAT(i / 32);
1300                 ct->regs.mask = IPU_INT_CTRL(i / 32);
1301         }
1302
1303         irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
1304         irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
1305                                          ipu);
1306
1307         return 0;
1308 }
1309
1310 static void ipu_irq_exit(struct ipu_soc *ipu)
1311 {
1312         int i, irq;
1313
1314         irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
1315         irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
1316
1317         /* TODO: remove irq_domain_generic_chips */
1318
1319         for (i = 0; i < IPU_NUM_IRQS; i++) {
1320                 irq = irq_linear_revmap(ipu->domain, i);
1321                 if (irq)
1322                         irq_dispose_mapping(irq);
1323         }
1324
1325         irq_domain_remove(ipu->domain);
1326 }
1327
1328 void ipu_dump(struct ipu_soc *ipu)
1329 {
1330         int i;
1331
1332         dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
1333                 ipu_cm_read(ipu, IPU_CONF));
1334         dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
1335                 ipu_idmac_read(ipu, IDMAC_CONF));
1336         dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
1337                 ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
1338         dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
1339                 ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
1340         dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1341                 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
1342         dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1343                 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
1344         dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
1345                 ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
1346         dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
1347                 ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
1348         dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1349                 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
1350         dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1351                 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
1352         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1353                 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
1354         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1355                 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
1356         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1357                 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
1358         dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1359                 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
1360         for (i = 0; i < 15; i++)
1361                 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
1362                         ipu_cm_read(ipu, IPU_INT_CTRL(i)));
1363 }
1364 EXPORT_SYMBOL_GPL(ipu_dump);
1365
1366 static int ipu_probe(struct platform_device *pdev)
1367 {
1368         struct device_node *np = pdev->dev.of_node;
1369         struct ipu_soc *ipu;
1370         struct resource *res;
1371         unsigned long ipu_base;
1372         int i, ret, irq_sync, irq_err;
1373         const struct ipu_devtype *devtype;
1374
1375         devtype = of_device_get_match_data(&pdev->dev);
1376         if (!devtype)
1377                 return -EINVAL;
1378
1379         irq_sync = platform_get_irq(pdev, 0);
1380         irq_err = platform_get_irq(pdev, 1);
1381         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1382
1383         dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
1384                         irq_sync, irq_err);
1385
1386         if (!res || irq_sync < 0 || irq_err < 0)
1387                 return -ENODEV;
1388
1389         ipu_base = res->start;
1390
1391         ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1392         if (!ipu)
1393                 return -ENODEV;
1394
1395         for (i = 0; i < 64; i++)
1396                 ipu->channel[i].ipu = ipu;
1397         ipu->devtype = devtype;
1398         ipu->ipu_type = devtype->type;
1399         ipu->id = of_alias_get_id(np, "ipu");
1400
1401         spin_lock_init(&ipu->lock);
1402         mutex_init(&ipu->channel_lock);
1403
1404         dev_dbg(&pdev->dev, "cm_reg:   0x%08lx\n",
1405                         ipu_base + devtype->cm_ofs);
1406         dev_dbg(&pdev->dev, "idmac:    0x%08lx\n",
1407                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1408         dev_dbg(&pdev->dev, "cpmem:    0x%08lx\n",
1409                         ipu_base + devtype->cpmem_ofs);
1410         dev_dbg(&pdev->dev, "csi0:    0x%08lx\n",
1411                         ipu_base + devtype->csi0_ofs);
1412         dev_dbg(&pdev->dev, "csi1:    0x%08lx\n",
1413                         ipu_base + devtype->csi1_ofs);
1414         dev_dbg(&pdev->dev, "ic:      0x%08lx\n",
1415                         ipu_base + devtype->ic_ofs);
1416         dev_dbg(&pdev->dev, "disp0:    0x%08lx\n",
1417                         ipu_base + devtype->disp0_ofs);
1418         dev_dbg(&pdev->dev, "disp1:    0x%08lx\n",
1419                         ipu_base + devtype->disp1_ofs);
1420         dev_dbg(&pdev->dev, "srm:      0x%08lx\n",
1421                         ipu_base + devtype->srm_ofs);
1422         dev_dbg(&pdev->dev, "tpm:      0x%08lx\n",
1423                         ipu_base + devtype->tpm_ofs);
1424         dev_dbg(&pdev->dev, "dc:       0x%08lx\n",
1425                         ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1426         dev_dbg(&pdev->dev, "ic:       0x%08lx\n",
1427                         ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1428         dev_dbg(&pdev->dev, "dmfc:     0x%08lx\n",
1429                         ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1430         dev_dbg(&pdev->dev, "vdi:      0x%08lx\n",
1431                         ipu_base + devtype->vdi_ofs);
1432
1433         ipu->cm_reg = devm_ioremap(&pdev->dev,
1434                         ipu_base + devtype->cm_ofs, PAGE_SIZE);
1435         ipu->idmac_reg = devm_ioremap(&pdev->dev,
1436                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1437                         PAGE_SIZE);
1438
1439         if (!ipu->cm_reg || !ipu->idmac_reg)
1440                 return -ENOMEM;
1441
1442         ipu->clk = devm_clk_get(&pdev->dev, "bus");
1443         if (IS_ERR(ipu->clk)) {
1444                 ret = PTR_ERR(ipu->clk);
1445                 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1446                 return ret;
1447         }
1448
1449         platform_set_drvdata(pdev, ipu);
1450
1451         ret = clk_prepare_enable(ipu->clk);
1452         if (ret) {
1453                 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1454                 return ret;
1455         }
1456
1457         ipu->dev = &pdev->dev;
1458         ipu->irq_sync = irq_sync;
1459         ipu->irq_err = irq_err;
1460
1461         ret = device_reset(&pdev->dev);
1462         if (ret) {
1463                 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1464                 goto out_failed_reset;
1465         }
1466         ret = ipu_memory_reset(ipu);
1467         if (ret)
1468                 goto out_failed_reset;
1469
1470         ret = ipu_irq_init(ipu);
1471         if (ret)
1472                 goto out_failed_irq;
1473
1474         /* Set MCU_T to divide MCU access window into 2 */
1475         ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1476                         IPU_DISP_GEN);
1477
1478         ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1479         if (ret)
1480                 goto failed_submodules_init;
1481
1482         ret = ipu_add_client_devices(ipu, ipu_base);
1483         if (ret) {
1484                 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1485                                 ret);
1486                 goto failed_add_clients;
1487         }
1488
1489         dev_info(&pdev->dev, "%s probed\n", devtype->name);
1490
1491         return 0;
1492
1493 failed_add_clients:
1494         ipu_submodules_exit(ipu);
1495 failed_submodules_init:
1496         ipu_irq_exit(ipu);
1497 out_failed_irq:
1498 out_failed_reset:
1499         clk_disable_unprepare(ipu->clk);
1500         return ret;
1501 }
1502
1503 static int ipu_remove(struct platform_device *pdev)
1504 {
1505         struct ipu_soc *ipu = platform_get_drvdata(pdev);
1506
1507         platform_device_unregister_children(pdev);
1508         ipu_submodules_exit(ipu);
1509         ipu_irq_exit(ipu);
1510
1511         clk_disable_unprepare(ipu->clk);
1512
1513         return 0;
1514 }
1515
1516 static struct platform_driver imx_ipu_driver = {
1517         .driver = {
1518                 .name = "imx-ipuv3",
1519                 .of_match_table = imx_ipu_dt_ids,
1520         },
1521         .probe = ipu_probe,
1522         .remove = ipu_remove,
1523 };
1524
1525 module_platform_driver(imx_ipu_driver);
1526
1527 MODULE_ALIAS("platform:imx-ipuv3");
1528 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1529 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1530 MODULE_LICENSE("GPL");