2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 #include <linux/module.h>
16 #include <linux/export.h>
17 #include <linux/types.h>
18 #include <linux/reset.h>
19 #include <linux/platform_device.h>
20 #include <linux/err.h>
21 #include <linux/spinlock.h>
22 #include <linux/delay.h>
23 #include <linux/interrupt.h>
25 #include <linux/clk.h>
26 #include <linux/list.h>
27 #include <linux/irq.h>
28 #include <linux/irqchip/chained_irq.h>
29 #include <linux/irqdomain.h>
30 #include <linux/of_device.h>
31 #include <linux/of_graph.h>
33 #include <drm/drm_fourcc.h>
35 #include <video/imx-ipu-v3.h>
38 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
40 return readl(ipu->cm_reg + offset);
43 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
45 writel(value, ipu->cm_reg + offset);
48 int ipu_get_num(struct ipu_soc *ipu)
52 EXPORT_SYMBOL_GPL(ipu_get_num);
54 void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
58 val = ipu_cm_read(ipu, IPU_SRM_PRI2);
60 ipu_cm_write(ipu, val, IPU_SRM_PRI2);
62 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
64 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
67 case DRM_FORMAT_ARGB1555:
68 case DRM_FORMAT_ABGR1555:
69 case DRM_FORMAT_RGBA5551:
70 case DRM_FORMAT_BGRA5551:
71 case DRM_FORMAT_RGB565:
72 case DRM_FORMAT_BGR565:
73 case DRM_FORMAT_RGB888:
74 case DRM_FORMAT_BGR888:
75 case DRM_FORMAT_ARGB4444:
76 case DRM_FORMAT_XRGB8888:
77 case DRM_FORMAT_XBGR8888:
78 case DRM_FORMAT_RGBX8888:
79 case DRM_FORMAT_BGRX8888:
80 case DRM_FORMAT_ARGB8888:
81 case DRM_FORMAT_ABGR8888:
82 case DRM_FORMAT_RGBA8888:
83 case DRM_FORMAT_BGRA8888:
84 return IPUV3_COLORSPACE_RGB;
87 case DRM_FORMAT_YUV420:
88 case DRM_FORMAT_YVU420:
89 case DRM_FORMAT_YUV422:
90 case DRM_FORMAT_YVU422:
91 case DRM_FORMAT_YUV444:
92 case DRM_FORMAT_YVU444:
97 return IPUV3_COLORSPACE_YUV;
99 return IPUV3_COLORSPACE_UNKNOWN;
102 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
104 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
106 switch (pixelformat) {
107 case V4L2_PIX_FMT_YUV420:
108 case V4L2_PIX_FMT_YVU420:
109 case V4L2_PIX_FMT_YUV422P:
110 case V4L2_PIX_FMT_UYVY:
111 case V4L2_PIX_FMT_YUYV:
112 case V4L2_PIX_FMT_NV12:
113 case V4L2_PIX_FMT_NV21:
114 case V4L2_PIX_FMT_NV16:
115 case V4L2_PIX_FMT_NV61:
116 return IPUV3_COLORSPACE_YUV;
117 case V4L2_PIX_FMT_RGB32:
118 case V4L2_PIX_FMT_BGR32:
119 case V4L2_PIX_FMT_RGB24:
120 case V4L2_PIX_FMT_BGR24:
121 case V4L2_PIX_FMT_RGB565:
122 return IPUV3_COLORSPACE_RGB;
124 return IPUV3_COLORSPACE_UNKNOWN;
127 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
129 bool ipu_pixelformat_is_planar(u32 pixelformat)
131 switch (pixelformat) {
132 case V4L2_PIX_FMT_YUV420:
133 case V4L2_PIX_FMT_YVU420:
134 case V4L2_PIX_FMT_YUV422P:
135 case V4L2_PIX_FMT_NV12:
136 case V4L2_PIX_FMT_NV21:
137 case V4L2_PIX_FMT_NV16:
138 case V4L2_PIX_FMT_NV61:
144 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
146 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
148 switch (mbus_code & 0xf000) {
150 return IPUV3_COLORSPACE_RGB;
152 return IPUV3_COLORSPACE_YUV;
154 return IPUV3_COLORSPACE_UNKNOWN;
157 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
159 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
161 switch (pixelformat) {
162 case V4L2_PIX_FMT_YUV420:
163 case V4L2_PIX_FMT_YVU420:
164 case V4L2_PIX_FMT_YUV422P:
165 case V4L2_PIX_FMT_NV12:
166 case V4L2_PIX_FMT_NV21:
167 case V4L2_PIX_FMT_NV16:
168 case V4L2_PIX_FMT_NV61:
170 * for the planar YUV formats, the stride passed to
171 * cpmem must be the stride in bytes of the Y plane.
172 * And all the planar YUV formats have an 8-bit
175 return (8 * pixel_stride) >> 3;
176 case V4L2_PIX_FMT_RGB565:
177 case V4L2_PIX_FMT_YUYV:
178 case V4L2_PIX_FMT_UYVY:
179 return (16 * pixel_stride) >> 3;
180 case V4L2_PIX_FMT_BGR24:
181 case V4L2_PIX_FMT_RGB24:
182 return (24 * pixel_stride) >> 3;
183 case V4L2_PIX_FMT_BGR32:
184 case V4L2_PIX_FMT_RGB32:
185 return (32 * pixel_stride) >> 3;
192 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
194 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
195 bool hflip, bool vflip)
221 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
224 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
226 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
227 bool hflip, bool vflip)
231 r90 = ((u32)mode >> 2) & 0x1;
232 hf = ((u32)mode >> 1) & 0x1;
233 vf = ((u32)mode >> 0) & 0x1;
237 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
238 case IPU_ROTATE_NONE:
241 case IPU_ROTATE_90_RIGHT:
247 case IPU_ROTATE_90_LEFT:
256 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
258 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
260 struct ipuv3_channel *channel;
262 dev_dbg(ipu->dev, "%s %d\n", __func__, num);
265 return ERR_PTR(-ENODEV);
267 mutex_lock(&ipu->channel_lock);
269 channel = &ipu->channel[num];
272 channel = ERR_PTR(-EBUSY);
276 channel->busy = true;
280 mutex_unlock(&ipu->channel_lock);
284 EXPORT_SYMBOL_GPL(ipu_idmac_get);
286 void ipu_idmac_put(struct ipuv3_channel *channel)
288 struct ipu_soc *ipu = channel->ipu;
290 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
292 mutex_lock(&ipu->channel_lock);
294 channel->busy = false;
296 mutex_unlock(&ipu->channel_lock);
298 EXPORT_SYMBOL_GPL(ipu_idmac_put);
300 #define idma_mask(ch) (1 << ((ch) & 0x1f))
303 * This is an undocumented feature, a write one to a channel bit in
304 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
305 * internal current buffer pointer so that transfers start from buffer
306 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
307 * only says these are read-only registers). This operation is required
308 * for channel linking to work correctly, for instance video capture
309 * pipelines that carry out image rotations will fail after the first
310 * streaming unless this function is called for each channel before
311 * re-enabling the channels.
313 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
315 struct ipu_soc *ipu = channel->ipu;
316 unsigned int chno = channel->num;
318 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
321 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
324 struct ipu_soc *ipu = channel->ipu;
328 spin_lock_irqsave(&ipu->lock, flags);
330 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
332 reg |= idma_mask(channel->num);
334 reg &= ~idma_mask(channel->num);
335 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
337 __ipu_idmac_reset_current_buffer(channel);
339 spin_unlock_irqrestore(&ipu->lock, flags);
341 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
343 static const struct {
347 } idmac_lock_en_info[] = {
348 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, },
349 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, },
350 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, },
351 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, },
352 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, },
353 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
354 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
355 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
356 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
357 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
358 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
359 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, },
360 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, },
361 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, },
362 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, },
363 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, },
364 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
367 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
369 struct ipu_soc *ipu = channel->ipu;
374 switch (num_bursts) {
377 bursts = 0x00; /* locking disabled */
392 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
393 if (channel->num == idmac_lock_en_info[i].chnum)
396 if (i >= ARRAY_SIZE(idmac_lock_en_info))
399 spin_lock_irqsave(&ipu->lock, flags);
401 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
402 regval &= ~(0x03 << idmac_lock_en_info[i].shift);
403 regval |= (bursts << idmac_lock_en_info[i].shift);
404 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
406 spin_unlock_irqrestore(&ipu->lock, flags);
410 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
412 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
414 unsigned long lock_flags;
417 spin_lock_irqsave(&ipu->lock, lock_flags);
419 val = ipu_cm_read(ipu, IPU_DISP_GEN);
421 if (mask & IPU_CONF_DI0_EN)
422 val |= IPU_DI0_COUNTER_RELEASE;
423 if (mask & IPU_CONF_DI1_EN)
424 val |= IPU_DI1_COUNTER_RELEASE;
426 ipu_cm_write(ipu, val, IPU_DISP_GEN);
428 val = ipu_cm_read(ipu, IPU_CONF);
430 ipu_cm_write(ipu, val, IPU_CONF);
432 spin_unlock_irqrestore(&ipu->lock, lock_flags);
436 EXPORT_SYMBOL_GPL(ipu_module_enable);
438 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
440 unsigned long lock_flags;
443 spin_lock_irqsave(&ipu->lock, lock_flags);
445 val = ipu_cm_read(ipu, IPU_CONF);
447 ipu_cm_write(ipu, val, IPU_CONF);
449 val = ipu_cm_read(ipu, IPU_DISP_GEN);
451 if (mask & IPU_CONF_DI0_EN)
452 val &= ~IPU_DI0_COUNTER_RELEASE;
453 if (mask & IPU_CONF_DI1_EN)
454 val &= ~IPU_DI1_COUNTER_RELEASE;
456 ipu_cm_write(ipu, val, IPU_DISP_GEN);
458 spin_unlock_irqrestore(&ipu->lock, lock_flags);
462 EXPORT_SYMBOL_GPL(ipu_module_disable);
464 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
466 struct ipu_soc *ipu = channel->ipu;
467 unsigned int chno = channel->num;
469 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
471 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
473 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
475 struct ipu_soc *ipu = channel->ipu;
479 spin_lock_irqsave(&ipu->lock, flags);
482 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
485 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
488 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
491 spin_unlock_irqrestore(&ipu->lock, flags);
493 return ((reg & idma_mask(channel->num)) != 0);
495 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
497 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
499 struct ipu_soc *ipu = channel->ipu;
500 unsigned int chno = channel->num;
503 spin_lock_irqsave(&ipu->lock, flags);
505 /* Mark buffer as ready. */
507 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
509 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
511 spin_unlock_irqrestore(&ipu->lock, flags);
513 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
515 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
517 struct ipu_soc *ipu = channel->ipu;
518 unsigned int chno = channel->num;
521 spin_lock_irqsave(&ipu->lock, flags);
523 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
526 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
529 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
532 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
537 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
539 spin_unlock_irqrestore(&ipu->lock, flags);
541 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
543 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
545 struct ipu_soc *ipu = channel->ipu;
549 spin_lock_irqsave(&ipu->lock, flags);
551 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
552 val |= idma_mask(channel->num);
553 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
555 spin_unlock_irqrestore(&ipu->lock, flags);
559 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
561 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
563 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
565 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
567 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
569 struct ipu_soc *ipu = channel->ipu;
570 unsigned long timeout;
572 timeout = jiffies + msecs_to_jiffies(ms);
573 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
574 idma_mask(channel->num)) {
575 if (time_after(jiffies, timeout))
582 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
584 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
586 unsigned long timeout;
588 timeout = jiffies + msecs_to_jiffies(ms);
589 ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
590 while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
591 if (time_after(jiffies, timeout))
598 EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
600 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
602 struct ipu_soc *ipu = channel->ipu;
606 spin_lock_irqsave(&ipu->lock, flags);
608 /* Disable DMA channel(s) */
609 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
610 val &= ~idma_mask(channel->num);
611 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
613 __ipu_idmac_reset_current_buffer(channel);
615 /* Set channel buffers NOT to be ready */
616 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
618 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
619 idma_mask(channel->num)) {
620 ipu_cm_write(ipu, idma_mask(channel->num),
621 IPU_CHA_BUF0_RDY(channel->num));
624 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
625 idma_mask(channel->num)) {
626 ipu_cm_write(ipu, idma_mask(channel->num),
627 IPU_CHA_BUF1_RDY(channel->num));
630 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
632 /* Reset the double buffer */
633 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
634 val &= ~idma_mask(channel->num);
635 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
637 spin_unlock_irqrestore(&ipu->lock, flags);
641 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
644 * The imx6 rev. D TRM says that enabling the WM feature will increase
645 * a channel's priority. Refer to Table 36-8 Calculated priority value.
646 * The sub-module that is the sink or source for the channel must enable
647 * watermark signal for this to take effect (SMFC_WM for instance).
649 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
651 struct ipu_soc *ipu = channel->ipu;
655 spin_lock_irqsave(&ipu->lock, flags);
657 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
659 val |= 1 << (channel->num % 32);
661 val &= ~(1 << (channel->num % 32));
662 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
664 spin_unlock_irqrestore(&ipu->lock, flags);
666 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
668 static int ipu_memory_reset(struct ipu_soc *ipu)
670 unsigned long timeout;
672 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
674 timeout = jiffies + msecs_to_jiffies(1000);
675 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
676 if (time_after(jiffies, timeout))
685 * Set the source mux for the given CSI. Selects either parallel or
688 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
693 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
694 IPU_CONF_CSI0_DATA_SOURCE;
696 spin_lock_irqsave(&ipu->lock, flags);
698 val = ipu_cm_read(ipu, IPU_CONF);
703 ipu_cm_write(ipu, val, IPU_CONF);
705 spin_unlock_irqrestore(&ipu->lock, flags);
707 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
710 * Set the source mux for the IC. Selects either CSI[01] or the VDI.
712 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
717 spin_lock_irqsave(&ipu->lock, flags);
719 val = ipu_cm_read(ipu, IPU_CONF);
721 val |= IPU_CONF_IC_INPUT;
723 val &= ~IPU_CONF_IC_INPUT;
725 val |= IPU_CONF_CSI_SEL;
727 val &= ~IPU_CONF_CSI_SEL;
729 ipu_cm_write(ipu, val, IPU_CONF);
731 spin_unlock_irqrestore(&ipu->lock, flags);
733 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
736 /* Frame Synchronization Unit Channel Linking */
738 struct fsu_link_reg_info {
745 struct fsu_link_info {
746 struct fsu_link_reg_info src;
747 struct fsu_link_reg_info sink;
750 static const struct fsu_link_info fsu_link_info[] = {
752 .src = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2,
753 FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC },
754 .sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1,
755 FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC },
757 .src = { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2,
758 FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF },
759 .sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1,
760 FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF },
762 .src = { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2,
763 FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP },
764 .sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1,
765 FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP },
767 .src = { IPUV3_CHANNEL_CSI_DIRECT, 0 },
768 .sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1,
769 FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT },
773 static const struct fsu_link_info *find_fsu_link_info(int src, int sink)
777 for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) {
778 if (src == fsu_link_info[i].src.chno &&
779 sink == fsu_link_info[i].sink.chno)
780 return &fsu_link_info[i];
787 * Links a source channel to a sink channel in the FSU.
789 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch)
791 const struct fsu_link_info *link;
792 u32 src_reg, sink_reg;
795 link = find_fsu_link_info(src_ch, sink_ch);
799 spin_lock_irqsave(&ipu->lock, flags);
801 if (link->src.mask) {
802 src_reg = ipu_cm_read(ipu, link->src.reg);
803 src_reg &= ~link->src.mask;
804 src_reg |= link->src.val;
805 ipu_cm_write(ipu, src_reg, link->src.reg);
808 if (link->sink.mask) {
809 sink_reg = ipu_cm_read(ipu, link->sink.reg);
810 sink_reg &= ~link->sink.mask;
811 sink_reg |= link->sink.val;
812 ipu_cm_write(ipu, sink_reg, link->sink.reg);
815 spin_unlock_irqrestore(&ipu->lock, flags);
818 EXPORT_SYMBOL_GPL(ipu_fsu_link);
821 * Unlinks source and sink channels in the FSU.
823 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch)
825 const struct fsu_link_info *link;
826 u32 src_reg, sink_reg;
829 link = find_fsu_link_info(src_ch, sink_ch);
833 spin_lock_irqsave(&ipu->lock, flags);
835 if (link->src.mask) {
836 src_reg = ipu_cm_read(ipu, link->src.reg);
837 src_reg &= ~link->src.mask;
838 ipu_cm_write(ipu, src_reg, link->src.reg);
841 if (link->sink.mask) {
842 sink_reg = ipu_cm_read(ipu, link->sink.reg);
843 sink_reg &= ~link->sink.mask;
844 ipu_cm_write(ipu, sink_reg, link->sink.reg);
847 spin_unlock_irqrestore(&ipu->lock, flags);
850 EXPORT_SYMBOL_GPL(ipu_fsu_unlink);
852 /* Link IDMAC channels in the FSU */
853 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink)
855 return ipu_fsu_link(src->ipu, src->num, sink->num);
857 EXPORT_SYMBOL_GPL(ipu_idmac_link);
859 /* Unlink IDMAC channels in the FSU */
860 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink)
862 return ipu_fsu_unlink(src->ipu, src->num, sink->num);
864 EXPORT_SYMBOL_GPL(ipu_idmac_unlink);
868 unsigned long cm_ofs;
869 unsigned long cpmem_ofs;
870 unsigned long srm_ofs;
871 unsigned long tpm_ofs;
872 unsigned long csi0_ofs;
873 unsigned long csi1_ofs;
874 unsigned long ic_ofs;
875 unsigned long disp0_ofs;
876 unsigned long disp1_ofs;
877 unsigned long dc_tmpl_ofs;
878 unsigned long vdi_ofs;
879 enum ipuv3_type type;
882 static struct ipu_devtype ipu_type_imx51 = {
884 .cm_ofs = 0x1e000000,
885 .cpmem_ofs = 0x1f000000,
886 .srm_ofs = 0x1f040000,
887 .tpm_ofs = 0x1f060000,
888 .csi0_ofs = 0x1f030000,
889 .csi1_ofs = 0x1f038000,
890 .ic_ofs = 0x1e020000,
891 .disp0_ofs = 0x1e040000,
892 .disp1_ofs = 0x1e048000,
893 .dc_tmpl_ofs = 0x1f080000,
894 .vdi_ofs = 0x1e068000,
898 static struct ipu_devtype ipu_type_imx53 = {
900 .cm_ofs = 0x06000000,
901 .cpmem_ofs = 0x07000000,
902 .srm_ofs = 0x07040000,
903 .tpm_ofs = 0x07060000,
904 .csi0_ofs = 0x07030000,
905 .csi1_ofs = 0x07038000,
906 .ic_ofs = 0x06020000,
907 .disp0_ofs = 0x06040000,
908 .disp1_ofs = 0x06048000,
909 .dc_tmpl_ofs = 0x07080000,
910 .vdi_ofs = 0x06068000,
914 static struct ipu_devtype ipu_type_imx6q = {
916 .cm_ofs = 0x00200000,
917 .cpmem_ofs = 0x00300000,
918 .srm_ofs = 0x00340000,
919 .tpm_ofs = 0x00360000,
920 .csi0_ofs = 0x00230000,
921 .csi1_ofs = 0x00238000,
922 .ic_ofs = 0x00220000,
923 .disp0_ofs = 0x00240000,
924 .disp1_ofs = 0x00248000,
925 .dc_tmpl_ofs = 0x00380000,
926 .vdi_ofs = 0x00268000,
930 static const struct of_device_id imx_ipu_dt_ids[] = {
931 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
932 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
933 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
936 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
938 static int ipu_submodules_init(struct ipu_soc *ipu,
939 struct platform_device *pdev, unsigned long ipu_base,
944 struct device *dev = &pdev->dev;
945 const struct ipu_devtype *devtype = ipu->devtype;
947 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
953 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
954 IPU_CONF_CSI0_EN, ipu_clk);
960 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
961 IPU_CONF_CSI1_EN, ipu_clk);
967 ret = ipu_ic_init(ipu, dev,
968 ipu_base + devtype->ic_ofs,
969 ipu_base + devtype->tpm_ofs);
975 ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs,
976 IPU_CONF_VDI_EN | IPU_CONF_ISP_EN |
983 ret = ipu_image_convert_init(ipu, dev);
985 unit = "image_convert";
986 goto err_image_convert;
989 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
990 IPU_CONF_DI0_EN, ipu_clk);
996 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
997 IPU_CONF_DI1_EN, ipu_clk);
1003 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
1004 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
1006 unit = "dc_template";
1010 ret = ipu_dmfc_init(ipu, dev, ipu_base +
1011 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
1017 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
1023 ret = ipu_smfc_init(ipu, dev, ipu_base +
1024 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
1039 ipu_di_exit(ipu, 1);
1041 ipu_di_exit(ipu, 0);
1043 ipu_image_convert_exit(ipu);
1049 ipu_csi_exit(ipu, 1);
1051 ipu_csi_exit(ipu, 0);
1053 ipu_cpmem_exit(ipu);
1055 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
1059 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
1061 unsigned long status;
1064 for (i = 0; i < num_regs; i++) {
1066 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
1067 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
1069 for_each_set_bit(bit, &status, 32) {
1070 irq = irq_linear_revmap(ipu->domain,
1071 regs[i] * 32 + bit);
1073 generic_handle_irq(irq);
1078 static void ipu_irq_handler(struct irq_desc *desc)
1080 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1081 struct irq_chip *chip = irq_desc_get_chip(desc);
1082 const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
1084 chained_irq_enter(chip, desc);
1086 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1088 chained_irq_exit(chip, desc);
1091 static void ipu_err_irq_handler(struct irq_desc *desc)
1093 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1094 struct irq_chip *chip = irq_desc_get_chip(desc);
1095 const int int_reg[] = { 4, 5, 8, 9};
1097 chained_irq_enter(chip, desc);
1099 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1101 chained_irq_exit(chip, desc);
1104 int ipu_map_irq(struct ipu_soc *ipu, int irq)
1108 virq = irq_linear_revmap(ipu->domain, irq);
1110 virq = irq_create_mapping(ipu->domain, irq);
1114 EXPORT_SYMBOL_GPL(ipu_map_irq);
1116 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
1117 enum ipu_channel_irq irq_type)
1119 return ipu_map_irq(ipu, irq_type + channel->num);
1121 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
1123 static void ipu_submodules_exit(struct ipu_soc *ipu)
1129 ipu_di_exit(ipu, 1);
1130 ipu_di_exit(ipu, 0);
1131 ipu_image_convert_exit(ipu);
1134 ipu_csi_exit(ipu, 1);
1135 ipu_csi_exit(ipu, 0);
1136 ipu_cpmem_exit(ipu);
1139 static int platform_remove_devices_fn(struct device *dev, void *unused)
1141 struct platform_device *pdev = to_platform_device(dev);
1143 platform_device_unregister(pdev);
1148 static void platform_device_unregister_children(struct platform_device *pdev)
1150 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
1153 struct ipu_platform_reg {
1154 struct ipu_client_platformdata pdata;
1158 /* These must be in the order of the corresponding device tree port nodes */
1159 static struct ipu_platform_reg client_reg[] = {
1163 .dma[0] = IPUV3_CHANNEL_CSI0,
1166 .name = "imx-ipuv3-csi",
1170 .dma[0] = IPUV3_CHANNEL_CSI1,
1173 .name = "imx-ipuv3-csi",
1178 .dp = IPU_DP_FLOW_SYNC_BG,
1179 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
1180 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
1182 .name = "imx-ipuv3-crtc",
1188 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
1191 .name = "imx-ipuv3-crtc",
1195 static DEFINE_MUTEX(ipu_client_id_mutex);
1196 static int ipu_client_id;
1198 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
1200 struct device *dev = ipu->dev;
1204 mutex_lock(&ipu_client_id_mutex);
1206 ipu_client_id += ARRAY_SIZE(client_reg);
1207 mutex_unlock(&ipu_client_id_mutex);
1209 for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
1210 struct ipu_platform_reg *reg = &client_reg[i];
1211 struct platform_device *pdev;
1212 struct device_node *of_node;
1214 /* Associate subdevice with the corresponding port node */
1215 of_node = of_graph_get_port_by_id(dev->of_node, i);
1218 "no port@%d node in %s, not using %s%d\n",
1219 i, dev->of_node->full_name,
1220 (i / 2) ? "DI" : "CSI", i % 2);
1224 pdev = platform_device_alloc(reg->name, id++);
1230 pdev->dev.parent = dev;
1232 reg->pdata.of_node = of_node;
1233 ret = platform_device_add_data(pdev, ®->pdata,
1234 sizeof(reg->pdata));
1236 ret = platform_device_add(pdev);
1238 platform_device_put(pdev);
1246 platform_device_unregister_children(to_platform_device(dev));
1252 static int ipu_irq_init(struct ipu_soc *ipu)
1254 struct irq_chip_generic *gc;
1255 struct irq_chip_type *ct;
1256 unsigned long unused[IPU_NUM_IRQS / 32] = {
1257 0x400100d0, 0xffe000fd,
1258 0x400100d0, 0xffe000fd,
1259 0x400100d0, 0xffe000fd,
1260 0x4077ffff, 0xffe7e1fd,
1261 0x23fffffe, 0x8880fff0,
1262 0xf98fe7d0, 0xfff81fff,
1263 0x400100d0, 0xffe000fd,
1268 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
1269 &irq_generic_chip_ops, ipu);
1271 dev_err(ipu->dev, "failed to add irq domain\n");
1275 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1276 handle_level_irq, 0, 0, 0);
1278 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1279 irq_domain_remove(ipu->domain);
1283 /* Mask and clear all interrupts */
1284 for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1285 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
1286 ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32));
1289 for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1290 gc = irq_get_domain_generic_chip(ipu->domain, i);
1291 gc->reg_base = ipu->cm_reg;
1292 gc->unused = unused[i / 32];
1293 ct = gc->chip_types;
1294 ct->chip.irq_ack = irq_gc_ack_set_bit;
1295 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1296 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1297 ct->regs.ack = IPU_INT_STAT(i / 32);
1298 ct->regs.mask = IPU_INT_CTRL(i / 32);
1301 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
1302 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
1308 static void ipu_irq_exit(struct ipu_soc *ipu)
1312 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
1313 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
1315 /* TODO: remove irq_domain_generic_chips */
1317 for (i = 0; i < IPU_NUM_IRQS; i++) {
1318 irq = irq_linear_revmap(ipu->domain, i);
1320 irq_dispose_mapping(irq);
1323 irq_domain_remove(ipu->domain);
1326 void ipu_dump(struct ipu_soc *ipu)
1330 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
1331 ipu_cm_read(ipu, IPU_CONF));
1332 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
1333 ipu_idmac_read(ipu, IDMAC_CONF));
1334 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
1335 ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
1336 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
1337 ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
1338 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1339 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
1340 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1341 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
1342 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
1343 ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
1344 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
1345 ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
1346 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1347 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
1348 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1349 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
1350 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1351 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
1352 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1353 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
1354 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1355 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
1356 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1357 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
1358 for (i = 0; i < 15; i++)
1359 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
1360 ipu_cm_read(ipu, IPU_INT_CTRL(i)));
1362 EXPORT_SYMBOL_GPL(ipu_dump);
1364 static int ipu_probe(struct platform_device *pdev)
1366 struct device_node *np = pdev->dev.of_node;
1367 struct ipu_soc *ipu;
1368 struct resource *res;
1369 unsigned long ipu_base;
1370 int i, ret, irq_sync, irq_err;
1371 const struct ipu_devtype *devtype;
1373 devtype = of_device_get_match_data(&pdev->dev);
1377 irq_sync = platform_get_irq(pdev, 0);
1378 irq_err = platform_get_irq(pdev, 1);
1379 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1381 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
1384 if (!res || irq_sync < 0 || irq_err < 0)
1387 ipu_base = res->start;
1389 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1393 for (i = 0; i < 64; i++)
1394 ipu->channel[i].ipu = ipu;
1395 ipu->devtype = devtype;
1396 ipu->ipu_type = devtype->type;
1397 ipu->id = of_alias_get_id(np, "ipu");
1399 spin_lock_init(&ipu->lock);
1400 mutex_init(&ipu->channel_lock);
1402 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
1403 ipu_base + devtype->cm_ofs);
1404 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n",
1405 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1406 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
1407 ipu_base + devtype->cpmem_ofs);
1408 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n",
1409 ipu_base + devtype->csi0_ofs);
1410 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n",
1411 ipu_base + devtype->csi1_ofs);
1412 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1413 ipu_base + devtype->ic_ofs);
1414 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
1415 ipu_base + devtype->disp0_ofs);
1416 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
1417 ipu_base + devtype->disp1_ofs);
1418 dev_dbg(&pdev->dev, "srm: 0x%08lx\n",
1419 ipu_base + devtype->srm_ofs);
1420 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n",
1421 ipu_base + devtype->tpm_ofs);
1422 dev_dbg(&pdev->dev, "dc: 0x%08lx\n",
1423 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1424 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1425 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1426 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n",
1427 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1428 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n",
1429 ipu_base + devtype->vdi_ofs);
1431 ipu->cm_reg = devm_ioremap(&pdev->dev,
1432 ipu_base + devtype->cm_ofs, PAGE_SIZE);
1433 ipu->idmac_reg = devm_ioremap(&pdev->dev,
1434 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1437 if (!ipu->cm_reg || !ipu->idmac_reg)
1440 ipu->clk = devm_clk_get(&pdev->dev, "bus");
1441 if (IS_ERR(ipu->clk)) {
1442 ret = PTR_ERR(ipu->clk);
1443 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1447 platform_set_drvdata(pdev, ipu);
1449 ret = clk_prepare_enable(ipu->clk);
1451 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1455 ipu->dev = &pdev->dev;
1456 ipu->irq_sync = irq_sync;
1457 ipu->irq_err = irq_err;
1459 ret = device_reset(&pdev->dev);
1461 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1462 goto out_failed_reset;
1464 ret = ipu_memory_reset(ipu);
1466 goto out_failed_reset;
1468 ret = ipu_irq_init(ipu);
1470 goto out_failed_irq;
1472 /* Set MCU_T to divide MCU access window into 2 */
1473 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1476 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1478 goto failed_submodules_init;
1480 ret = ipu_add_client_devices(ipu, ipu_base);
1482 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1484 goto failed_add_clients;
1487 dev_info(&pdev->dev, "%s probed\n", devtype->name);
1492 ipu_submodules_exit(ipu);
1493 failed_submodules_init:
1497 clk_disable_unprepare(ipu->clk);
1501 static int ipu_remove(struct platform_device *pdev)
1503 struct ipu_soc *ipu = platform_get_drvdata(pdev);
1505 platform_device_unregister_children(pdev);
1506 ipu_submodules_exit(ipu);
1509 clk_disable_unprepare(ipu->clk);
1514 static struct platform_driver imx_ipu_driver = {
1516 .name = "imx-ipuv3",
1517 .of_match_table = imx_ipu_dt_ids,
1520 .remove = ipu_remove,
1523 module_platform_driver(imx_ipu_driver);
1525 MODULE_ALIAS("platform:imx-ipuv3");
1526 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1527 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1528 MODULE_LICENSE("GPL");