drivers/gpu/ipu-v3/ipu-common.c

   1 /*
   2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
   3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/export.h>
  17 #include <linux/types.h>
  18 #include <linux/reset.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/err.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/delay.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/clk.h>
  26 #include <linux/list.h>
  27 #include <linux/irq.h>
  28 #include <linux/irqchip/chained_irq.h>
  29 #include <linux/irqdomain.h>
  30 #include <linux/of_device.h>
  31 #include <linux/of_graph.h>
  32
  33 #include <drm/drm_fourcc.h>
  34
  35 #include <video/imx-ipu-v3.h>
  36 #include "ipu-prv.h"
  37
  38 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
  39 {
  40         return readl(ipu->cm_reg + offset);
  41 }
  42
  43 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
  44 {
  45         writel(value, ipu->cm_reg + offset);
  46 }
  47
  48 int ipu_get_num(struct ipu_soc *ipu)
  49 {
  50         return ipu->id;
  51 }
  52 EXPORT_SYMBOL_GPL(ipu_get_num);
  53
  54 void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
  55 {
  56         u32 val;
  57
  58         val = ipu_cm_read(ipu, IPU_SRM_PRI2);
  59         val |= 0x8;
  60         ipu_cm_write(ipu, val, IPU_SRM_PRI2);
  61 }
  62 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
  63
  64 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
  65 {
  66         switch (drm_fourcc) {
  67         case DRM_FORMAT_ARGB1555:
  68         case DRM_FORMAT_ABGR1555:
  69         case DRM_FORMAT_RGBA5551:
  70         case DRM_FORMAT_BGRA5551:
  71         case DRM_FORMAT_RGB565:
  72         case DRM_FORMAT_BGR565:
  73         case DRM_FORMAT_RGB888:
  74         case DRM_FORMAT_BGR888:
  75         case DRM_FORMAT_ARGB4444:
  76         case DRM_FORMAT_XRGB8888:
  77         case DRM_FORMAT_XBGR8888:
  78         case DRM_FORMAT_RGBX8888:
  79         case DRM_FORMAT_BGRX8888:
  80         case DRM_FORMAT_ARGB8888:
  81         case DRM_FORMAT_ABGR8888:
  82         case DRM_FORMAT_RGBA8888:
  83         case DRM_FORMAT_BGRA8888:
  84                 return IPUV3_COLORSPACE_RGB;
  85         case DRM_FORMAT_YUYV:
  86         case DRM_FORMAT_UYVY:
  87         case DRM_FORMAT_YUV420:
  88         case DRM_FORMAT_YVU420:
  89         case DRM_FORMAT_YUV422:
  90         case DRM_FORMAT_YVU422:
  91         case DRM_FORMAT_YUV444:
  92         case DRM_FORMAT_YVU444:
  93         case DRM_FORMAT_NV12:
  94         case DRM_FORMAT_NV21:
  95         case DRM_FORMAT_NV16:
  96         case DRM_FORMAT_NV61:
  97                 return IPUV3_COLORSPACE_YUV;
  98         default:
  99                 return IPUV3_COLORSPACE_UNKNOWN;
 100         }
 101 }
 102 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
 103
 104 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
 105 {
 106         switch (pixelformat) {
 107         case V4L2_PIX_FMT_YUV420:
 108         case V4L2_PIX_FMT_YVU420:
 109         case V4L2_PIX_FMT_YUV422P:
 110         case V4L2_PIX_FMT_UYVY:
 111         case V4L2_PIX_FMT_YUYV:
 112         case V4L2_PIX_FMT_NV12:
 113         case V4L2_PIX_FMT_NV21:
 114         case V4L2_PIX_FMT_NV16:
 115         case V4L2_PIX_FMT_NV61:
 116                 return IPUV3_COLORSPACE_YUV;
 117         case V4L2_PIX_FMT_RGB32:
 118         case V4L2_PIX_FMT_BGR32:
 119         case V4L2_PIX_FMT_RGB24:
 120         case V4L2_PIX_FMT_BGR24:
 121         case V4L2_PIX_FMT_RGB565:
 122                 return IPUV3_COLORSPACE_RGB;
 123         default:
 124                 return IPUV3_COLORSPACE_UNKNOWN;
 125         }
 126 }
 127 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
 128
 129 bool ipu_pixelformat_is_planar(u32 pixelformat)
 130 {
 131         switch (pixelformat) {
 132         case V4L2_PIX_FMT_YUV420:
 133         case V4L2_PIX_FMT_YVU420:
 134         case V4L2_PIX_FMT_YUV422P:
 135         case V4L2_PIX_FMT_NV12:
 136         case V4L2_PIX_FMT_NV21:
 137         case V4L2_PIX_FMT_NV16:
 138         case V4L2_PIX_FMT_NV61:
 139                 return true;
 140         }
 141
 142         return false;
 143 }
 144 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
 145
 146 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
 147 {
 148         switch (mbus_code & 0xf000) {
 149         case 0x1000:
 150                 return IPUV3_COLORSPACE_RGB;
 151         case 0x2000:
 152                 return IPUV3_COLORSPACE_YUV;
 153         default:
 154                 return IPUV3_COLORSPACE_UNKNOWN;
 155         }
 156 }
 157 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
 158
 159 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
 160 {
 161         switch (pixelformat) {
 162         case V4L2_PIX_FMT_YUV420:
 163         case V4L2_PIX_FMT_YVU420:
 164         case V4L2_PIX_FMT_YUV422P:
 165         case V4L2_PIX_FMT_NV12:
 166         case V4L2_PIX_FMT_NV21:
 167         case V4L2_PIX_FMT_NV16:
 168         case V4L2_PIX_FMT_NV61:
 169                 /*
 170                  * for the planar YUV formats, the stride passed to
 171                  * cpmem must be the stride in bytes of the Y plane.
 172                  * And all the planar YUV formats have an 8-bit
 173                  * Y component.
 174                  */
 175                 return (8 * pixel_stride) >> 3;
 176         case V4L2_PIX_FMT_RGB565:
 177         case V4L2_PIX_FMT_YUYV:
 178         case V4L2_PIX_FMT_UYVY:
 179                 return (16 * pixel_stride) >> 3;
 180         case V4L2_PIX_FMT_BGR24:
 181         case V4L2_PIX_FMT_RGB24:
 182                 return (24 * pixel_stride) >> 3;
 183         case V4L2_PIX_FMT_BGR32:
 184         case V4L2_PIX_FMT_RGB32:
 185                 return (32 * pixel_stride) >> 3;
 186         default:
 187                 break;
 188         }
 189
 190         return -EINVAL;
 191 }
 192 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
 193
 194 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
 195                             bool hflip, bool vflip)
 196 {
 197         u32 r90, vf, hf;
 198
 199         switch (degrees) {
 200         case 0:
 201                 vf = hf = r90 = 0;
 202                 break;
 203         case 90:
 204                 vf = hf = 0;
 205                 r90 = 1;
 206                 break;
 207         case 180:
 208                 vf = hf = 1;
 209                 r90 = 0;
 210                 break;
 211         case 270:
 212                 vf = hf = r90 = 1;
 213                 break;
 214         default:
 215                 return -EINVAL;
 216         }
 217
 218         hf ^= (u32)hflip;
 219         vf ^= (u32)vflip;
 220
 221         *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
 222         return 0;
 223 }
 224 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
 225
 226 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
 227                             bool hflip, bool vflip)
 228 {
 229         u32 r90, vf, hf;
 230
 231         r90 = ((u32)mode >> 2) & 0x1;
 232         hf = ((u32)mode >> 1) & 0x1;
 233         vf = ((u32)mode >> 0) & 0x1;
 234         hf ^= (u32)hflip;
 235         vf ^= (u32)vflip;
 236
 237         switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
 238         case IPU_ROTATE_NONE:
 239                 *degrees = 0;
 240                 break;
 241         case IPU_ROTATE_90_RIGHT:
 242                 *degrees = 90;
 243                 break;
 244         case IPU_ROTATE_180:
 245                 *degrees = 180;
 246                 break;
 247         case IPU_ROTATE_90_LEFT:
 248                 *degrees = 270;
 249                 break;
 250         default:
 251                 return -EINVAL;
 252         }
 253
 254         return 0;
 255 }
 256 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
 257
 258 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
 259 {
 260         struct ipuv3_channel *channel;
 261
 262         dev_dbg(ipu->dev, "%s %d\n", __func__, num);
 263
 264         if (num > 63)
 265                 return ERR_PTR(-ENODEV);
 266
 267         mutex_lock(&ipu->channel_lock);
 268
 269         channel = &ipu->channel[num];
 270
 271         if (channel->busy) {
 272                 channel = ERR_PTR(-EBUSY);
 273                 goto out;
 274         }
 275
 276         channel->busy = true;
 277         channel->num = num;
 278
 279 out:
 280         mutex_unlock(&ipu->channel_lock);
 281
 282         return channel;
 283 }
 284 EXPORT_SYMBOL_GPL(ipu_idmac_get);
 285
 286 void ipu_idmac_put(struct ipuv3_channel *channel)
 287 {
 288         struct ipu_soc *ipu = channel->ipu;
 289
 290         dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
 291
 292         mutex_lock(&ipu->channel_lock);
 293
 294         channel->busy = false;
 295
 296         mutex_unlock(&ipu->channel_lock);
 297 }
 298 EXPORT_SYMBOL_GPL(ipu_idmac_put);
 299
 300 #define idma_mask(ch)                   (1 << ((ch) & 0x1f))
 301
 302 /*
 303  * This is an undocumented feature, a write one to a channel bit in
 304  * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
 305  * internal current buffer pointer so that transfers start from buffer
 306  * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
 307  * only says these are read-only registers). This operation is required
 308  * for channel linking to work correctly, for instance video capture
 309  * pipelines that carry out image rotations will fail after the first
 310  * streaming unless this function is called for each channel before
 311  * re-enabling the channels.
 312  */
 313 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
 314 {
 315         struct ipu_soc *ipu = channel->ipu;
 316         unsigned int chno = channel->num;
 317
 318         ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
 319 }
 320
 321 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
 322                 bool doublebuffer)
 323 {
 324         struct ipu_soc *ipu = channel->ipu;
 325         unsigned long flags;
 326         u32 reg;
 327
 328         spin_lock_irqsave(&ipu->lock, flags);
 329
 330         reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 331         if (doublebuffer)
 332                 reg |= idma_mask(channel->num);
 333         else
 334                 reg &= ~idma_mask(channel->num);
 335         ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
 336
 337         __ipu_idmac_reset_current_buffer(channel);
 338
 339         spin_unlock_irqrestore(&ipu->lock, flags);
 340 }
 341 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
 342
 343 static const struct {
 344         int chnum;
 345         u32 reg;
 346         int shift;
 347 } idmac_lock_en_info[] = {
 348         { .chnum =  5, .reg = IDMAC_CH_LOCK_EN_1, .shift =  0, },
 349         { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift =  2, },
 350         { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift =  4, },
 351         { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift =  6, },
 352         { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift =  8, },
 353         { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
 354         { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
 355         { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
 356         { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
 357         { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
 358         { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
 359         { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift =  0, },
 360         { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift =  2, },
 361         { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift =  4, },
 362         { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift =  6, },
 363         { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift =  8, },
 364         { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
 365 };
 366
 367 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
 368 {
 369         struct ipu_soc *ipu = channel->ipu;
 370         unsigned long flags;
 371         u32 bursts, regval;
 372         int i;
 373
 374         switch (num_bursts) {
 375         case 0:
 376         case 1:
 377                 bursts = 0x00; /* locking disabled */
 378                 break;
 379         case 2:
 380                 bursts = 0x01;
 381                 break;
 382         case 4:
 383                 bursts = 0x02;
 384                 break;
 385         case 8:
 386                 bursts = 0x03;
 387                 break;
 388         default:
 389                 return -EINVAL;
 390         }
 391
 392         for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
 393                 if (channel->num == idmac_lock_en_info[i].chnum)
 394                         break;
 395         }
 396         if (i >= ARRAY_SIZE(idmac_lock_en_info))
 397                 return -EINVAL;
 398
 399         spin_lock_irqsave(&ipu->lock, flags);
 400
 401         regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
 402         regval &= ~(0x03 << idmac_lock_en_info[i].shift);
 403         regval |= (bursts << idmac_lock_en_info[i].shift);
 404         ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
 405
 406         spin_unlock_irqrestore(&ipu->lock, flags);
 407
 408         return 0;
 409 }
 410 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
 411
 412 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
 413 {
 414         unsigned long lock_flags;
 415         u32 val;
 416
 417         spin_lock_irqsave(&ipu->lock, lock_flags);
 418
 419         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 420
 421         if (mask & IPU_CONF_DI0_EN)
 422                 val |= IPU_DI0_COUNTER_RELEASE;
 423         if (mask & IPU_CONF_DI1_EN)
 424                 val |= IPU_DI1_COUNTER_RELEASE;
 425
 426         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 427
 428         val = ipu_cm_read(ipu, IPU_CONF);
 429         val |= mask;
 430         ipu_cm_write(ipu, val, IPU_CONF);
 431
 432         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 433
 434         return 0;
 435 }
 436 EXPORT_SYMBOL_GPL(ipu_module_enable);
 437
 438 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
 439 {
 440         unsigned long lock_flags;
 441         u32 val;
 442
 443         spin_lock_irqsave(&ipu->lock, lock_flags);
 444
 445         val = ipu_cm_read(ipu, IPU_CONF);
 446         val &= ~mask;
 447         ipu_cm_write(ipu, val, IPU_CONF);
 448
 449         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 450
 451         if (mask & IPU_CONF_DI0_EN)
 452                 val &= ~IPU_DI0_COUNTER_RELEASE;
 453         if (mask & IPU_CONF_DI1_EN)
 454                 val &= ~IPU_DI1_COUNTER_RELEASE;
 455
 456         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 457
 458         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 459
 460         return 0;
 461 }
 462 EXPORT_SYMBOL_GPL(ipu_module_disable);
 463
 464 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
 465 {
 466         struct ipu_soc *ipu = channel->ipu;
 467         unsigned int chno = channel->num;
 468
 469         return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
 470 }
 471 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
 472
 473 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
 474 {
 475         struct ipu_soc *ipu = channel->ipu;
 476         unsigned long flags;
 477         u32 reg = 0;
 478
 479         spin_lock_irqsave(&ipu->lock, flags);
 480         switch (buf_num) {
 481         case 0:
 482                 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
 483                 break;
 484         case 1:
 485                 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
 486                 break;
 487         case 2:
 488                 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
 489                 break;
 490         }
 491         spin_unlock_irqrestore(&ipu->lock, flags);
 492
 493         return ((reg & idma_mask(channel->num)) != 0);
 494 }
 495 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
 496
 497 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
 498 {
 499         struct ipu_soc *ipu = channel->ipu;
 500         unsigned int chno = channel->num;
 501         unsigned long flags;
 502
 503         spin_lock_irqsave(&ipu->lock, flags);
 504
 505         /* Mark buffer as ready. */
 506         if (buf_num == 0)
 507                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
 508         else
 509                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
 510
 511         spin_unlock_irqrestore(&ipu->lock, flags);
 512 }
 513 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
 514
 515 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
 516 {
 517         struct ipu_soc *ipu = channel->ipu;
 518         unsigned int chno = channel->num;
 519         unsigned long flags;
 520
 521         spin_lock_irqsave(&ipu->lock, flags);
 522
 523         ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
 524         switch (buf_num) {
 525         case 0:
 526                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
 527                 break;
 528         case 1:
 529                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
 530                 break;
 531         case 2:
 532                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
 533                 break;
 534         default:
 535                 break;
 536         }
 537         ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
 538
 539         spin_unlock_irqrestore(&ipu->lock, flags);
 540 }
 541 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
 542
 543 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
 544 {
 545         struct ipu_soc *ipu = channel->ipu;
 546         u32 val;
 547         unsigned long flags;
 548
 549         spin_lock_irqsave(&ipu->lock, flags);
 550
 551         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 552         val |= idma_mask(channel->num);
 553         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 554
 555         spin_unlock_irqrestore(&ipu->lock, flags);
 556
 557         return 0;
 558 }
 559 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
 560
 561 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
 562 {
 563         return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
 564 }
 565 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
 566
 567 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
 568 {
 569         struct ipu_soc *ipu = channel->ipu;
 570         unsigned long timeout;
 571
 572         timeout = jiffies + msecs_to_jiffies(ms);
 573         while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
 574                         idma_mask(channel->num)) {
 575                 if (time_after(jiffies, timeout))
 576                         return -ETIMEDOUT;
 577                 cpu_relax();
 578         }
 579
 580         return 0;
 581 }
 582 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
 583
 584 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
 585 {
 586         unsigned long timeout;
 587
 588         timeout = jiffies + msecs_to_jiffies(ms);
 589         ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
 590         while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
 591                 if (time_after(jiffies, timeout))
 592                         return -ETIMEDOUT;
 593                 cpu_relax();
 594         }
 595
 596         return 0;
 597 }
 598 EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
 599
 600 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
 601 {
 602         struct ipu_soc *ipu = channel->ipu;
 603         u32 val;
 604         unsigned long flags;
 605
 606         spin_lock_irqsave(&ipu->lock, flags);
 607
 608         /* Disable DMA channel(s) */
 609         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 610         val &= ~idma_mask(channel->num);
 611         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 612
 613         __ipu_idmac_reset_current_buffer(channel);
 614
 615         /* Set channel buffers NOT to be ready */
 616         ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
 617
 618         if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
 619                         idma_mask(channel->num)) {
 620                 ipu_cm_write(ipu, idma_mask(channel->num),
 621                              IPU_CHA_BUF0_RDY(channel->num));
 622         }
 623
 624         if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
 625                         idma_mask(channel->num)) {
 626                 ipu_cm_write(ipu, idma_mask(channel->num),
 627                              IPU_CHA_BUF1_RDY(channel->num));
 628         }
 629
 630         ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
 631
 632         /* Reset the double buffer */
 633         val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 634         val &= ~idma_mask(channel->num);
 635         ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
 636
 637         spin_unlock_irqrestore(&ipu->lock, flags);
 638
 639         return 0;
 640 }
 641 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
 642
 643 /*
 644  * The imx6 rev. D TRM says that enabling the WM feature will increase
 645  * a channel's priority. Refer to Table 36-8 Calculated priority value.
 646  * The sub-module that is the sink or source for the channel must enable
 647  * watermark signal for this to take effect (SMFC_WM for instance).
 648  */
 649 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
 650 {
 651         struct ipu_soc *ipu = channel->ipu;
 652         unsigned long flags;
 653         u32 val;
 654
 655         spin_lock_irqsave(&ipu->lock, flags);
 656
 657         val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
 658         if (enable)
 659                 val |= 1 << (channel->num % 32);
 660         else
 661                 val &= ~(1 << (channel->num % 32));
 662         ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
 663
 664         spin_unlock_irqrestore(&ipu->lock, flags);
 665 }
 666 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
 667
 668 static int ipu_memory_reset(struct ipu_soc *ipu)
 669 {
 670         unsigned long timeout;
 671
 672         ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
 673
 674         timeout = jiffies + msecs_to_jiffies(1000);
 675         while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
 676                 if (time_after(jiffies, timeout))
 677                         return -ETIME;
 678                 cpu_relax();
 679         }
 680
 681         return 0;
 682 }
 683
 684 /*
 685  * Set the source mux for the given CSI. Selects either parallel or
 686  * MIPI CSI2 sources.
 687  */
 688 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
 689 {
 690         unsigned long flags;
 691         u32 val, mask;
 692
 693         mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
 694                 IPU_CONF_CSI0_DATA_SOURCE;
 695
 696         spin_lock_irqsave(&ipu->lock, flags);
 697
 698         val = ipu_cm_read(ipu, IPU_CONF);
 699         if (mipi_csi2)
 700                 val |= mask;
 701         else
 702                 val &= ~mask;
 703         ipu_cm_write(ipu, val, IPU_CONF);
 704
 705         spin_unlock_irqrestore(&ipu->lock, flags);
 706 }
 707 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
 708
 709 /*
 710  * Set the source mux for the IC. Selects either CSI[01] or the VDI.
 711  */
 712 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
 713 {
 714         unsigned long flags;
 715         u32 val;
 716
 717         spin_lock_irqsave(&ipu->lock, flags);
 718
 719         val = ipu_cm_read(ipu, IPU_CONF);
 720         if (vdi) {
 721                 val |= IPU_CONF_IC_INPUT;
 722         } else {
 723                 val &= ~IPU_CONF_IC_INPUT;
 724                 if (csi_id == 1)
 725                         val |= IPU_CONF_CSI_SEL;
 726                 else
 727                         val &= ~IPU_CONF_CSI_SEL;
 728         }
 729         ipu_cm_write(ipu, val, IPU_CONF);
 730
 731         spin_unlock_irqrestore(&ipu->lock, flags);
 732 }
 733 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
 734
 735
 736 /* Frame Synchronization Unit Channel Linking */
 737
 738 struct fsu_link_reg_info {
 739         int chno;
 740         u32 reg;
 741         u32 mask;
 742         u32 val;
 743 };
 744
 745 struct fsu_link_info {
 746         struct fsu_link_reg_info src;
 747         struct fsu_link_reg_info sink;
 748 };
 749
 750 static const struct fsu_link_info fsu_link_info[] = {
 751         {
 752                 .src  = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2,
 753                           FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC },
 754                 .sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1,
 755                           FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC },
 756         }, {
 757                 .src =  { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2,
 758                           FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF },
 759                 .sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1,
 760                           FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF },
 761         }, {
 762                 .src =  { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2,
 763                           FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP },
 764                 .sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1,
 765                           FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP },
 766         }, {
 767                 .src =  { IPUV3_CHANNEL_CSI_DIRECT, 0 },
 768                 .sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1,
 769                           FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT },
 770         },
 771 };
 772
 773 static const struct fsu_link_info *find_fsu_link_info(int src, int sink)
 774 {
 775         int i;
 776
 777         for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) {
 778                 if (src == fsu_link_info[i].src.chno &&
 779                     sink == fsu_link_info[i].sink.chno)
 780                         return &fsu_link_info[i];
 781         }
 782
 783         return NULL;
 784 }
 785
 786 /*
 787  * Links a source channel to a sink channel in the FSU.
 788  */
 789 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch)
 790 {
 791         const struct fsu_link_info *link;
 792         u32 src_reg, sink_reg;
 793         unsigned long flags;
 794
 795         link = find_fsu_link_info(src_ch, sink_ch);
 796         if (!link)
 797                 return -EINVAL;
 798
 799         spin_lock_irqsave(&ipu->lock, flags);
 800
 801         if (link->src.mask) {
 802                 src_reg = ipu_cm_read(ipu, link->src.reg);
 803                 src_reg &= ~link->src.mask;
 804                 src_reg |= link->src.val;
 805                 ipu_cm_write(ipu, src_reg, link->src.reg);
 806         }
 807
 808         if (link->sink.mask) {
 809                 sink_reg = ipu_cm_read(ipu, link->sink.reg);
 810                 sink_reg &= ~link->sink.mask;
 811                 sink_reg |= link->sink.val;
 812                 ipu_cm_write(ipu, sink_reg, link->sink.reg);
 813         }
 814
 815         spin_unlock_irqrestore(&ipu->lock, flags);
 816         return 0;
 817 }
 818 EXPORT_SYMBOL_GPL(ipu_fsu_link);
 819
 820 /*
 821  * Unlinks source and sink channels in the FSU.
 822  */
 823 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch)
 824 {
 825         const struct fsu_link_info *link;
 826         u32 src_reg, sink_reg;
 827         unsigned long flags;
 828
 829         link = find_fsu_link_info(src_ch, sink_ch);
 830         if (!link)
 831                 return -EINVAL;
 832
 833         spin_lock_irqsave(&ipu->lock, flags);
 834
 835         if (link->src.mask) {
 836                 src_reg = ipu_cm_read(ipu, link->src.reg);
 837                 src_reg &= ~link->src.mask;
 838                 ipu_cm_write(ipu, src_reg, link->src.reg);
 839         }
 840
 841         if (link->sink.mask) {
 842                 sink_reg = ipu_cm_read(ipu, link->sink.reg);
 843                 sink_reg &= ~link->sink.mask;
 844                 ipu_cm_write(ipu, sink_reg, link->sink.reg);
 845         }
 846
 847         spin_unlock_irqrestore(&ipu->lock, flags);
 848         return 0;
 849 }
 850 EXPORT_SYMBOL_GPL(ipu_fsu_unlink);
 851
 852 /* Link IDMAC channels in the FSU */
 853 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink)
 854 {
 855         return ipu_fsu_link(src->ipu, src->num, sink->num);
 856 }
 857 EXPORT_SYMBOL_GPL(ipu_idmac_link);
 858
 859 /* Unlink IDMAC channels in the FSU */
 860 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink)
 861 {
 862         return ipu_fsu_unlink(src->ipu, src->num, sink->num);
 863 }
 864 EXPORT_SYMBOL_GPL(ipu_idmac_unlink);
 865
 866 struct ipu_devtype {
 867         const char *name;
 868         unsigned long cm_ofs;
 869         unsigned long cpmem_ofs;
 870         unsigned long srm_ofs;
 871         unsigned long tpm_ofs;
 872         unsigned long csi0_ofs;
 873         unsigned long csi1_ofs;
 874         unsigned long ic_ofs;
 875         unsigned long disp0_ofs;
 876         unsigned long disp1_ofs;
 877         unsigned long dc_tmpl_ofs;
 878         unsigned long vdi_ofs;
 879         enum ipuv3_type type;
 880 };
 881
 882 static struct ipu_devtype ipu_type_imx51 = {
 883         .name = "IPUv3EX",
 884         .cm_ofs = 0x1e000000,
 885         .cpmem_ofs = 0x1f000000,
 886         .srm_ofs = 0x1f040000,
 887         .tpm_ofs = 0x1f060000,
 888         .csi0_ofs = 0x1f030000,
 889         .csi1_ofs = 0x1f038000,
 890         .ic_ofs = 0x1e020000,
 891         .disp0_ofs = 0x1e040000,
 892         .disp1_ofs = 0x1e048000,
 893         .dc_tmpl_ofs = 0x1f080000,
 894         .vdi_ofs = 0x1e068000,
 895         .type = IPUV3EX,
 896 };
 897
 898 static struct ipu_devtype ipu_type_imx53 = {
 899         .name = "IPUv3M",
 900         .cm_ofs = 0x06000000,
 901         .cpmem_ofs = 0x07000000,
 902         .srm_ofs = 0x07040000,
 903         .tpm_ofs = 0x07060000,
 904         .csi0_ofs = 0x07030000,
 905         .csi1_ofs = 0x07038000,
 906         .ic_ofs = 0x06020000,
 907         .disp0_ofs = 0x06040000,
 908         .disp1_ofs = 0x06048000,
 909         .dc_tmpl_ofs = 0x07080000,
 910         .vdi_ofs = 0x06068000,
 911         .type = IPUV3M,
 912 };
 913
 914 static struct ipu_devtype ipu_type_imx6q = {
 915         .name = "IPUv3H",
 916         .cm_ofs = 0x00200000,
 917         .cpmem_ofs = 0x00300000,
 918         .srm_ofs = 0x00340000,
 919         .tpm_ofs = 0x00360000,
 920         .csi0_ofs = 0x00230000,
 921         .csi1_ofs = 0x00238000,
 922         .ic_ofs = 0x00220000,
 923         .disp0_ofs = 0x00240000,
 924         .disp1_ofs = 0x00248000,
 925         .dc_tmpl_ofs = 0x00380000,
 926         .vdi_ofs = 0x00268000,
 927         .type = IPUV3H,
 928 };
 929
 930 static const struct of_device_id imx_ipu_dt_ids[] = {
 931         { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
 932         { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
 933         { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
 934         { /* sentinel */ }
 935 };
 936 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
 937
 938 static int ipu_submodules_init(struct ipu_soc *ipu,
 939                 struct platform_device *pdev, unsigned long ipu_base,
 940                 struct clk *ipu_clk)
 941 {
 942         char *unit;
 943         int ret;
 944         struct device *dev = &pdev->dev;
 945         const struct ipu_devtype *devtype = ipu->devtype;
 946
 947         ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
 948         if (ret) {
 949                 unit = "cpmem";
 950                 goto err_cpmem;
 951         }
 952
 953         ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
 954                            IPU_CONF_CSI0_EN, ipu_clk);
 955         if (ret) {
 956                 unit = "csi0";
 957                 goto err_csi_0;
 958         }
 959
 960         ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
 961                            IPU_CONF_CSI1_EN, ipu_clk);
 962         if (ret) {
 963                 unit = "csi1";
 964                 goto err_csi_1;
 965         }
 966
 967         ret = ipu_ic_init(ipu, dev,
 968                           ipu_base + devtype->ic_ofs,
 969                           ipu_base + devtype->tpm_ofs);
 970         if (ret) {
 971                 unit = "ic";
 972                 goto err_ic;
 973         }
 974
 975         ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs,
 976                            IPU_CONF_VDI_EN | IPU_CONF_ISP_EN |
 977                            IPU_CONF_IC_INPUT);
 978         if (ret) {
 979                 unit = "vdi";
 980                 goto err_vdi;
 981         }
 982
 983         ret = ipu_image_convert_init(ipu, dev);
 984         if (ret) {
 985                 unit = "image_convert";
 986                 goto err_image_convert;
 987         }
 988
 989         ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
 990                           IPU_CONF_DI0_EN, ipu_clk);
 991         if (ret) {
 992                 unit = "di0";
 993                 goto err_di_0;
 994         }
 995
 996         ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
 997                         IPU_CONF_DI1_EN, ipu_clk);
 998         if (ret) {
 999                 unit = "di1";
1000                 goto err_di_1;
1001         }
1002
1003         ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
1004                         IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
1005         if (ret) {
1006                 unit = "dc_template";
1007                 goto err_dc;
1008         }
1009
1010         ret = ipu_dmfc_init(ipu, dev, ipu_base +
1011                         devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
1012         if (ret) {
1013                 unit = "dmfc";
1014                 goto err_dmfc;
1015         }
1016
1017         ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
1018         if (ret) {
1019                 unit = "dp";
1020                 goto err_dp;
1021         }
1022
1023         ret = ipu_smfc_init(ipu, dev, ipu_base +
1024                         devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
1025         if (ret) {
1026                 unit = "smfc";
1027                 goto err_smfc;
1028         }
1029
1030         return 0;
1031
1032 err_smfc:
1033         ipu_dp_exit(ipu);
1034 err_dp:
1035         ipu_dmfc_exit(ipu);
1036 err_dmfc:
1037         ipu_dc_exit(ipu);
1038 err_dc:
1039         ipu_di_exit(ipu, 1);
1040 err_di_1:
1041         ipu_di_exit(ipu, 0);
1042 err_di_0:
1043         ipu_image_convert_exit(ipu);
1044 err_image_convert:
1045         ipu_vdi_exit(ipu);
1046 err_vdi:
1047         ipu_ic_exit(ipu);
1048 err_ic:
1049         ipu_csi_exit(ipu, 1);
1050 err_csi_1:
1051         ipu_csi_exit(ipu, 0);
1052 err_csi_0:
1053         ipu_cpmem_exit(ipu);
1054 err_cpmem:
1055         dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
1056         return ret;
1057 }
1058
1059 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
1060 {
1061         unsigned long status;
1062         int i, bit, irq;
1063
1064         for (i = 0; i < num_regs; i++) {
1065
1066                 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
1067                 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
1068
1069                 for_each_set_bit(bit, &status, 32) {
1070                         irq = irq_linear_revmap(ipu->domain,
1071                                                 regs[i] * 32 + bit);
1072                         if (irq)
1073                                 generic_handle_irq(irq);
1074                 }
1075         }
1076 }
1077
1078 static void ipu_irq_handler(struct irq_desc *desc)
1079 {
1080         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1081         struct irq_chip *chip = irq_desc_get_chip(desc);
1082         const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
1083
1084         chained_irq_enter(chip, desc);
1085
1086         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1087
1088         chained_irq_exit(chip, desc);
1089 }
1090
1091 static void ipu_err_irq_handler(struct irq_desc *desc)
1092 {
1093         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1094         struct irq_chip *chip = irq_desc_get_chip(desc);
1095         const int int_reg[] = { 4, 5, 8, 9};
1096
1097         chained_irq_enter(chip, desc);
1098
1099         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1100
1101         chained_irq_exit(chip, desc);
1102 }
1103
1104 int ipu_map_irq(struct ipu_soc *ipu, int irq)
1105 {
1106         int virq;
1107
1108         virq = irq_linear_revmap(ipu->domain, irq);
1109         if (!virq)
1110                 virq = irq_create_mapping(ipu->domain, irq);
1111
1112         return virq;
1113 }
1114 EXPORT_SYMBOL_GPL(ipu_map_irq);
1115
1116 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
1117                 enum ipu_channel_irq irq_type)
1118 {
1119         return ipu_map_irq(ipu, irq_type + channel->num);
1120 }
1121 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
1122
1123 static void ipu_submodules_exit(struct ipu_soc *ipu)
1124 {
1125         ipu_smfc_exit(ipu);
1126         ipu_dp_exit(ipu);
1127         ipu_dmfc_exit(ipu);
1128         ipu_dc_exit(ipu);
1129         ipu_di_exit(ipu, 1);
1130         ipu_di_exit(ipu, 0);
1131         ipu_image_convert_exit(ipu);
1132         ipu_vdi_exit(ipu);
1133         ipu_ic_exit(ipu);
1134         ipu_csi_exit(ipu, 1);
1135         ipu_csi_exit(ipu, 0);
1136         ipu_cpmem_exit(ipu);
1137 }
1138
1139 static int platform_remove_devices_fn(struct device *dev, void *unused)
1140 {
1141         struct platform_device *pdev = to_platform_device(dev);
1142
1143         platform_device_unregister(pdev);
1144
1145         return 0;
1146 }
1147
1148 static void platform_device_unregister_children(struct platform_device *pdev)
1149 {
1150         device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
1151 }
1152
1153 struct ipu_platform_reg {
1154         struct ipu_client_platformdata pdata;
1155         const char *name;
1156 };
1157
1158 /* These must be in the order of the corresponding device tree port nodes */
1159 static struct ipu_platform_reg client_reg[] = {
1160         {
1161                 .pdata = {
1162                         .csi = 0,
1163                         .dma[0] = IPUV3_CHANNEL_CSI0,
1164                         .dma[1] = -EINVAL,
1165                 },
1166                 .name = "imx-ipuv3-csi",
1167         }, {
1168                 .pdata = {
1169                         .csi = 1,
1170                         .dma[0] = IPUV3_CHANNEL_CSI1,
1171                         .dma[1] = -EINVAL,
1172                 },
1173                 .name = "imx-ipuv3-csi",
1174         }, {
1175                 .pdata = {
1176                         .di = 0,
1177                         .dc = 5,
1178                         .dp = IPU_DP_FLOW_SYNC_BG,
1179                         .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
1180                         .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
1181                 },
1182                 .name = "imx-ipuv3-crtc",
1183         }, {
1184                 .pdata = {
1185                         .di = 1,
1186                         .dc = 1,
1187                         .dp = -EINVAL,
1188                         .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
1189                         .dma[1] = -EINVAL,
1190                 },
1191                 .name = "imx-ipuv3-crtc",
1192         },
1193 };
1194
1195 static DEFINE_MUTEX(ipu_client_id_mutex);
1196 static int ipu_client_id;
1197
1198 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
1199 {
1200         struct device *dev = ipu->dev;
1201         unsigned i;
1202         int id, ret;
1203
1204         mutex_lock(&ipu_client_id_mutex);
1205         id = ipu_client_id;
1206         ipu_client_id += ARRAY_SIZE(client_reg);
1207         mutex_unlock(&ipu_client_id_mutex);
1208
1209         for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
1210                 struct ipu_platform_reg *reg = &client_reg[i];
1211                 struct platform_device *pdev;
1212                 struct device_node *of_node;
1213
1214                 /* Associate subdevice with the corresponding port node */
1215                 of_node = of_graph_get_port_by_id(dev->of_node, i);
1216                 if (!of_node) {
1217                         dev_info(dev,
1218                                  "no port@%d node in %s, not using %s%d\n",
1219                                  i, dev->of_node->full_name,
1220                                  (i / 2) ? "DI" : "CSI", i % 2);
1221                         continue;
1222                 }
1223
1224                 pdev = platform_device_alloc(reg->name, id++);
1225                 if (!pdev) {
1226                         ret = -ENOMEM;
1227                         goto err_register;
1228                 }
1229
1230                 pdev->dev.parent = dev;
1231
1232                 reg->pdata.of_node = of_node;
1233                 ret = platform_device_add_data(pdev, &reg->pdata,
1234                                                sizeof(reg->pdata));
1235                 if (!ret)
1236                         ret = platform_device_add(pdev);
1237                 if (ret) {
1238                         platform_device_put(pdev);
1239                         goto err_register;
1240                 }
1241         }
1242
1243         return 0;
1244
1245 err_register:
1246         platform_device_unregister_children(to_platform_device(dev));
1247
1248         return ret;
1249 }
1250
1251
1252 static int ipu_irq_init(struct ipu_soc *ipu)
1253 {
1254         struct irq_chip_generic *gc;
1255         struct irq_chip_type *ct;
1256         unsigned long unused[IPU_NUM_IRQS / 32] = {
1257                 0x400100d0, 0xffe000fd,
1258                 0x400100d0, 0xffe000fd,
1259                 0x400100d0, 0xffe000fd,
1260                 0x4077ffff, 0xffe7e1fd,
1261                 0x23fffffe, 0x8880fff0,
1262                 0xf98fe7d0, 0xfff81fff,
1263                 0x400100d0, 0xffe000fd,
1264                 0x00000000,
1265         };
1266         int ret, i;
1267
1268         ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
1269                                             &irq_generic_chip_ops, ipu);
1270         if (!ipu->domain) {
1271                 dev_err(ipu->dev, "failed to add irq domain\n");
1272                 return -ENODEV;
1273         }
1274
1275         ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1276                                              handle_level_irq, 0, 0, 0);
1277         if (ret < 0) {
1278                 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1279                 irq_domain_remove(ipu->domain);
1280                 return ret;
1281         }
1282
1283         /* Mask and clear all interrupts */
1284         for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1285                 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
1286                 ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32));
1287         }
1288
1289         for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1290                 gc = irq_get_domain_generic_chip(ipu->domain, i);
1291                 gc->reg_base = ipu->cm_reg;
1292                 gc->unused = unused[i / 32];
1293                 ct = gc->chip_types;
1294                 ct->chip.irq_ack = irq_gc_ack_set_bit;
1295                 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1296                 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1297                 ct->regs.ack = IPU_INT_STAT(i / 32);
1298                 ct->regs.mask = IPU_INT_CTRL(i / 32);
1299         }
1300
1301         irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
1302         irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
1303                                          ipu);
1304
1305         return 0;
1306 }
1307
1308 static void ipu_irq_exit(struct ipu_soc *ipu)
1309 {
1310         int i, irq;
1311
1312         irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
1313         irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
1314
1315         /* TODO: remove irq_domain_generic_chips */
1316
1317         for (i = 0; i < IPU_NUM_IRQS; i++) {
1318                 irq = irq_linear_revmap(ipu->domain, i);
1319                 if (irq)
1320                         irq_dispose_mapping(irq);
1321         }
1322
1323         irq_domain_remove(ipu->domain);
1324 }
1325
1326 void ipu_dump(struct ipu_soc *ipu)
1327 {
1328         int i;
1329
1330         dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
1331                 ipu_cm_read(ipu, IPU_CONF));
1332         dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
1333                 ipu_idmac_read(ipu, IDMAC_CONF));
1334         dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
1335                 ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
1336         dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
1337                 ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
1338         dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1339                 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
1340         dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1341                 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
1342         dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
1343                 ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
1344         dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
1345                 ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
1346         dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1347                 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
1348         dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1349                 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
1350         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1351                 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
1352         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1353                 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
1354         dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1355                 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
1356         dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1357                 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
1358         for (i = 0; i < 15; i++)
1359                 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
1360                         ipu_cm_read(ipu, IPU_INT_CTRL(i)));
1361 }
1362 EXPORT_SYMBOL_GPL(ipu_dump);
1363
1364 static int ipu_probe(struct platform_device *pdev)
1365 {
1366         struct device_node *np = pdev->dev.of_node;
1367         struct ipu_soc *ipu;
1368         struct resource *res;
1369         unsigned long ipu_base;
1370         int i, ret, irq_sync, irq_err;
1371         const struct ipu_devtype *devtype;
1372
1373         devtype = of_device_get_match_data(&pdev->dev);
1374         if (!devtype)
1375                 return -EINVAL;
1376
1377         irq_sync = platform_get_irq(pdev, 0);
1378         irq_err = platform_get_irq(pdev, 1);
1379         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1380
1381         dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
1382                         irq_sync, irq_err);
1383
1384         if (!res || irq_sync < 0 || irq_err < 0)
1385                 return -ENODEV;
1386
1387         ipu_base = res->start;
1388
1389         ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1390         if (!ipu)
1391                 return -ENODEV;
1392
1393         for (i = 0; i < 64; i++)
1394                 ipu->channel[i].ipu = ipu;
1395         ipu->devtype = devtype;
1396         ipu->ipu_type = devtype->type;
1397         ipu->id = of_alias_get_id(np, "ipu");
1398
1399         spin_lock_init(&ipu->lock);
1400         mutex_init(&ipu->channel_lock);
1401
1402         dev_dbg(&pdev->dev, "cm_reg:   0x%08lx\n",
1403                         ipu_base + devtype->cm_ofs);
1404         dev_dbg(&pdev->dev, "idmac:    0x%08lx\n",
1405                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1406         dev_dbg(&pdev->dev, "cpmem:    0x%08lx\n",
1407                         ipu_base + devtype->cpmem_ofs);
1408         dev_dbg(&pdev->dev, "csi0:    0x%08lx\n",
1409                         ipu_base + devtype->csi0_ofs);
1410         dev_dbg(&pdev->dev, "csi1:    0x%08lx\n",
1411                         ipu_base + devtype->csi1_ofs);
1412         dev_dbg(&pdev->dev, "ic:      0x%08lx\n",
1413                         ipu_base + devtype->ic_ofs);
1414         dev_dbg(&pdev->dev, "disp0:    0x%08lx\n",
1415                         ipu_base + devtype->disp0_ofs);
1416         dev_dbg(&pdev->dev, "disp1:    0x%08lx\n",
1417                         ipu_base + devtype->disp1_ofs);
1418         dev_dbg(&pdev->dev, "srm:      0x%08lx\n",
1419                         ipu_base + devtype->srm_ofs);
1420         dev_dbg(&pdev->dev, "tpm:      0x%08lx\n",
1421                         ipu_base + devtype->tpm_ofs);
1422         dev_dbg(&pdev->dev, "dc:       0x%08lx\n",
1423                         ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1424         dev_dbg(&pdev->dev, "ic:       0x%08lx\n",
1425                         ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1426         dev_dbg(&pdev->dev, "dmfc:     0x%08lx\n",
1427                         ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1428         dev_dbg(&pdev->dev, "vdi:      0x%08lx\n",
1429                         ipu_base + devtype->vdi_ofs);
1430
1431         ipu->cm_reg = devm_ioremap(&pdev->dev,
1432                         ipu_base + devtype->cm_ofs, PAGE_SIZE);
1433         ipu->idmac_reg = devm_ioremap(&pdev->dev,
1434                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1435                         PAGE_SIZE);
1436
1437         if (!ipu->cm_reg || !ipu->idmac_reg)
1438                 return -ENOMEM;
1439
1440         ipu->clk = devm_clk_get(&pdev->dev, "bus");
1441         if (IS_ERR(ipu->clk)) {
1442                 ret = PTR_ERR(ipu->clk);
1443                 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1444                 return ret;
1445         }
1446
1447         platform_set_drvdata(pdev, ipu);
1448
1449         ret = clk_prepare_enable(ipu->clk);
1450         if (ret) {
1451                 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1452                 return ret;
1453         }
1454
1455         ipu->dev = &pdev->dev;
1456         ipu->irq_sync = irq_sync;
1457         ipu->irq_err = irq_err;
1458
1459         ret = device_reset(&pdev->dev);
1460         if (ret) {
1461                 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1462                 goto out_failed_reset;
1463         }
1464         ret = ipu_memory_reset(ipu);
1465         if (ret)
1466                 goto out_failed_reset;
1467
1468         ret = ipu_irq_init(ipu);
1469         if (ret)
1470                 goto out_failed_irq;
1471
1472         /* Set MCU_T to divide MCU access window into 2 */
1473         ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1474                         IPU_DISP_GEN);
1475
1476         ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1477         if (ret)
1478                 goto failed_submodules_init;
1479
1480         ret = ipu_add_client_devices(ipu, ipu_base);
1481         if (ret) {
1482                 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1483                                 ret);
1484                 goto failed_add_clients;
1485         }
1486
1487         dev_info(&pdev->dev, "%s probed\n", devtype->name);
1488
1489         return 0;
1490
1491 failed_add_clients:
1492         ipu_submodules_exit(ipu);
1493 failed_submodules_init:
1494         ipu_irq_exit(ipu);
1495 out_failed_irq:
1496 out_failed_reset:
1497         clk_disable_unprepare(ipu->clk);
1498         return ret;
1499 }
1500
1501 static int ipu_remove(struct platform_device *pdev)
1502 {
1503         struct ipu_soc *ipu = platform_get_drvdata(pdev);
1504
1505         platform_device_unregister_children(pdev);
1506         ipu_submodules_exit(ipu);
1507         ipu_irq_exit(ipu);
1508
1509         clk_disable_unprepare(ipu->clk);
1510
1511         return 0;
1512 }
1513
1514 static struct platform_driver imx_ipu_driver = {
1515         .driver = {
1516                 .name = "imx-ipuv3",
1517                 .of_match_table = imx_ipu_dt_ids,
1518         },
1519         .probe = ipu_probe,
1520         .remove = ipu_remove,
1521 };
1522
1523 module_platform_driver(imx_ipu_driver);
1524
1525 MODULE_ALIAS("platform:imx-ipuv3");
1526 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1527 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1528 MODULE_LICENSE("GPL");