drivers/gpu/ipu-v3/ipu-common.c

   1 /*
   2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
   3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/export.h>
  17 #include <linux/types.h>
  18 #include <linux/reset.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/err.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/delay.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/clk.h>
  26 #include <linux/list.h>
  27 #include <linux/irq.h>
  28 #include <linux/irqchip/chained_irq.h>
  29 #include <linux/irqdomain.h>
  30 #include <linux/of_device.h>
  31
  32 #include <drm/drm_fourcc.h>
  33
  34 #include <video/imx-ipu-v3.h>
  35 #include "ipu-prv.h"
  36
  37 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
  38 {
  39         return readl(ipu->cm_reg + offset);
  40 }
  41
  42 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
  43 {
  44         writel(value, ipu->cm_reg + offset);
  45 }
  46
  47 void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
  48 {
  49         u32 val;
  50
  51         val = ipu_cm_read(ipu, IPU_SRM_PRI2);
  52         val |= 0x8;
  53         ipu_cm_write(ipu, val, IPU_SRM_PRI2);
  54 }
  55 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
  56
  57 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
  58 {
  59         switch (drm_fourcc) {
  60         case DRM_FORMAT_RGB565:
  61         case DRM_FORMAT_BGR565:
  62         case DRM_FORMAT_RGB888:
  63         case DRM_FORMAT_BGR888:
  64         case DRM_FORMAT_XRGB8888:
  65         case DRM_FORMAT_XBGR8888:
  66         case DRM_FORMAT_RGBX8888:
  67         case DRM_FORMAT_BGRX8888:
  68         case DRM_FORMAT_ARGB8888:
  69         case DRM_FORMAT_ABGR8888:
  70         case DRM_FORMAT_RGBA8888:
  71         case DRM_FORMAT_BGRA8888:
  72                 return IPUV3_COLORSPACE_RGB;
  73         case DRM_FORMAT_YUYV:
  74         case DRM_FORMAT_UYVY:
  75         case DRM_FORMAT_YUV420:
  76         case DRM_FORMAT_YVU420:
  77                 return IPUV3_COLORSPACE_YUV;
  78         default:
  79                 return IPUV3_COLORSPACE_UNKNOWN;
  80         }
  81 }
  82 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
  83
  84 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
  85 {
  86         switch (pixelformat) {
  87         case V4L2_PIX_FMT_YUV420:
  88         case V4L2_PIX_FMT_YVU420:
  89         case V4L2_PIX_FMT_UYVY:
  90         case V4L2_PIX_FMT_YUYV:
  91                 return IPUV3_COLORSPACE_YUV;
  92         case V4L2_PIX_FMT_RGB32:
  93         case V4L2_PIX_FMT_BGR32:
  94         case V4L2_PIX_FMT_RGB24:
  95         case V4L2_PIX_FMT_BGR24:
  96         case V4L2_PIX_FMT_RGB565:
  97                 return IPUV3_COLORSPACE_RGB;
  98         default:
  99                 return IPUV3_COLORSPACE_UNKNOWN;
 100         }
 101 }
 102 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
 103
 104 bool ipu_pixelformat_is_planar(u32 pixelformat)
 105 {
 106         switch (pixelformat) {
 107         case V4L2_PIX_FMT_YUV420:
 108         case V4L2_PIX_FMT_YVU420:
 109                 return true;
 110         }
 111
 112         return false;
 113 }
 114 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
 115
 116 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
 117 {
 118         switch (mbus_code & 0xf000) {
 119         case 0x1000:
 120                 return IPUV3_COLORSPACE_RGB;
 121         case 0x2000:
 122                 return IPUV3_COLORSPACE_YUV;
 123         default:
 124                 return IPUV3_COLORSPACE_UNKNOWN;
 125         }
 126 }
 127 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
 128
 129 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
 130                             bool hflip, bool vflip)
 131 {
 132         u32 r90, vf, hf;
 133
 134         switch (degrees) {
 135         case 0:
 136                 vf = hf = r90 = 0;
 137                 break;
 138         case 90:
 139                 vf = hf = 0;
 140                 r90 = 1;
 141                 break;
 142         case 180:
 143                 vf = hf = 1;
 144                 r90 = 0;
 145                 break;
 146         case 270:
 147                 vf = hf = r90 = 1;
 148                 break;
 149         default:
 150                 return -EINVAL;
 151         }
 152
 153         hf ^= (u32)hflip;
 154         vf ^= (u32)vflip;
 155
 156         *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
 157         return 0;
 158 }
 159 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
 160
 161 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
 162                             bool hflip, bool vflip)
 163 {
 164         u32 r90, vf, hf;
 165
 166         r90 = ((u32)mode >> 2) & 0x1;
 167         hf = ((u32)mode >> 1) & 0x1;
 168         vf = ((u32)mode >> 0) & 0x1;
 169         hf ^= (u32)hflip;
 170         vf ^= (u32)vflip;
 171
 172         switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
 173         case IPU_ROTATE_NONE:
 174                 *degrees = 0;
 175                 break;
 176         case IPU_ROTATE_90_RIGHT:
 177                 *degrees = 90;
 178                 break;
 179         case IPU_ROTATE_180:
 180                 *degrees = 180;
 181                 break;
 182         case IPU_ROTATE_90_LEFT:
 183                 *degrees = 270;
 184                 break;
 185         default:
 186                 return -EINVAL;
 187         }
 188
 189         return 0;
 190 }
 191 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
 192
 193 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
 194 {
 195         struct ipuv3_channel *channel;
 196
 197         dev_dbg(ipu->dev, "%s %d\n", __func__, num);
 198
 199         if (num > 63)
 200                 return ERR_PTR(-ENODEV);
 201
 202         mutex_lock(&ipu->channel_lock);
 203
 204         channel = &ipu->channel[num];
 205
 206         if (channel->busy) {
 207                 channel = ERR_PTR(-EBUSY);
 208                 goto out;
 209         }
 210
 211         channel->busy = true;
 212         channel->num = num;
 213
 214 out:
 215         mutex_unlock(&ipu->channel_lock);
 216
 217         return channel;
 218 }
 219 EXPORT_SYMBOL_GPL(ipu_idmac_get);
 220
 221 void ipu_idmac_put(struct ipuv3_channel *channel)
 222 {
 223         struct ipu_soc *ipu = channel->ipu;
 224
 225         dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
 226
 227         mutex_lock(&ipu->channel_lock);
 228
 229         channel->busy = false;
 230
 231         mutex_unlock(&ipu->channel_lock);
 232 }
 233 EXPORT_SYMBOL_GPL(ipu_idmac_put);
 234
 235 #define idma_mask(ch)                   (1 << ((ch) & 0x1f))
 236
 237 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
 238                 bool doublebuffer)
 239 {
 240         struct ipu_soc *ipu = channel->ipu;
 241         unsigned long flags;
 242         u32 reg;
 243
 244         spin_lock_irqsave(&ipu->lock, flags);
 245
 246         reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 247         if (doublebuffer)
 248                 reg |= idma_mask(channel->num);
 249         else
 250                 reg &= ~idma_mask(channel->num);
 251         ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
 252
 253         spin_unlock_irqrestore(&ipu->lock, flags);
 254 }
 255 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
 256
 257 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
 258 {
 259         unsigned long lock_flags;
 260         u32 val;
 261
 262         spin_lock_irqsave(&ipu->lock, lock_flags);
 263
 264         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 265
 266         if (mask & IPU_CONF_DI0_EN)
 267                 val |= IPU_DI0_COUNTER_RELEASE;
 268         if (mask & IPU_CONF_DI1_EN)
 269                 val |= IPU_DI1_COUNTER_RELEASE;
 270
 271         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 272
 273         val = ipu_cm_read(ipu, IPU_CONF);
 274         val |= mask;
 275         ipu_cm_write(ipu, val, IPU_CONF);
 276
 277         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 278
 279         return 0;
 280 }
 281 EXPORT_SYMBOL_GPL(ipu_module_enable);
 282
 283 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
 284 {
 285         unsigned long lock_flags;
 286         u32 val;
 287
 288         spin_lock_irqsave(&ipu->lock, lock_flags);
 289
 290         val = ipu_cm_read(ipu, IPU_CONF);
 291         val &= ~mask;
 292         ipu_cm_write(ipu, val, IPU_CONF);
 293
 294         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 295
 296         if (mask & IPU_CONF_DI0_EN)
 297                 val &= ~IPU_DI0_COUNTER_RELEASE;
 298         if (mask & IPU_CONF_DI1_EN)
 299                 val &= ~IPU_DI1_COUNTER_RELEASE;
 300
 301         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 302
 303         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 304
 305         return 0;
 306 }
 307 EXPORT_SYMBOL_GPL(ipu_module_disable);
 308
 309 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
 310 {
 311         struct ipu_soc *ipu = channel->ipu;
 312         unsigned int chno = channel->num;
 313
 314         return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
 315 }
 316 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
 317
 318 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
 319 {
 320         struct ipu_soc *ipu = channel->ipu;
 321         unsigned long flags;
 322         u32 reg = 0;
 323
 324         spin_lock_irqsave(&ipu->lock, flags);
 325         switch (buf_num) {
 326         case 0:
 327                 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
 328                 break;
 329         case 1:
 330                 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
 331                 break;
 332         case 2:
 333                 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
 334                 break;
 335         }
 336         spin_unlock_irqrestore(&ipu->lock, flags);
 337
 338         return ((reg & idma_mask(channel->num)) != 0);
 339 }
 340 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
 341
 342 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
 343 {
 344         struct ipu_soc *ipu = channel->ipu;
 345         unsigned int chno = channel->num;
 346         unsigned long flags;
 347
 348         spin_lock_irqsave(&ipu->lock, flags);
 349
 350         /* Mark buffer as ready. */
 351         if (buf_num == 0)
 352                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
 353         else
 354                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
 355
 356         spin_unlock_irqrestore(&ipu->lock, flags);
 357 }
 358 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
 359
 360 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
 361 {
 362         struct ipu_soc *ipu = channel->ipu;
 363         u32 val;
 364         unsigned long flags;
 365
 366         spin_lock_irqsave(&ipu->lock, flags);
 367
 368         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 369         val |= idma_mask(channel->num);
 370         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 371
 372         spin_unlock_irqrestore(&ipu->lock, flags);
 373
 374         return 0;
 375 }
 376 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
 377
 378 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
 379 {
 380         return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
 381 }
 382 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
 383
 384 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
 385 {
 386         struct ipu_soc *ipu = channel->ipu;
 387         unsigned long timeout;
 388
 389         timeout = jiffies + msecs_to_jiffies(ms);
 390         while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
 391                         idma_mask(channel->num)) {
 392                 if (time_after(jiffies, timeout))
 393                         return -ETIMEDOUT;
 394                 cpu_relax();
 395         }
 396
 397         return 0;
 398 }
 399 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
 400
 401 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
 402 {
 403         unsigned long timeout;
 404
 405         timeout = jiffies + msecs_to_jiffies(ms);
 406         ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
 407         while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
 408                 if (time_after(jiffies, timeout))
 409                         return -ETIMEDOUT;
 410                 cpu_relax();
 411         }
 412
 413         return 0;
 414 }
 415 EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
 416
 417 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
 418 {
 419         struct ipu_soc *ipu = channel->ipu;
 420         u32 val;
 421         unsigned long flags;
 422
 423         spin_lock_irqsave(&ipu->lock, flags);
 424
 425         /* Disable DMA channel(s) */
 426         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 427         val &= ~idma_mask(channel->num);
 428         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 429
 430         /* Set channel buffers NOT to be ready */
 431         ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
 432
 433         if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
 434                         idma_mask(channel->num)) {
 435                 ipu_cm_write(ipu, idma_mask(channel->num),
 436                              IPU_CHA_BUF0_RDY(channel->num));
 437         }
 438
 439         if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
 440                         idma_mask(channel->num)) {
 441                 ipu_cm_write(ipu, idma_mask(channel->num),
 442                              IPU_CHA_BUF1_RDY(channel->num));
 443         }
 444
 445         ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
 446
 447         /* Reset the double buffer */
 448         val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 449         val &= ~idma_mask(channel->num);
 450         ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
 451
 452         spin_unlock_irqrestore(&ipu->lock, flags);
 453
 454         return 0;
 455 }
 456 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
 457
 458 static int ipu_memory_reset(struct ipu_soc *ipu)
 459 {
 460         unsigned long timeout;
 461
 462         ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
 463
 464         timeout = jiffies + msecs_to_jiffies(1000);
 465         while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
 466                 if (time_after(jiffies, timeout))
 467                         return -ETIME;
 468                 cpu_relax();
 469         }
 470
 471         return 0;
 472 }
 473
 474 /*
 475  * Set the source mux for the given CSI. Selects either parallel or
 476  * MIPI CSI2 sources.
 477  */
 478 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
 479 {
 480         unsigned long flags;
 481         u32 val, mask;
 482
 483         mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
 484                 IPU_CONF_CSI0_DATA_SOURCE;
 485
 486         spin_lock_irqsave(&ipu->lock, flags);
 487
 488         val = ipu_cm_read(ipu, IPU_CONF);
 489         if (mipi_csi2)
 490                 val |= mask;
 491         else
 492                 val &= ~mask;
 493         ipu_cm_write(ipu, val, IPU_CONF);
 494
 495         spin_unlock_irqrestore(&ipu->lock, flags);
 496 }
 497 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
 498
 499 /*
 500  * Set the source mux for the IC. Selects either CSI[01] or the VDI.
 501  */
 502 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
 503 {
 504         unsigned long flags;
 505         u32 val;
 506
 507         spin_lock_irqsave(&ipu->lock, flags);
 508
 509         val = ipu_cm_read(ipu, IPU_CONF);
 510         if (vdi) {
 511                 val |= IPU_CONF_IC_INPUT;
 512         } else {
 513                 val &= ~IPU_CONF_IC_INPUT;
 514                 if (csi_id == 1)
 515                         val |= IPU_CONF_CSI_SEL;
 516                 else
 517                         val &= ~IPU_CONF_CSI_SEL;
 518         }
 519         ipu_cm_write(ipu, val, IPU_CONF);
 520
 521         spin_unlock_irqrestore(&ipu->lock, flags);
 522 }
 523 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
 524
 525 struct ipu_devtype {
 526         const char *name;
 527         unsigned long cm_ofs;
 528         unsigned long cpmem_ofs;
 529         unsigned long srm_ofs;
 530         unsigned long tpm_ofs;
 531         unsigned long csi0_ofs;
 532         unsigned long csi1_ofs;
 533         unsigned long ic_ofs;
 534         unsigned long disp0_ofs;
 535         unsigned long disp1_ofs;
 536         unsigned long dc_tmpl_ofs;
 537         unsigned long vdi_ofs;
 538         enum ipuv3_type type;
 539 };
 540
 541 static struct ipu_devtype ipu_type_imx51 = {
 542         .name = "IPUv3EX",
 543         .cm_ofs = 0x1e000000,
 544         .cpmem_ofs = 0x1f000000,
 545         .srm_ofs = 0x1f040000,
 546         .tpm_ofs = 0x1f060000,
 547         .csi0_ofs = 0x1f030000,
 548         .csi1_ofs = 0x1f038000,
 549         .ic_ofs = 0x1f020000,
 550         .disp0_ofs = 0x1e040000,
 551         .disp1_ofs = 0x1e048000,
 552         .dc_tmpl_ofs = 0x1f080000,
 553         .vdi_ofs = 0x1e068000,
 554         .type = IPUV3EX,
 555 };
 556
 557 static struct ipu_devtype ipu_type_imx53 = {
 558         .name = "IPUv3M",
 559         .cm_ofs = 0x06000000,
 560         .cpmem_ofs = 0x07000000,
 561         .srm_ofs = 0x07040000,
 562         .tpm_ofs = 0x07060000,
 563         .csi0_ofs = 0x07030000,
 564         .csi1_ofs = 0x07038000,
 565         .ic_ofs = 0x07020000,
 566         .disp0_ofs = 0x06040000,
 567         .disp1_ofs = 0x06048000,
 568         .dc_tmpl_ofs = 0x07080000,
 569         .vdi_ofs = 0x06068000,
 570         .type = IPUV3M,
 571 };
 572
 573 static struct ipu_devtype ipu_type_imx6q = {
 574         .name = "IPUv3H",
 575         .cm_ofs = 0x00200000,
 576         .cpmem_ofs = 0x00300000,
 577         .srm_ofs = 0x00340000,
 578         .tpm_ofs = 0x00360000,
 579         .csi0_ofs = 0x00230000,
 580         .csi1_ofs = 0x00238000,
 581         .ic_ofs = 0x00220000,
 582         .disp0_ofs = 0x00240000,
 583         .disp1_ofs = 0x00248000,
 584         .dc_tmpl_ofs = 0x00380000,
 585         .vdi_ofs = 0x00268000,
 586         .type = IPUV3H,
 587 };
 588
 589 static const struct of_device_id imx_ipu_dt_ids[] = {
 590         { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
 591         { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
 592         { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
 593         { /* sentinel */ }
 594 };
 595 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
 596
 597 static int ipu_submodules_init(struct ipu_soc *ipu,
 598                 struct platform_device *pdev, unsigned long ipu_base,
 599                 struct clk *ipu_clk)
 600 {
 601         char *unit;
 602         int ret;
 603         struct device *dev = &pdev->dev;
 604         const struct ipu_devtype *devtype = ipu->devtype;
 605
 606         ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
 607         if (ret) {
 608                 unit = "cpmem";
 609                 goto err_cpmem;
 610         }
 611
 612         ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
 613                            IPU_CONF_CSI0_EN, ipu_clk);
 614         if (ret) {
 615                 unit = "csi0";
 616                 goto err_csi_0;
 617         }
 618
 619         ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
 620                            IPU_CONF_CSI1_EN, ipu_clk);
 621         if (ret) {
 622                 unit = "csi1";
 623                 goto err_csi_1;
 624         }
 625
 626         ret = ipu_ic_init(ipu, dev,
 627                           ipu_base + devtype->ic_ofs,
 628                           ipu_base + devtype->tpm_ofs);
 629         if (ret) {
 630                 unit = "ic";
 631                 goto err_ic;
 632         }
 633
 634         ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
 635                           IPU_CONF_DI0_EN, ipu_clk);
 636         if (ret) {
 637                 unit = "di0";
 638                 goto err_di_0;
 639         }
 640
 641         ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
 642                         IPU_CONF_DI1_EN, ipu_clk);
 643         if (ret) {
 644                 unit = "di1";
 645                 goto err_di_1;
 646         }
 647
 648         ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
 649                         IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
 650         if (ret) {
 651                 unit = "dc_template";
 652                 goto err_dc;
 653         }
 654
 655         ret = ipu_dmfc_init(ipu, dev, ipu_base +
 656                         devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
 657         if (ret) {
 658                 unit = "dmfc";
 659                 goto err_dmfc;
 660         }
 661
 662         ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
 663         if (ret) {
 664                 unit = "dp";
 665                 goto err_dp;
 666         }
 667
 668         ret = ipu_smfc_init(ipu, dev, ipu_base +
 669                         devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
 670         if (ret) {
 671                 unit = "smfc";
 672                 goto err_smfc;
 673         }
 674
 675         return 0;
 676
 677 err_smfc:
 678         ipu_dp_exit(ipu);
 679 err_dp:
 680         ipu_dmfc_exit(ipu);
 681 err_dmfc:
 682         ipu_dc_exit(ipu);
 683 err_dc:
 684         ipu_di_exit(ipu, 1);
 685 err_di_1:
 686         ipu_di_exit(ipu, 0);
 687 err_di_0:
 688         ipu_ic_exit(ipu);
 689 err_ic:
 690         ipu_csi_exit(ipu, 1);
 691 err_csi_1:
 692         ipu_csi_exit(ipu, 0);
 693 err_csi_0:
 694         ipu_cpmem_exit(ipu);
 695 err_cpmem:
 696         dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
 697         return ret;
 698 }
 699
 700 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
 701 {
 702         unsigned long status;
 703         int i, bit, irq;
 704
 705         for (i = 0; i < num_regs; i++) {
 706
 707                 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
 708                 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
 709
 710                 for_each_set_bit(bit, &status, 32) {
 711                         irq = irq_linear_revmap(ipu->domain,
 712                                                 regs[i] * 32 + bit);
 713                         if (irq)
 714                                 generic_handle_irq(irq);
 715                 }
 716         }
 717 }
 718
 719 static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc)
 720 {
 721         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
 722         const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
 723         struct irq_chip *chip = irq_get_chip(irq);
 724
 725         chained_irq_enter(chip, desc);
 726
 727         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
 728
 729         chained_irq_exit(chip, desc);
 730 }
 731
 732 static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
 733 {
 734         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
 735         const int int_reg[] = { 4, 5, 8, 9};
 736         struct irq_chip *chip = irq_get_chip(irq);
 737
 738         chained_irq_enter(chip, desc);
 739
 740         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
 741
 742         chained_irq_exit(chip, desc);
 743 }
 744
 745 int ipu_map_irq(struct ipu_soc *ipu, int irq)
 746 {
 747         int virq;
 748
 749         virq = irq_linear_revmap(ipu->domain, irq);
 750         if (!virq)
 751                 virq = irq_create_mapping(ipu->domain, irq);
 752
 753         return virq;
 754 }
 755 EXPORT_SYMBOL_GPL(ipu_map_irq);
 756
 757 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
 758                 enum ipu_channel_irq irq_type)
 759 {
 760         return ipu_map_irq(ipu, irq_type + channel->num);
 761 }
 762 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
 763
 764 static void ipu_submodules_exit(struct ipu_soc *ipu)
 765 {
 766         ipu_smfc_exit(ipu);
 767         ipu_dp_exit(ipu);
 768         ipu_dmfc_exit(ipu);
 769         ipu_dc_exit(ipu);
 770         ipu_di_exit(ipu, 1);
 771         ipu_di_exit(ipu, 0);
 772         ipu_ic_exit(ipu);
 773         ipu_csi_exit(ipu, 1);
 774         ipu_csi_exit(ipu, 0);
 775         ipu_cpmem_exit(ipu);
 776 }
 777
 778 static int platform_remove_devices_fn(struct device *dev, void *unused)
 779 {
 780         struct platform_device *pdev = to_platform_device(dev);
 781
 782         platform_device_unregister(pdev);
 783
 784         return 0;
 785 }
 786
 787 static void platform_device_unregister_children(struct platform_device *pdev)
 788 {
 789         device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
 790 }
 791
 792 struct ipu_platform_reg {
 793         struct ipu_client_platformdata pdata;
 794         const char *name;
 795         int reg_offset;
 796 };
 797
 798 static const struct ipu_platform_reg client_reg[] = {
 799         {
 800                 .pdata = {
 801                         .di = 0,
 802                         .dc = 5,
 803                         .dp = IPU_DP_FLOW_SYNC_BG,
 804                         .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
 805                         .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
 806                 },
 807                 .name = "imx-ipuv3-crtc",
 808         }, {
 809                 .pdata = {
 810                         .di = 1,
 811                         .dc = 1,
 812                         .dp = -EINVAL,
 813                         .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
 814                         .dma[1] = -EINVAL,
 815                 },
 816                 .name = "imx-ipuv3-crtc",
 817         }, {
 818                 .pdata = {
 819                         .csi = 0,
 820                         .dma[0] = IPUV3_CHANNEL_CSI0,
 821                         .dma[1] = -EINVAL,
 822                 },
 823                 .reg_offset = IPU_CM_CSI0_REG_OFS,
 824                 .name = "imx-ipuv3-camera",
 825         }, {
 826                 .pdata = {
 827                         .csi = 1,
 828                         .dma[0] = IPUV3_CHANNEL_CSI1,
 829                         .dma[1] = -EINVAL,
 830                 },
 831                 .reg_offset = IPU_CM_CSI1_REG_OFS,
 832                 .name = "imx-ipuv3-camera",
 833         },
 834 };
 835
 836 static DEFINE_MUTEX(ipu_client_id_mutex);
 837 static int ipu_client_id;
 838
 839 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
 840 {
 841         struct device *dev = ipu->dev;
 842         unsigned i;
 843         int id, ret;
 844
 845         mutex_lock(&ipu_client_id_mutex);
 846         id = ipu_client_id;
 847         ipu_client_id += ARRAY_SIZE(client_reg);
 848         mutex_unlock(&ipu_client_id_mutex);
 849
 850         for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
 851                 const struct ipu_platform_reg *reg = &client_reg[i];
 852                 struct platform_device *pdev;
 853                 struct resource res;
 854
 855                 if (reg->reg_offset) {
 856                         memset(&res, 0, sizeof(res));
 857                         res.flags = IORESOURCE_MEM;
 858                         res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset;
 859                         res.end = res.start + PAGE_SIZE - 1;
 860                         pdev = platform_device_register_resndata(dev, reg->name,
 861                                 id++, &res, 1, &reg->pdata, sizeof(reg->pdata));
 862                 } else {
 863                         pdev = platform_device_register_data(dev, reg->name,
 864                                 id++, &reg->pdata, sizeof(reg->pdata));
 865                 }
 866
 867                 if (IS_ERR(pdev))
 868                         goto err_register;
 869         }
 870
 871         return 0;
 872
 873 err_register:
 874         platform_device_unregister_children(to_platform_device(dev));
 875
 876         return ret;
 877 }
 878
 879
 880 static int ipu_irq_init(struct ipu_soc *ipu)
 881 {
 882         struct irq_chip_generic *gc;
 883         struct irq_chip_type *ct;
 884         unsigned long unused[IPU_NUM_IRQS / 32] = {
 885                 0x400100d0, 0xffe000fd,
 886                 0x400100d0, 0xffe000fd,
 887                 0x400100d0, 0xffe000fd,
 888                 0x4077ffff, 0xffe7e1fd,
 889                 0x23fffffe, 0x8880fff0,
 890                 0xf98fe7d0, 0xfff81fff,
 891                 0x400100d0, 0xffe000fd,
 892                 0x00000000,
 893         };
 894         int ret, i;
 895
 896         ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
 897                                             &irq_generic_chip_ops, ipu);
 898         if (!ipu->domain) {
 899                 dev_err(ipu->dev, "failed to add irq domain\n");
 900                 return -ENODEV;
 901         }
 902
 903         ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
 904                                              handle_level_irq, 0,
 905                                              IRQF_VALID, 0);
 906         if (ret < 0) {
 907                 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
 908                 irq_domain_remove(ipu->domain);
 909                 return ret;
 910         }
 911
 912         for (i = 0; i < IPU_NUM_IRQS; i += 32) {
 913                 gc = irq_get_domain_generic_chip(ipu->domain, i);
 914                 gc->reg_base = ipu->cm_reg;
 915                 gc->unused = unused[i / 32];
 916                 ct = gc->chip_types;
 917                 ct->chip.irq_ack = irq_gc_ack_set_bit;
 918                 ct->chip.irq_mask = irq_gc_mask_clr_bit;
 919                 ct->chip.irq_unmask = irq_gc_mask_set_bit;
 920                 ct->regs.ack = IPU_INT_STAT(i / 32);
 921                 ct->regs.mask = IPU_INT_CTRL(i / 32);
 922         }
 923
 924         irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler);
 925         irq_set_handler_data(ipu->irq_sync, ipu);
 926         irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler);
 927         irq_set_handler_data(ipu->irq_err, ipu);
 928
 929         return 0;
 930 }
 931
 932 static void ipu_irq_exit(struct ipu_soc *ipu)
 933 {
 934         int i, irq;
 935
 936         irq_set_chained_handler(ipu->irq_err, NULL);
 937         irq_set_handler_data(ipu->irq_err, NULL);
 938         irq_set_chained_handler(ipu->irq_sync, NULL);
 939         irq_set_handler_data(ipu->irq_sync, NULL);
 940
 941         /* TODO: remove irq_domain_generic_chips */
 942
 943         for (i = 0; i < IPU_NUM_IRQS; i++) {
 944                 irq = irq_linear_revmap(ipu->domain, i);
 945                 if (irq)
 946                         irq_dispose_mapping(irq);
 947         }
 948
 949         irq_domain_remove(ipu->domain);
 950 }
 951
 952 static int ipu_probe(struct platform_device *pdev)
 953 {
 954         const struct of_device_id *of_id =
 955                         of_match_device(imx_ipu_dt_ids, &pdev->dev);
 956         struct ipu_soc *ipu;
 957         struct resource *res;
 958         unsigned long ipu_base;
 959         int i, ret, irq_sync, irq_err;
 960         const struct ipu_devtype *devtype;
 961
 962         devtype = of_id->data;
 963
 964         irq_sync = platform_get_irq(pdev, 0);
 965         irq_err = platform_get_irq(pdev, 1);
 966         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 967
 968         dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
 969                         irq_sync, irq_err);
 970
 971         if (!res || irq_sync < 0 || irq_err < 0)
 972                 return -ENODEV;
 973
 974         ipu_base = res->start;
 975
 976         ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
 977         if (!ipu)
 978                 return -ENODEV;
 979
 980         for (i = 0; i < 64; i++)
 981                 ipu->channel[i].ipu = ipu;
 982         ipu->devtype = devtype;
 983         ipu->ipu_type = devtype->type;
 984
 985         spin_lock_init(&ipu->lock);
 986         mutex_init(&ipu->channel_lock);
 987
 988         dev_dbg(&pdev->dev, "cm_reg:   0x%08lx\n",
 989                         ipu_base + devtype->cm_ofs);
 990         dev_dbg(&pdev->dev, "idmac:    0x%08lx\n",
 991                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
 992         dev_dbg(&pdev->dev, "cpmem:    0x%08lx\n",
 993                         ipu_base + devtype->cpmem_ofs);
 994         dev_dbg(&pdev->dev, "csi0:    0x%08lx\n",
 995                         ipu_base + devtype->csi0_ofs);
 996         dev_dbg(&pdev->dev, "csi1:    0x%08lx\n",
 997                         ipu_base + devtype->csi1_ofs);
 998         dev_dbg(&pdev->dev, "ic:      0x%08lx\n",
 999                         ipu_base + devtype->ic_ofs);
1000         dev_dbg(&pdev->dev, "disp0:    0x%08lx\n",
1001                         ipu_base + devtype->disp0_ofs);
1002         dev_dbg(&pdev->dev, "disp1:    0x%08lx\n",
1003                         ipu_base + devtype->disp1_ofs);
1004         dev_dbg(&pdev->dev, "srm:      0x%08lx\n",
1005                         ipu_base + devtype->srm_ofs);
1006         dev_dbg(&pdev->dev, "tpm:      0x%08lx\n",
1007                         ipu_base + devtype->tpm_ofs);
1008         dev_dbg(&pdev->dev, "dc:       0x%08lx\n",
1009                         ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1010         dev_dbg(&pdev->dev, "ic:       0x%08lx\n",
1011                         ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1012         dev_dbg(&pdev->dev, "dmfc:     0x%08lx\n",
1013                         ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1014         dev_dbg(&pdev->dev, "vdi:      0x%08lx\n",
1015                         ipu_base + devtype->vdi_ofs);
1016
1017         ipu->cm_reg = devm_ioremap(&pdev->dev,
1018                         ipu_base + devtype->cm_ofs, PAGE_SIZE);
1019         ipu->idmac_reg = devm_ioremap(&pdev->dev,
1020                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1021                         PAGE_SIZE);
1022
1023         if (!ipu->cm_reg || !ipu->idmac_reg)
1024                 return -ENOMEM;
1025
1026         ipu->clk = devm_clk_get(&pdev->dev, "bus");
1027         if (IS_ERR(ipu->clk)) {
1028                 ret = PTR_ERR(ipu->clk);
1029                 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1030                 return ret;
1031         }
1032
1033         platform_set_drvdata(pdev, ipu);
1034
1035         ret = clk_prepare_enable(ipu->clk);
1036         if (ret) {
1037                 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1038                 return ret;
1039         }
1040
1041         ipu->dev = &pdev->dev;
1042         ipu->irq_sync = irq_sync;
1043         ipu->irq_err = irq_err;
1044
1045         ret = ipu_irq_init(ipu);
1046         if (ret)
1047                 goto out_failed_irq;
1048
1049         ret = device_reset(&pdev->dev);
1050         if (ret) {
1051                 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1052                 goto out_failed_reset;
1053         }
1054         ret = ipu_memory_reset(ipu);
1055         if (ret)
1056                 goto out_failed_reset;
1057
1058         /* Set MCU_T to divide MCU access window into 2 */
1059         ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1060                         IPU_DISP_GEN);
1061
1062         ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1063         if (ret)
1064                 goto failed_submodules_init;
1065
1066         ret = ipu_add_client_devices(ipu, ipu_base);
1067         if (ret) {
1068                 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1069                                 ret);
1070                 goto failed_add_clients;
1071         }
1072
1073         dev_info(&pdev->dev, "%s probed\n", devtype->name);
1074
1075         return 0;
1076
1077 failed_add_clients:
1078         ipu_submodules_exit(ipu);
1079 failed_submodules_init:
1080 out_failed_reset:
1081         ipu_irq_exit(ipu);
1082 out_failed_irq:
1083         clk_disable_unprepare(ipu->clk);
1084         return ret;
1085 }
1086
1087 static int ipu_remove(struct platform_device *pdev)
1088 {
1089         struct ipu_soc *ipu = platform_get_drvdata(pdev);
1090
1091         platform_device_unregister_children(pdev);
1092         ipu_submodules_exit(ipu);
1093         ipu_irq_exit(ipu);
1094
1095         clk_disable_unprepare(ipu->clk);
1096
1097         return 0;
1098 }
1099
1100 static struct platform_driver imx_ipu_driver = {
1101         .driver = {
1102                 .name = "imx-ipuv3",
1103                 .of_match_table = imx_ipu_dt_ids,
1104         },
1105         .probe = ipu_probe,
1106         .remove = ipu_remove,
1107 };
1108
1109 module_platform_driver(imx_ipu_driver);
1110
1111 MODULE_ALIAS("platform:imx-ipuv3");
1112 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1113 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1114 MODULE_LICENSE("GPL");