drivers/gpu/ipu-v3/ipu-common.c

   1 /*
   2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
   3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/export.h>
  17 #include <linux/types.h>
  18 #include <linux/reset.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/err.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/delay.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/clk.h>
  26 #include <linux/list.h>
  27 #include <linux/irq.h>
  28 #include <linux/irqchip/chained_irq.h>
  29 #include <linux/irqdomain.h>
  30 #include <linux/of_device.h>
  31
  32 #include <drm/drm_fourcc.h>
  33
  34 #include <video/imx-ipu-v3.h>
  35 #include "ipu-prv.h"
  36
  37 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
  38 {
  39         return readl(ipu->cm_reg + offset);
  40 }
  41
  42 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
  43 {
  44         writel(value, ipu->cm_reg + offset);
  45 }
  46
  47 void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
  48 {
  49         u32 val;
  50
  51         val = ipu_cm_read(ipu, IPU_SRM_PRI2);
  52         val |= 0x8;
  53         ipu_cm_write(ipu, val, IPU_SRM_PRI2);
  54 }
  55 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
  56
  57 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
  58 {
  59         switch (drm_fourcc) {
  60         case DRM_FORMAT_RGB565:
  61         case DRM_FORMAT_BGR565:
  62         case DRM_FORMAT_RGB888:
  63         case DRM_FORMAT_BGR888:
  64         case DRM_FORMAT_XRGB8888:
  65         case DRM_FORMAT_XBGR8888:
  66         case DRM_FORMAT_RGBX8888:
  67         case DRM_FORMAT_BGRX8888:
  68         case DRM_FORMAT_ARGB8888:
  69         case DRM_FORMAT_ABGR8888:
  70         case DRM_FORMAT_RGBA8888:
  71         case DRM_FORMAT_BGRA8888:
  72                 return IPUV3_COLORSPACE_RGB;
  73         case DRM_FORMAT_YUYV:
  74         case DRM_FORMAT_UYVY:
  75         case DRM_FORMAT_YUV420:
  76         case DRM_FORMAT_YVU420:
  77                 return IPUV3_COLORSPACE_YUV;
  78         default:
  79                 return IPUV3_COLORSPACE_UNKNOWN;
  80         }
  81 }
  82 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
  83
  84 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
  85 {
  86         switch (pixelformat) {
  87         case V4L2_PIX_FMT_YUV420:
  88         case V4L2_PIX_FMT_YVU420:
  89         case V4L2_PIX_FMT_UYVY:
  90         case V4L2_PIX_FMT_YUYV:
  91                 return IPUV3_COLORSPACE_YUV;
  92         case V4L2_PIX_FMT_RGB32:
  93         case V4L2_PIX_FMT_BGR32:
  94         case V4L2_PIX_FMT_RGB24:
  95         case V4L2_PIX_FMT_BGR24:
  96         case V4L2_PIX_FMT_RGB565:
  97                 return IPUV3_COLORSPACE_RGB;
  98         default:
  99                 return IPUV3_COLORSPACE_UNKNOWN;
 100         }
 101 }
 102 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
 103
 104 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
 105 {
 106         struct ipuv3_channel *channel;
 107
 108         dev_dbg(ipu->dev, "%s %d\n", __func__, num);
 109
 110         if (num > 63)
 111                 return ERR_PTR(-ENODEV);
 112
 113         mutex_lock(&ipu->channel_lock);
 114
 115         channel = &ipu->channel[num];
 116
 117         if (channel->busy) {
 118                 channel = ERR_PTR(-EBUSY);
 119                 goto out;
 120         }
 121
 122         channel->busy = true;
 123         channel->num = num;
 124
 125 out:
 126         mutex_unlock(&ipu->channel_lock);
 127
 128         return channel;
 129 }
 130 EXPORT_SYMBOL_GPL(ipu_idmac_get);
 131
 132 void ipu_idmac_put(struct ipuv3_channel *channel)
 133 {
 134         struct ipu_soc *ipu = channel->ipu;
 135
 136         dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
 137
 138         mutex_lock(&ipu->channel_lock);
 139
 140         channel->busy = false;
 141
 142         mutex_unlock(&ipu->channel_lock);
 143 }
 144 EXPORT_SYMBOL_GPL(ipu_idmac_put);
 145
 146 #define idma_mask(ch)                   (1 << (ch & 0x1f))
 147
 148 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
 149                 bool doublebuffer)
 150 {
 151         struct ipu_soc *ipu = channel->ipu;
 152         unsigned long flags;
 153         u32 reg;
 154
 155         spin_lock_irqsave(&ipu->lock, flags);
 156
 157         reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 158         if (doublebuffer)
 159                 reg |= idma_mask(channel->num);
 160         else
 161                 reg &= ~idma_mask(channel->num);
 162         ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
 163
 164         spin_unlock_irqrestore(&ipu->lock, flags);
 165 }
 166 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
 167
 168 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
 169 {
 170         unsigned long lock_flags;
 171         u32 val;
 172
 173         spin_lock_irqsave(&ipu->lock, lock_flags);
 174
 175         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 176
 177         if (mask & IPU_CONF_DI0_EN)
 178                 val |= IPU_DI0_COUNTER_RELEASE;
 179         if (mask & IPU_CONF_DI1_EN)
 180                 val |= IPU_DI1_COUNTER_RELEASE;
 181
 182         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 183
 184         val = ipu_cm_read(ipu, IPU_CONF);
 185         val |= mask;
 186         ipu_cm_write(ipu, val, IPU_CONF);
 187
 188         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 189
 190         return 0;
 191 }
 192 EXPORT_SYMBOL_GPL(ipu_module_enable);
 193
 194 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
 195 {
 196         unsigned long lock_flags;
 197         u32 val;
 198
 199         spin_lock_irqsave(&ipu->lock, lock_flags);
 200
 201         val = ipu_cm_read(ipu, IPU_CONF);
 202         val &= ~mask;
 203         ipu_cm_write(ipu, val, IPU_CONF);
 204
 205         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 206
 207         if (mask & IPU_CONF_DI0_EN)
 208                 val &= ~IPU_DI0_COUNTER_RELEASE;
 209         if (mask & IPU_CONF_DI1_EN)
 210                 val &= ~IPU_DI1_COUNTER_RELEASE;
 211
 212         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 213
 214         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 215
 216         return 0;
 217 }
 218 EXPORT_SYMBOL_GPL(ipu_module_disable);
 219
 220 int ipu_csi_enable(struct ipu_soc *ipu, int csi)
 221 {
 222         return ipu_module_enable(ipu, csi ? IPU_CONF_CSI1_EN : IPU_CONF_CSI0_EN);
 223 }
 224 EXPORT_SYMBOL_GPL(ipu_csi_enable);
 225
 226 int ipu_csi_disable(struct ipu_soc *ipu, int csi)
 227 {
 228         return ipu_module_disable(ipu, csi ? IPU_CONF_CSI1_EN : IPU_CONF_CSI0_EN);
 229 }
 230 EXPORT_SYMBOL_GPL(ipu_csi_disable);
 231
 232 int ipu_smfc_enable(struct ipu_soc *ipu)
 233 {
 234         return ipu_module_enable(ipu, IPU_CONF_SMFC_EN);
 235 }
 236 EXPORT_SYMBOL_GPL(ipu_smfc_enable);
 237
 238 int ipu_smfc_disable(struct ipu_soc *ipu)
 239 {
 240         return ipu_module_disable(ipu, IPU_CONF_SMFC_EN);
 241 }
 242 EXPORT_SYMBOL_GPL(ipu_smfc_disable);
 243
 244 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
 245 {
 246         struct ipu_soc *ipu = channel->ipu;
 247         unsigned int chno = channel->num;
 248
 249         return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
 250 }
 251 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
 252
 253 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
 254 {
 255         struct ipu_soc *ipu = channel->ipu;
 256         unsigned int chno = channel->num;
 257         unsigned long flags;
 258
 259         spin_lock_irqsave(&ipu->lock, flags);
 260
 261         /* Mark buffer as ready. */
 262         if (buf_num == 0)
 263                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
 264         else
 265                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
 266
 267         spin_unlock_irqrestore(&ipu->lock, flags);
 268 }
 269 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
 270
 271 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
 272 {
 273         struct ipu_soc *ipu = channel->ipu;
 274         u32 val;
 275         unsigned long flags;
 276
 277         spin_lock_irqsave(&ipu->lock, flags);
 278
 279         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 280         val |= idma_mask(channel->num);
 281         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 282
 283         spin_unlock_irqrestore(&ipu->lock, flags);
 284
 285         return 0;
 286 }
 287 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
 288
 289 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
 290 {
 291         return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
 292 }
 293 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
 294
 295 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
 296 {
 297         struct ipu_soc *ipu = channel->ipu;
 298         unsigned long timeout;
 299
 300         timeout = jiffies + msecs_to_jiffies(ms);
 301         while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
 302                         idma_mask(channel->num)) {
 303                 if (time_after(jiffies, timeout))
 304                         return -ETIMEDOUT;
 305                 cpu_relax();
 306         }
 307
 308         return 0;
 309 }
 310 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
 311
 312 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
 313 {
 314         unsigned long timeout;
 315
 316         timeout = jiffies + msecs_to_jiffies(ms);
 317         ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
 318         while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
 319                 if (time_after(jiffies, timeout))
 320                         return -ETIMEDOUT;
 321                 cpu_relax();
 322         }
 323
 324         return 0;
 325 }
 326 EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
 327
 328 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
 329 {
 330         struct ipu_soc *ipu = channel->ipu;
 331         u32 val;
 332         unsigned long flags;
 333
 334         spin_lock_irqsave(&ipu->lock, flags);
 335
 336         /* Disable DMA channel(s) */
 337         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 338         val &= ~idma_mask(channel->num);
 339         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 340
 341         /* Set channel buffers NOT to be ready */
 342         ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
 343
 344         if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
 345                         idma_mask(channel->num)) {
 346                 ipu_cm_write(ipu, idma_mask(channel->num),
 347                              IPU_CHA_BUF0_RDY(channel->num));
 348         }
 349
 350         if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
 351                         idma_mask(channel->num)) {
 352                 ipu_cm_write(ipu, idma_mask(channel->num),
 353                              IPU_CHA_BUF1_RDY(channel->num));
 354         }
 355
 356         ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
 357
 358         /* Reset the double buffer */
 359         val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 360         val &= ~idma_mask(channel->num);
 361         ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
 362
 363         spin_unlock_irqrestore(&ipu->lock, flags);
 364
 365         return 0;
 366 }
 367 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
 368
 369 static int ipu_memory_reset(struct ipu_soc *ipu)
 370 {
 371         unsigned long timeout;
 372
 373         ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
 374
 375         timeout = jiffies + msecs_to_jiffies(1000);
 376         while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
 377                 if (time_after(jiffies, timeout))
 378                         return -ETIME;
 379                 cpu_relax();
 380         }
 381
 382         return 0;
 383 }
 384
 385 /*
 386  * Set the source mux for the given CSI. Selects either parallel or
 387  * MIPI CSI2 sources.
 388  */
 389 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
 390 {
 391         unsigned long flags;
 392         u32 val, mask;
 393
 394         mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
 395                 IPU_CONF_CSI0_DATA_SOURCE;
 396
 397         spin_lock_irqsave(&ipu->lock, flags);
 398
 399         val = ipu_cm_read(ipu, IPU_CONF);
 400         if (mipi_csi2)
 401                 val |= mask;
 402         else
 403                 val &= ~mask;
 404         ipu_cm_write(ipu, val, IPU_CONF);
 405
 406         spin_unlock_irqrestore(&ipu->lock, flags);
 407 }
 408 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
 409
 410 /*
 411  * Set the source mux for the IC. Selects either CSI[01] or the VDI.
 412  */
 413 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
 414 {
 415         unsigned long flags;
 416         u32 val;
 417
 418         spin_lock_irqsave(&ipu->lock, flags);
 419
 420         val = ipu_cm_read(ipu, IPU_CONF);
 421         if (vdi) {
 422                 val |= IPU_CONF_IC_INPUT;
 423         } else {
 424                 val &= ~IPU_CONF_IC_INPUT;
 425                 if (csi_id == 1)
 426                         val |= IPU_CONF_CSI_SEL;
 427                 else
 428                         val &= ~IPU_CONF_CSI_SEL;
 429         }
 430         ipu_cm_write(ipu, val, IPU_CONF);
 431
 432         spin_unlock_irqrestore(&ipu->lock, flags);
 433 }
 434 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
 435
 436 struct ipu_devtype {
 437         const char *name;
 438         unsigned long cm_ofs;
 439         unsigned long cpmem_ofs;
 440         unsigned long srm_ofs;
 441         unsigned long tpm_ofs;
 442         unsigned long disp0_ofs;
 443         unsigned long disp1_ofs;
 444         unsigned long dc_tmpl_ofs;
 445         unsigned long vdi_ofs;
 446         enum ipuv3_type type;
 447 };
 448
 449 static struct ipu_devtype ipu_type_imx51 = {
 450         .name = "IPUv3EX",
 451         .cm_ofs = 0x1e000000,
 452         .cpmem_ofs = 0x1f000000,
 453         .srm_ofs = 0x1f040000,
 454         .tpm_ofs = 0x1f060000,
 455         .disp0_ofs = 0x1e040000,
 456         .disp1_ofs = 0x1e048000,
 457         .dc_tmpl_ofs = 0x1f080000,
 458         .vdi_ofs = 0x1e068000,
 459         .type = IPUV3EX,
 460 };
 461
 462 static struct ipu_devtype ipu_type_imx53 = {
 463         .name = "IPUv3M",
 464         .cm_ofs = 0x06000000,
 465         .cpmem_ofs = 0x07000000,
 466         .srm_ofs = 0x07040000,
 467         .tpm_ofs = 0x07060000,
 468         .disp0_ofs = 0x06040000,
 469         .disp1_ofs = 0x06048000,
 470         .dc_tmpl_ofs = 0x07080000,
 471         .vdi_ofs = 0x06068000,
 472         .type = IPUV3M,
 473 };
 474
 475 static struct ipu_devtype ipu_type_imx6q = {
 476         .name = "IPUv3H",
 477         .cm_ofs = 0x00200000,
 478         .cpmem_ofs = 0x00300000,
 479         .srm_ofs = 0x00340000,
 480         .tpm_ofs = 0x00360000,
 481         .disp0_ofs = 0x00240000,
 482         .disp1_ofs = 0x00248000,
 483         .dc_tmpl_ofs = 0x00380000,
 484         .vdi_ofs = 0x00268000,
 485         .type = IPUV3H,
 486 };
 487
 488 static const struct of_device_id imx_ipu_dt_ids[] = {
 489         { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
 490         { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
 491         { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
 492         { /* sentinel */ }
 493 };
 494 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
 495
 496 static int ipu_submodules_init(struct ipu_soc *ipu,
 497                 struct platform_device *pdev, unsigned long ipu_base,
 498                 struct clk *ipu_clk)
 499 {
 500         char *unit;
 501         int ret;
 502         struct device *dev = &pdev->dev;
 503         const struct ipu_devtype *devtype = ipu->devtype;
 504
 505         ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
 506         if (ret) {
 507                 unit = "cpmem";
 508                 goto err_cpmem;
 509         }
 510
 511         ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
 512                         IPU_CONF_DI0_EN, ipu_clk);
 513         if (ret) {
 514                 unit = "di0";
 515                 goto err_di_0;
 516         }
 517
 518         ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
 519                         IPU_CONF_DI1_EN, ipu_clk);
 520         if (ret) {
 521                 unit = "di1";
 522                 goto err_di_1;
 523         }
 524
 525         ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
 526                         IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
 527         if (ret) {
 528                 unit = "dc_template";
 529                 goto err_dc;
 530         }
 531
 532         ret = ipu_dmfc_init(ipu, dev, ipu_base +
 533                         devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
 534         if (ret) {
 535                 unit = "dmfc";
 536                 goto err_dmfc;
 537         }
 538
 539         ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
 540         if (ret) {
 541                 unit = "dp";
 542                 goto err_dp;
 543         }
 544
 545         ret = ipu_smfc_init(ipu, dev, ipu_base +
 546                         devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
 547         if (ret) {
 548                 unit = "smfc";
 549                 goto err_smfc;
 550         }
 551
 552         return 0;
 553
 554 err_smfc:
 555         ipu_dp_exit(ipu);
 556 err_dp:
 557         ipu_dmfc_exit(ipu);
 558 err_dmfc:
 559         ipu_dc_exit(ipu);
 560 err_dc:
 561         ipu_di_exit(ipu, 1);
 562 err_di_1:
 563         ipu_di_exit(ipu, 0);
 564 err_di_0:
 565         ipu_cpmem_exit(ipu);
 566 err_cpmem:
 567         dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
 568         return ret;
 569 }
 570
 571 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
 572 {
 573         unsigned long status;
 574         int i, bit, irq;
 575
 576         for (i = 0; i < num_regs; i++) {
 577
 578                 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
 579                 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
 580
 581                 for_each_set_bit(bit, &status, 32) {
 582                         irq = irq_linear_revmap(ipu->domain,
 583                                                 regs[i] * 32 + bit);
 584                         if (irq)
 585                                 generic_handle_irq(irq);
 586                 }
 587         }
 588 }
 589
 590 static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc)
 591 {
 592         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
 593         const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
 594         struct irq_chip *chip = irq_get_chip(irq);
 595
 596         chained_irq_enter(chip, desc);
 597
 598         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
 599
 600         chained_irq_exit(chip, desc);
 601 }
 602
 603 static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
 604 {
 605         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
 606         const int int_reg[] = { 4, 5, 8, 9};
 607         struct irq_chip *chip = irq_get_chip(irq);
 608
 609         chained_irq_enter(chip, desc);
 610
 611         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
 612
 613         chained_irq_exit(chip, desc);
 614 }
 615
 616 int ipu_map_irq(struct ipu_soc *ipu, int irq)
 617 {
 618         int virq;
 619
 620         virq = irq_linear_revmap(ipu->domain, irq);
 621         if (!virq)
 622                 virq = irq_create_mapping(ipu->domain, irq);
 623
 624         return virq;
 625 }
 626 EXPORT_SYMBOL_GPL(ipu_map_irq);
 627
 628 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
 629                 enum ipu_channel_irq irq_type)
 630 {
 631         return ipu_map_irq(ipu, irq_type + channel->num);
 632 }
 633 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
 634
 635 static void ipu_submodules_exit(struct ipu_soc *ipu)
 636 {
 637         ipu_smfc_exit(ipu);
 638         ipu_dp_exit(ipu);
 639         ipu_dmfc_exit(ipu);
 640         ipu_dc_exit(ipu);
 641         ipu_di_exit(ipu, 1);
 642         ipu_di_exit(ipu, 0);
 643         ipu_cpmem_exit(ipu);
 644 }
 645
 646 static int platform_remove_devices_fn(struct device *dev, void *unused)
 647 {
 648         struct platform_device *pdev = to_platform_device(dev);
 649
 650         platform_device_unregister(pdev);
 651
 652         return 0;
 653 }
 654
 655 static void platform_device_unregister_children(struct platform_device *pdev)
 656 {
 657         device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
 658 }
 659
 660 struct ipu_platform_reg {
 661         struct ipu_client_platformdata pdata;
 662         const char *name;
 663         int reg_offset;
 664 };
 665
 666 static const struct ipu_platform_reg client_reg[] = {
 667         {
 668                 .pdata = {
 669                         .di = 0,
 670                         .dc = 5,
 671                         .dp = IPU_DP_FLOW_SYNC_BG,
 672                         .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
 673                         .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
 674                 },
 675                 .name = "imx-ipuv3-crtc",
 676         }, {
 677                 .pdata = {
 678                         .di = 1,
 679                         .dc = 1,
 680                         .dp = -EINVAL,
 681                         .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
 682                         .dma[1] = -EINVAL,
 683                 },
 684                 .name = "imx-ipuv3-crtc",
 685         }, {
 686                 .pdata = {
 687                         .csi = 0,
 688                         .dma[0] = IPUV3_CHANNEL_CSI0,
 689                         .dma[1] = -EINVAL,
 690                 },
 691                 .reg_offset = IPU_CM_CSI0_REG_OFS,
 692                 .name = "imx-ipuv3-camera",
 693         }, {
 694                 .pdata = {
 695                         .csi = 1,
 696                         .dma[0] = IPUV3_CHANNEL_CSI1,
 697                         .dma[1] = -EINVAL,
 698                 },
 699                 .reg_offset = IPU_CM_CSI1_REG_OFS,
 700                 .name = "imx-ipuv3-camera",
 701         },
 702 };
 703
 704 static DEFINE_MUTEX(ipu_client_id_mutex);
 705 static int ipu_client_id;
 706
 707 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
 708 {
 709         struct device *dev = ipu->dev;
 710         unsigned i;
 711         int id, ret;
 712
 713         mutex_lock(&ipu_client_id_mutex);
 714         id = ipu_client_id;
 715         ipu_client_id += ARRAY_SIZE(client_reg);
 716         mutex_unlock(&ipu_client_id_mutex);
 717
 718         for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
 719                 const struct ipu_platform_reg *reg = &client_reg[i];
 720                 struct platform_device *pdev;
 721                 struct resource res;
 722
 723                 if (reg->reg_offset) {
 724                         memset(&res, 0, sizeof(res));
 725                         res.flags = IORESOURCE_MEM;
 726                         res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset;
 727                         res.end = res.start + PAGE_SIZE - 1;
 728                         pdev = platform_device_register_resndata(dev, reg->name,
 729                                 id++, &res, 1, &reg->pdata, sizeof(reg->pdata));
 730                 } else {
 731                         pdev = platform_device_register_data(dev, reg->name,
 732                                 id++, &reg->pdata, sizeof(reg->pdata));
 733                 }
 734
 735                 if (IS_ERR(pdev))
 736                         goto err_register;
 737         }
 738
 739         return 0;
 740
 741 err_register:
 742         platform_device_unregister_children(to_platform_device(dev));
 743
 744         return ret;
 745 }
 746
 747
 748 static int ipu_irq_init(struct ipu_soc *ipu)
 749 {
 750         struct irq_chip_generic *gc;
 751         struct irq_chip_type *ct;
 752         unsigned long unused[IPU_NUM_IRQS / 32] = {
 753                 0x400100d0, 0xffe000fd,
 754                 0x400100d0, 0xffe000fd,
 755                 0x400100d0, 0xffe000fd,
 756                 0x4077ffff, 0xffe7e1fd,
 757                 0x23fffffe, 0x8880fff0,
 758                 0xf98fe7d0, 0xfff81fff,
 759                 0x400100d0, 0xffe000fd,
 760                 0x00000000,
 761         };
 762         int ret, i;
 763
 764         ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
 765                                             &irq_generic_chip_ops, ipu);
 766         if (!ipu->domain) {
 767                 dev_err(ipu->dev, "failed to add irq domain\n");
 768                 return -ENODEV;
 769         }
 770
 771         ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
 772                                              handle_level_irq, 0,
 773                                              IRQF_VALID, 0);
 774         if (ret < 0) {
 775                 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
 776                 irq_domain_remove(ipu->domain);
 777                 return ret;
 778         }
 779
 780         for (i = 0; i < IPU_NUM_IRQS; i += 32) {
 781                 gc = irq_get_domain_generic_chip(ipu->domain, i);
 782                 gc->reg_base = ipu->cm_reg;
 783                 gc->unused = unused[i / 32];
 784                 ct = gc->chip_types;
 785                 ct->chip.irq_ack = irq_gc_ack_set_bit;
 786                 ct->chip.irq_mask = irq_gc_mask_clr_bit;
 787                 ct->chip.irq_unmask = irq_gc_mask_set_bit;
 788                 ct->regs.ack = IPU_INT_STAT(i / 32);
 789                 ct->regs.mask = IPU_INT_CTRL(i / 32);
 790         }
 791
 792         irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler);
 793         irq_set_handler_data(ipu->irq_sync, ipu);
 794         irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler);
 795         irq_set_handler_data(ipu->irq_err, ipu);
 796
 797         return 0;
 798 }
 799
 800 static void ipu_irq_exit(struct ipu_soc *ipu)
 801 {
 802         int i, irq;
 803
 804         irq_set_chained_handler(ipu->irq_err, NULL);
 805         irq_set_handler_data(ipu->irq_err, NULL);
 806         irq_set_chained_handler(ipu->irq_sync, NULL);
 807         irq_set_handler_data(ipu->irq_sync, NULL);
 808
 809         /* TODO: remove irq_domain_generic_chips */
 810
 811         for (i = 0; i < IPU_NUM_IRQS; i++) {
 812                 irq = irq_linear_revmap(ipu->domain, i);
 813                 if (irq)
 814                         irq_dispose_mapping(irq);
 815         }
 816
 817         irq_domain_remove(ipu->domain);
 818 }
 819
 820 static int ipu_probe(struct platform_device *pdev)
 821 {
 822         const struct of_device_id *of_id =
 823                         of_match_device(imx_ipu_dt_ids, &pdev->dev);
 824         struct ipu_soc *ipu;
 825         struct resource *res;
 826         unsigned long ipu_base;
 827         int i, ret, irq_sync, irq_err;
 828         const struct ipu_devtype *devtype;
 829
 830         devtype = of_id->data;
 831
 832         irq_sync = platform_get_irq(pdev, 0);
 833         irq_err = platform_get_irq(pdev, 1);
 834         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 835
 836         dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
 837                         irq_sync, irq_err);
 838
 839         if (!res || irq_sync < 0 || irq_err < 0)
 840                 return -ENODEV;
 841
 842         ipu_base = res->start;
 843
 844         ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
 845         if (!ipu)
 846                 return -ENODEV;
 847
 848         for (i = 0; i < 64; i++)
 849                 ipu->channel[i].ipu = ipu;
 850         ipu->devtype = devtype;
 851         ipu->ipu_type = devtype->type;
 852
 853         spin_lock_init(&ipu->lock);
 854         mutex_init(&ipu->channel_lock);
 855
 856         dev_dbg(&pdev->dev, "cm_reg:   0x%08lx\n",
 857                         ipu_base + devtype->cm_ofs);
 858         dev_dbg(&pdev->dev, "idmac:    0x%08lx\n",
 859                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
 860         dev_dbg(&pdev->dev, "cpmem:    0x%08lx\n",
 861                         ipu_base + devtype->cpmem_ofs);
 862         dev_dbg(&pdev->dev, "disp0:    0x%08lx\n",
 863                         ipu_base + devtype->disp0_ofs);
 864         dev_dbg(&pdev->dev, "disp1:    0x%08lx\n",
 865                         ipu_base + devtype->disp1_ofs);
 866         dev_dbg(&pdev->dev, "srm:      0x%08lx\n",
 867                         ipu_base + devtype->srm_ofs);
 868         dev_dbg(&pdev->dev, "tpm:      0x%08lx\n",
 869                         ipu_base + devtype->tpm_ofs);
 870         dev_dbg(&pdev->dev, "dc:       0x%08lx\n",
 871                         ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
 872         dev_dbg(&pdev->dev, "ic:       0x%08lx\n",
 873                         ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
 874         dev_dbg(&pdev->dev, "dmfc:     0x%08lx\n",
 875                         ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
 876         dev_dbg(&pdev->dev, "vdi:      0x%08lx\n",
 877                         ipu_base + devtype->vdi_ofs);
 878
 879         ipu->cm_reg = devm_ioremap(&pdev->dev,
 880                         ipu_base + devtype->cm_ofs, PAGE_SIZE);
 881         ipu->idmac_reg = devm_ioremap(&pdev->dev,
 882                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
 883                         PAGE_SIZE);
 884
 885         if (!ipu->cm_reg || !ipu->idmac_reg)
 886                 return -ENOMEM;
 887
 888         ipu->clk = devm_clk_get(&pdev->dev, "bus");
 889         if (IS_ERR(ipu->clk)) {
 890                 ret = PTR_ERR(ipu->clk);
 891                 dev_err(&pdev->dev, "clk_get failed with %d", ret);
 892                 return ret;
 893         }
 894
 895         platform_set_drvdata(pdev, ipu);
 896
 897         ret = clk_prepare_enable(ipu->clk);
 898         if (ret) {
 899                 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
 900                 return ret;
 901         }
 902
 903         ipu->dev = &pdev->dev;
 904         ipu->irq_sync = irq_sync;
 905         ipu->irq_err = irq_err;
 906
 907         ret = ipu_irq_init(ipu);
 908         if (ret)
 909                 goto out_failed_irq;
 910
 911         ret = device_reset(&pdev->dev);
 912         if (ret) {
 913                 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
 914                 goto out_failed_reset;
 915         }
 916         ret = ipu_memory_reset(ipu);
 917         if (ret)
 918                 goto out_failed_reset;
 919
 920         /* Set MCU_T to divide MCU access window into 2 */
 921         ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
 922                         IPU_DISP_GEN);
 923
 924         ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
 925         if (ret)
 926                 goto failed_submodules_init;
 927
 928         ret = ipu_add_client_devices(ipu, ipu_base);
 929         if (ret) {
 930                 dev_err(&pdev->dev, "adding client devices failed with %d\n",
 931                                 ret);
 932                 goto failed_add_clients;
 933         }
 934
 935         dev_info(&pdev->dev, "%s probed\n", devtype->name);
 936
 937         return 0;
 938
 939 failed_add_clients:
 940         ipu_submodules_exit(ipu);
 941 failed_submodules_init:
 942 out_failed_reset:
 943         ipu_irq_exit(ipu);
 944 out_failed_irq:
 945         clk_disable_unprepare(ipu->clk);
 946         return ret;
 947 }
 948
 949 static int ipu_remove(struct platform_device *pdev)
 950 {
 951         struct ipu_soc *ipu = platform_get_drvdata(pdev);
 952
 953         platform_device_unregister_children(pdev);
 954         ipu_submodules_exit(ipu);
 955         ipu_irq_exit(ipu);
 956
 957         clk_disable_unprepare(ipu->clk);
 958
 959         return 0;
 960 }
 961
 962 static struct platform_driver imx_ipu_driver = {
 963         .driver = {
 964                 .name = "imx-ipuv3",
 965                 .of_match_table = imx_ipu_dt_ids,
 966         },
 967         .probe = ipu_probe,
 968         .remove = ipu_remove,
 969 };
 970
 971 module_platform_driver(imx_ipu_driver);
 972
 973 MODULE_ALIAS("platform:imx-ipuv3");
 974 MODULE_DESCRIPTION("i.MX IPU v3 driver");
 975 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
 976 MODULE_LICENSE("GPL");