2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 #include <linux/module.h>
16 #include <linux/export.h>
17 #include <linux/types.h>
18 #include <linux/reset.h>
19 #include <linux/platform_device.h>
20 #include <linux/err.h>
21 #include <linux/spinlock.h>
22 #include <linux/delay.h>
23 #include <linux/interrupt.h>
25 #include <linux/clk.h>
26 #include <linux/list.h>
27 #include <linux/irq.h>
28 #include <linux/irqchip/chained_irq.h>
29 #include <linux/irqdomain.h>
30 #include <linux/of_device.h>
31 #include <linux/of_graph.h>
33 #include <drm/drm_fourcc.h>
35 #include <video/imx-ipu-v3.h>
38 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
40 return readl(ipu->cm_reg + offset);
43 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
45 writel(value, ipu->cm_reg + offset);
48 int ipu_get_num(struct ipu_soc *ipu)
52 EXPORT_SYMBOL_GPL(ipu_get_num);
54 void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
58 val = ipu_cm_read(ipu, IPU_SRM_PRI2);
60 ipu_cm_write(ipu, val, IPU_SRM_PRI2);
62 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
64 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
67 case DRM_FORMAT_ARGB1555:
68 case DRM_FORMAT_ABGR1555:
69 case DRM_FORMAT_RGBA5551:
70 case DRM_FORMAT_BGRA5551:
71 case DRM_FORMAT_RGB565:
72 case DRM_FORMAT_BGR565:
73 case DRM_FORMAT_RGB888:
74 case DRM_FORMAT_BGR888:
75 case DRM_FORMAT_ARGB4444:
76 case DRM_FORMAT_XRGB8888:
77 case DRM_FORMAT_XBGR8888:
78 case DRM_FORMAT_RGBX8888:
79 case DRM_FORMAT_BGRX8888:
80 case DRM_FORMAT_ARGB8888:
81 case DRM_FORMAT_ABGR8888:
82 case DRM_FORMAT_RGBA8888:
83 case DRM_FORMAT_BGRA8888:
84 return IPUV3_COLORSPACE_RGB;
87 case DRM_FORMAT_YUV420:
88 case DRM_FORMAT_YVU420:
89 case DRM_FORMAT_YUV422:
90 case DRM_FORMAT_YVU422:
95 return IPUV3_COLORSPACE_YUV;
97 return IPUV3_COLORSPACE_UNKNOWN;
100 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
102 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
104 switch (pixelformat) {
105 case V4L2_PIX_FMT_YUV420:
106 case V4L2_PIX_FMT_YVU420:
107 case V4L2_PIX_FMT_YUV422P:
108 case V4L2_PIX_FMT_UYVY:
109 case V4L2_PIX_FMT_YUYV:
110 case V4L2_PIX_FMT_NV12:
111 case V4L2_PIX_FMT_NV21:
112 case V4L2_PIX_FMT_NV16:
113 case V4L2_PIX_FMT_NV61:
114 return IPUV3_COLORSPACE_YUV;
115 case V4L2_PIX_FMT_RGB32:
116 case V4L2_PIX_FMT_BGR32:
117 case V4L2_PIX_FMT_RGB24:
118 case V4L2_PIX_FMT_BGR24:
119 case V4L2_PIX_FMT_RGB565:
120 return IPUV3_COLORSPACE_RGB;
122 return IPUV3_COLORSPACE_UNKNOWN;
125 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
127 bool ipu_pixelformat_is_planar(u32 pixelformat)
129 switch (pixelformat) {
130 case V4L2_PIX_FMT_YUV420:
131 case V4L2_PIX_FMT_YVU420:
132 case V4L2_PIX_FMT_YUV422P:
133 case V4L2_PIX_FMT_NV12:
134 case V4L2_PIX_FMT_NV21:
135 case V4L2_PIX_FMT_NV16:
136 case V4L2_PIX_FMT_NV61:
142 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
144 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
146 switch (mbus_code & 0xf000) {
148 return IPUV3_COLORSPACE_RGB;
150 return IPUV3_COLORSPACE_YUV;
152 return IPUV3_COLORSPACE_UNKNOWN;
155 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
157 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
159 switch (pixelformat) {
160 case V4L2_PIX_FMT_YUV420:
161 case V4L2_PIX_FMT_YVU420:
162 case V4L2_PIX_FMT_YUV422P:
163 case V4L2_PIX_FMT_NV12:
164 case V4L2_PIX_FMT_NV21:
165 case V4L2_PIX_FMT_NV16:
166 case V4L2_PIX_FMT_NV61:
168 * for the planar YUV formats, the stride passed to
169 * cpmem must be the stride in bytes of the Y plane.
170 * And all the planar YUV formats have an 8-bit
173 return (8 * pixel_stride) >> 3;
174 case V4L2_PIX_FMT_RGB565:
175 case V4L2_PIX_FMT_YUYV:
176 case V4L2_PIX_FMT_UYVY:
177 return (16 * pixel_stride) >> 3;
178 case V4L2_PIX_FMT_BGR24:
179 case V4L2_PIX_FMT_RGB24:
180 return (24 * pixel_stride) >> 3;
181 case V4L2_PIX_FMT_BGR32:
182 case V4L2_PIX_FMT_RGB32:
183 return (32 * pixel_stride) >> 3;
190 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
192 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
193 bool hflip, bool vflip)
219 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
222 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
224 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
225 bool hflip, bool vflip)
229 r90 = ((u32)mode >> 2) & 0x1;
230 hf = ((u32)mode >> 1) & 0x1;
231 vf = ((u32)mode >> 0) & 0x1;
235 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
236 case IPU_ROTATE_NONE:
239 case IPU_ROTATE_90_RIGHT:
245 case IPU_ROTATE_90_LEFT:
254 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
256 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
258 struct ipuv3_channel *channel;
260 dev_dbg(ipu->dev, "%s %d\n", __func__, num);
263 return ERR_PTR(-ENODEV);
265 mutex_lock(&ipu->channel_lock);
267 channel = &ipu->channel[num];
270 channel = ERR_PTR(-EBUSY);
274 channel->busy = true;
278 mutex_unlock(&ipu->channel_lock);
282 EXPORT_SYMBOL_GPL(ipu_idmac_get);
284 void ipu_idmac_put(struct ipuv3_channel *channel)
286 struct ipu_soc *ipu = channel->ipu;
288 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
290 mutex_lock(&ipu->channel_lock);
292 channel->busy = false;
294 mutex_unlock(&ipu->channel_lock);
296 EXPORT_SYMBOL_GPL(ipu_idmac_put);
298 #define idma_mask(ch) (1 << ((ch) & 0x1f))
301 * This is an undocumented feature, a write one to a channel bit in
302 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
303 * internal current buffer pointer so that transfers start from buffer
304 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
305 * only says these are read-only registers). This operation is required
306 * for channel linking to work correctly, for instance video capture
307 * pipelines that carry out image rotations will fail after the first
308 * streaming unless this function is called for each channel before
309 * re-enabling the channels.
311 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
313 struct ipu_soc *ipu = channel->ipu;
314 unsigned int chno = channel->num;
316 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
319 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
322 struct ipu_soc *ipu = channel->ipu;
326 spin_lock_irqsave(&ipu->lock, flags);
328 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
330 reg |= idma_mask(channel->num);
332 reg &= ~idma_mask(channel->num);
333 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
335 __ipu_idmac_reset_current_buffer(channel);
337 spin_unlock_irqrestore(&ipu->lock, flags);
339 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
341 static const struct {
345 } idmac_lock_en_info[] = {
346 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, },
347 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, },
348 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, },
349 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, },
350 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, },
351 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
352 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
353 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
354 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
355 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
356 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
357 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, },
358 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, },
359 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, },
360 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, },
361 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, },
362 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
365 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
367 struct ipu_soc *ipu = channel->ipu;
372 switch (num_bursts) {
375 bursts = 0x00; /* locking disabled */
390 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
391 if (channel->num == idmac_lock_en_info[i].chnum)
394 if (i >= ARRAY_SIZE(idmac_lock_en_info))
397 spin_lock_irqsave(&ipu->lock, flags);
399 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
400 regval &= ~(0x03 << idmac_lock_en_info[i].shift);
401 regval |= (bursts << idmac_lock_en_info[i].shift);
402 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
404 spin_unlock_irqrestore(&ipu->lock, flags);
408 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
410 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
412 unsigned long lock_flags;
415 spin_lock_irqsave(&ipu->lock, lock_flags);
417 val = ipu_cm_read(ipu, IPU_DISP_GEN);
419 if (mask & IPU_CONF_DI0_EN)
420 val |= IPU_DI0_COUNTER_RELEASE;
421 if (mask & IPU_CONF_DI1_EN)
422 val |= IPU_DI1_COUNTER_RELEASE;
424 ipu_cm_write(ipu, val, IPU_DISP_GEN);
426 val = ipu_cm_read(ipu, IPU_CONF);
428 ipu_cm_write(ipu, val, IPU_CONF);
430 spin_unlock_irqrestore(&ipu->lock, lock_flags);
434 EXPORT_SYMBOL_GPL(ipu_module_enable);
436 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
438 unsigned long lock_flags;
441 spin_lock_irqsave(&ipu->lock, lock_flags);
443 val = ipu_cm_read(ipu, IPU_CONF);
445 ipu_cm_write(ipu, val, IPU_CONF);
447 val = ipu_cm_read(ipu, IPU_DISP_GEN);
449 if (mask & IPU_CONF_DI0_EN)
450 val &= ~IPU_DI0_COUNTER_RELEASE;
451 if (mask & IPU_CONF_DI1_EN)
452 val &= ~IPU_DI1_COUNTER_RELEASE;
454 ipu_cm_write(ipu, val, IPU_DISP_GEN);
456 spin_unlock_irqrestore(&ipu->lock, lock_flags);
460 EXPORT_SYMBOL_GPL(ipu_module_disable);
462 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
464 struct ipu_soc *ipu = channel->ipu;
465 unsigned int chno = channel->num;
467 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
469 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
471 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
473 struct ipu_soc *ipu = channel->ipu;
477 spin_lock_irqsave(&ipu->lock, flags);
480 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
483 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
486 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
489 spin_unlock_irqrestore(&ipu->lock, flags);
491 return ((reg & idma_mask(channel->num)) != 0);
493 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
495 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
497 struct ipu_soc *ipu = channel->ipu;
498 unsigned int chno = channel->num;
501 spin_lock_irqsave(&ipu->lock, flags);
503 /* Mark buffer as ready. */
505 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
507 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
509 spin_unlock_irqrestore(&ipu->lock, flags);
511 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
513 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
515 struct ipu_soc *ipu = channel->ipu;
516 unsigned int chno = channel->num;
519 spin_lock_irqsave(&ipu->lock, flags);
521 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
524 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
527 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
530 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
535 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
537 spin_unlock_irqrestore(&ipu->lock, flags);
539 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
541 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
543 struct ipu_soc *ipu = channel->ipu;
547 spin_lock_irqsave(&ipu->lock, flags);
549 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
550 val |= idma_mask(channel->num);
551 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
553 spin_unlock_irqrestore(&ipu->lock, flags);
557 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
559 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
561 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
563 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
565 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
567 struct ipu_soc *ipu = channel->ipu;
568 unsigned long timeout;
570 timeout = jiffies + msecs_to_jiffies(ms);
571 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
572 idma_mask(channel->num)) {
573 if (time_after(jiffies, timeout))
580 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
582 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
584 unsigned long timeout;
586 timeout = jiffies + msecs_to_jiffies(ms);
587 ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
588 while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
589 if (time_after(jiffies, timeout))
596 EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
598 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
600 struct ipu_soc *ipu = channel->ipu;
604 spin_lock_irqsave(&ipu->lock, flags);
606 /* Disable DMA channel(s) */
607 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
608 val &= ~idma_mask(channel->num);
609 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
611 __ipu_idmac_reset_current_buffer(channel);
613 /* Set channel buffers NOT to be ready */
614 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
616 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
617 idma_mask(channel->num)) {
618 ipu_cm_write(ipu, idma_mask(channel->num),
619 IPU_CHA_BUF0_RDY(channel->num));
622 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
623 idma_mask(channel->num)) {
624 ipu_cm_write(ipu, idma_mask(channel->num),
625 IPU_CHA_BUF1_RDY(channel->num));
628 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
630 /* Reset the double buffer */
631 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
632 val &= ~idma_mask(channel->num);
633 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
635 spin_unlock_irqrestore(&ipu->lock, flags);
639 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
642 * The imx6 rev. D TRM says that enabling the WM feature will increase
643 * a channel's priority. Refer to Table 36-8 Calculated priority value.
644 * The sub-module that is the sink or source for the channel must enable
645 * watermark signal for this to take effect (SMFC_WM for instance).
647 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
649 struct ipu_soc *ipu = channel->ipu;
653 spin_lock_irqsave(&ipu->lock, flags);
655 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
657 val |= 1 << (channel->num % 32);
659 val &= ~(1 << (channel->num % 32));
660 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
662 spin_unlock_irqrestore(&ipu->lock, flags);
664 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
666 static int ipu_memory_reset(struct ipu_soc *ipu)
668 unsigned long timeout;
670 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
672 timeout = jiffies + msecs_to_jiffies(1000);
673 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
674 if (time_after(jiffies, timeout))
683 * Set the source mux for the given CSI. Selects either parallel or
686 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
691 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
692 IPU_CONF_CSI0_DATA_SOURCE;
694 spin_lock_irqsave(&ipu->lock, flags);
696 val = ipu_cm_read(ipu, IPU_CONF);
701 ipu_cm_write(ipu, val, IPU_CONF);
703 spin_unlock_irqrestore(&ipu->lock, flags);
705 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
708 * Set the source mux for the IC. Selects either CSI[01] or the VDI.
710 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
715 spin_lock_irqsave(&ipu->lock, flags);
717 val = ipu_cm_read(ipu, IPU_CONF);
719 val |= IPU_CONF_IC_INPUT;
721 val &= ~IPU_CONF_IC_INPUT;
723 val |= IPU_CONF_CSI_SEL;
725 val &= ~IPU_CONF_CSI_SEL;
727 ipu_cm_write(ipu, val, IPU_CONF);
729 spin_unlock_irqrestore(&ipu->lock, flags);
731 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
734 /* Frame Synchronization Unit Channel Linking */
736 struct fsu_link_reg_info {
743 struct fsu_link_info {
744 struct fsu_link_reg_info src;
745 struct fsu_link_reg_info sink;
748 static const struct fsu_link_info fsu_link_info[] = {
750 .src = { IPUV3_CHANNEL_IC_PRP_ENC_MEM, IPU_FS_PROC_FLOW2,
751 FS_PRP_ENC_DEST_SEL_MASK, FS_PRP_ENC_DEST_SEL_IRT_ENC },
752 .sink = { IPUV3_CHANNEL_MEM_ROT_ENC, IPU_FS_PROC_FLOW1,
753 FS_PRPENC_ROT_SRC_SEL_MASK, FS_PRPENC_ROT_SRC_SEL_ENC },
755 .src = { IPUV3_CHANNEL_IC_PRP_VF_MEM, IPU_FS_PROC_FLOW2,
756 FS_PRPVF_DEST_SEL_MASK, FS_PRPVF_DEST_SEL_IRT_VF },
757 .sink = { IPUV3_CHANNEL_MEM_ROT_VF, IPU_FS_PROC_FLOW1,
758 FS_PRPVF_ROT_SRC_SEL_MASK, FS_PRPVF_ROT_SRC_SEL_VF },
760 .src = { IPUV3_CHANNEL_IC_PP_MEM, IPU_FS_PROC_FLOW2,
761 FS_PP_DEST_SEL_MASK, FS_PP_DEST_SEL_IRT_PP },
762 .sink = { IPUV3_CHANNEL_MEM_ROT_PP, IPU_FS_PROC_FLOW1,
763 FS_PP_ROT_SRC_SEL_MASK, FS_PP_ROT_SRC_SEL_PP },
765 .src = { IPUV3_CHANNEL_CSI_DIRECT, 0 },
766 .sink = { IPUV3_CHANNEL_CSI_VDI_PREV, IPU_FS_PROC_FLOW1,
767 FS_VDI_SRC_SEL_MASK, FS_VDI_SRC_SEL_CSI_DIRECT },
771 static const struct fsu_link_info *find_fsu_link_info(int src, int sink)
775 for (i = 0; i < ARRAY_SIZE(fsu_link_info); i++) {
776 if (src == fsu_link_info[i].src.chno &&
777 sink == fsu_link_info[i].sink.chno)
778 return &fsu_link_info[i];
785 * Links a source channel to a sink channel in the FSU.
787 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch)
789 const struct fsu_link_info *link;
790 u32 src_reg, sink_reg;
793 link = find_fsu_link_info(src_ch, sink_ch);
797 spin_lock_irqsave(&ipu->lock, flags);
799 if (link->src.mask) {
800 src_reg = ipu_cm_read(ipu, link->src.reg);
801 src_reg &= ~link->src.mask;
802 src_reg |= link->src.val;
803 ipu_cm_write(ipu, src_reg, link->src.reg);
806 if (link->sink.mask) {
807 sink_reg = ipu_cm_read(ipu, link->sink.reg);
808 sink_reg &= ~link->sink.mask;
809 sink_reg |= link->sink.val;
810 ipu_cm_write(ipu, sink_reg, link->sink.reg);
813 spin_unlock_irqrestore(&ipu->lock, flags);
816 EXPORT_SYMBOL_GPL(ipu_fsu_link);
819 * Unlinks source and sink channels in the FSU.
821 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch)
823 const struct fsu_link_info *link;
824 u32 src_reg, sink_reg;
827 link = find_fsu_link_info(src_ch, sink_ch);
831 spin_lock_irqsave(&ipu->lock, flags);
833 if (link->src.mask) {
834 src_reg = ipu_cm_read(ipu, link->src.reg);
835 src_reg &= ~link->src.mask;
836 ipu_cm_write(ipu, src_reg, link->src.reg);
839 if (link->sink.mask) {
840 sink_reg = ipu_cm_read(ipu, link->sink.reg);
841 sink_reg &= ~link->sink.mask;
842 ipu_cm_write(ipu, sink_reg, link->sink.reg);
845 spin_unlock_irqrestore(&ipu->lock, flags);
848 EXPORT_SYMBOL_GPL(ipu_fsu_unlink);
850 /* Link IDMAC channels in the FSU */
851 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink)
853 return ipu_fsu_link(src->ipu, src->num, sink->num);
855 EXPORT_SYMBOL_GPL(ipu_idmac_link);
857 /* Unlink IDMAC channels in the FSU */
858 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink)
860 return ipu_fsu_unlink(src->ipu, src->num, sink->num);
862 EXPORT_SYMBOL_GPL(ipu_idmac_unlink);
866 unsigned long cm_ofs;
867 unsigned long cpmem_ofs;
868 unsigned long srm_ofs;
869 unsigned long tpm_ofs;
870 unsigned long csi0_ofs;
871 unsigned long csi1_ofs;
872 unsigned long ic_ofs;
873 unsigned long disp0_ofs;
874 unsigned long disp1_ofs;
875 unsigned long dc_tmpl_ofs;
876 unsigned long vdi_ofs;
877 enum ipuv3_type type;
880 static struct ipu_devtype ipu_type_imx51 = {
882 .cm_ofs = 0x1e000000,
883 .cpmem_ofs = 0x1f000000,
884 .srm_ofs = 0x1f040000,
885 .tpm_ofs = 0x1f060000,
886 .csi0_ofs = 0x1f030000,
887 .csi1_ofs = 0x1f038000,
888 .ic_ofs = 0x1e020000,
889 .disp0_ofs = 0x1e040000,
890 .disp1_ofs = 0x1e048000,
891 .dc_tmpl_ofs = 0x1f080000,
892 .vdi_ofs = 0x1e068000,
896 static struct ipu_devtype ipu_type_imx53 = {
898 .cm_ofs = 0x06000000,
899 .cpmem_ofs = 0x07000000,
900 .srm_ofs = 0x07040000,
901 .tpm_ofs = 0x07060000,
902 .csi0_ofs = 0x07030000,
903 .csi1_ofs = 0x07038000,
904 .ic_ofs = 0x06020000,
905 .disp0_ofs = 0x06040000,
906 .disp1_ofs = 0x06048000,
907 .dc_tmpl_ofs = 0x07080000,
908 .vdi_ofs = 0x06068000,
912 static struct ipu_devtype ipu_type_imx6q = {
914 .cm_ofs = 0x00200000,
915 .cpmem_ofs = 0x00300000,
916 .srm_ofs = 0x00340000,
917 .tpm_ofs = 0x00360000,
918 .csi0_ofs = 0x00230000,
919 .csi1_ofs = 0x00238000,
920 .ic_ofs = 0x00220000,
921 .disp0_ofs = 0x00240000,
922 .disp1_ofs = 0x00248000,
923 .dc_tmpl_ofs = 0x00380000,
924 .vdi_ofs = 0x00268000,
928 static const struct of_device_id imx_ipu_dt_ids[] = {
929 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
930 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
931 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
934 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
936 static int ipu_submodules_init(struct ipu_soc *ipu,
937 struct platform_device *pdev, unsigned long ipu_base,
942 struct device *dev = &pdev->dev;
943 const struct ipu_devtype *devtype = ipu->devtype;
945 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
951 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
952 IPU_CONF_CSI0_EN, ipu_clk);
958 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
959 IPU_CONF_CSI1_EN, ipu_clk);
965 ret = ipu_ic_init(ipu, dev,
966 ipu_base + devtype->ic_ofs,
967 ipu_base + devtype->tpm_ofs);
973 ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs,
974 IPU_CONF_VDI_EN | IPU_CONF_ISP_EN |
981 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
982 IPU_CONF_DI0_EN, ipu_clk);
988 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
989 IPU_CONF_DI1_EN, ipu_clk);
995 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
996 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
998 unit = "dc_template";
1002 ret = ipu_dmfc_init(ipu, dev, ipu_base +
1003 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
1009 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
1015 ret = ipu_smfc_init(ipu, dev, ipu_base +
1016 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
1031 ipu_di_exit(ipu, 1);
1033 ipu_di_exit(ipu, 0);
1039 ipu_csi_exit(ipu, 1);
1041 ipu_csi_exit(ipu, 0);
1043 ipu_cpmem_exit(ipu);
1045 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
1049 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
1051 unsigned long status;
1054 for (i = 0; i < num_regs; i++) {
1056 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
1057 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
1059 for_each_set_bit(bit, &status, 32) {
1060 irq = irq_linear_revmap(ipu->domain,
1061 regs[i] * 32 + bit);
1063 generic_handle_irq(irq);
1068 static void ipu_irq_handler(struct irq_desc *desc)
1070 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1071 struct irq_chip *chip = irq_desc_get_chip(desc);
1072 const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
1074 chained_irq_enter(chip, desc);
1076 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1078 chained_irq_exit(chip, desc);
1081 static void ipu_err_irq_handler(struct irq_desc *desc)
1083 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
1084 struct irq_chip *chip = irq_desc_get_chip(desc);
1085 const int int_reg[] = { 4, 5, 8, 9};
1087 chained_irq_enter(chip, desc);
1089 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
1091 chained_irq_exit(chip, desc);
1094 int ipu_map_irq(struct ipu_soc *ipu, int irq)
1098 virq = irq_linear_revmap(ipu->domain, irq);
1100 virq = irq_create_mapping(ipu->domain, irq);
1104 EXPORT_SYMBOL_GPL(ipu_map_irq);
1106 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
1107 enum ipu_channel_irq irq_type)
1109 return ipu_map_irq(ipu, irq_type + channel->num);
1111 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
1113 static void ipu_submodules_exit(struct ipu_soc *ipu)
1119 ipu_di_exit(ipu, 1);
1120 ipu_di_exit(ipu, 0);
1123 ipu_csi_exit(ipu, 1);
1124 ipu_csi_exit(ipu, 0);
1125 ipu_cpmem_exit(ipu);
1128 static int platform_remove_devices_fn(struct device *dev, void *unused)
1130 struct platform_device *pdev = to_platform_device(dev);
1132 platform_device_unregister(pdev);
1137 static void platform_device_unregister_children(struct platform_device *pdev)
1139 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
1142 struct ipu_platform_reg {
1143 struct ipu_client_platformdata pdata;
1147 /* These must be in the order of the corresponding device tree port nodes */
1148 static struct ipu_platform_reg client_reg[] = {
1152 .dma[0] = IPUV3_CHANNEL_CSI0,
1155 .name = "imx-ipuv3-csi",
1159 .dma[0] = IPUV3_CHANNEL_CSI1,
1162 .name = "imx-ipuv3-csi",
1167 .dp = IPU_DP_FLOW_SYNC_BG,
1168 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
1169 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
1171 .name = "imx-ipuv3-crtc",
1177 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
1180 .name = "imx-ipuv3-crtc",
1184 static DEFINE_MUTEX(ipu_client_id_mutex);
1185 static int ipu_client_id;
1187 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
1189 struct device *dev = ipu->dev;
1193 mutex_lock(&ipu_client_id_mutex);
1195 ipu_client_id += ARRAY_SIZE(client_reg);
1196 mutex_unlock(&ipu_client_id_mutex);
1198 for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
1199 struct ipu_platform_reg *reg = &client_reg[i];
1200 struct platform_device *pdev;
1201 struct device_node *of_node;
1203 /* Associate subdevice with the corresponding port node */
1204 of_node = of_graph_get_port_by_id(dev->of_node, i);
1207 "no port@%d node in %s, not using %s%d\n",
1208 i, dev->of_node->full_name,
1209 (i / 2) ? "DI" : "CSI", i % 2);
1213 pdev = platform_device_alloc(reg->name, id++);
1219 pdev->dev.parent = dev;
1221 reg->pdata.of_node = of_node;
1222 ret = platform_device_add_data(pdev, ®->pdata,
1223 sizeof(reg->pdata));
1225 ret = platform_device_add(pdev);
1227 platform_device_put(pdev);
1232 * Set of_node only after calling platform_device_add. Otherwise
1233 * the platform:imx-ipuv3-crtc modalias won't be used.
1235 pdev->dev.of_node = of_node;
1241 platform_device_unregister_children(to_platform_device(dev));
1247 static int ipu_irq_init(struct ipu_soc *ipu)
1249 struct irq_chip_generic *gc;
1250 struct irq_chip_type *ct;
1251 unsigned long unused[IPU_NUM_IRQS / 32] = {
1252 0x400100d0, 0xffe000fd,
1253 0x400100d0, 0xffe000fd,
1254 0x400100d0, 0xffe000fd,
1255 0x4077ffff, 0xffe7e1fd,
1256 0x23fffffe, 0x8880fff0,
1257 0xf98fe7d0, 0xfff81fff,
1258 0x400100d0, 0xffe000fd,
1263 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
1264 &irq_generic_chip_ops, ipu);
1266 dev_err(ipu->dev, "failed to add irq domain\n");
1270 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1271 handle_level_irq, 0, 0, 0);
1273 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1274 irq_domain_remove(ipu->domain);
1278 for (i = 0; i < IPU_NUM_IRQS; i += 32)
1279 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
1281 for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1282 gc = irq_get_domain_generic_chip(ipu->domain, i);
1283 gc->reg_base = ipu->cm_reg;
1284 gc->unused = unused[i / 32];
1285 ct = gc->chip_types;
1286 ct->chip.irq_ack = irq_gc_ack_set_bit;
1287 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1288 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1289 ct->regs.ack = IPU_INT_STAT(i / 32);
1290 ct->regs.mask = IPU_INT_CTRL(i / 32);
1293 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
1294 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
1300 static void ipu_irq_exit(struct ipu_soc *ipu)
1304 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
1305 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
1307 /* TODO: remove irq_domain_generic_chips */
1309 for (i = 0; i < IPU_NUM_IRQS; i++) {
1310 irq = irq_linear_revmap(ipu->domain, i);
1312 irq_dispose_mapping(irq);
1315 irq_domain_remove(ipu->domain);
1318 void ipu_dump(struct ipu_soc *ipu)
1322 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
1323 ipu_cm_read(ipu, IPU_CONF));
1324 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
1325 ipu_idmac_read(ipu, IDMAC_CONF));
1326 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
1327 ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
1328 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
1329 ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
1330 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1331 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
1332 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1333 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
1334 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
1335 ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
1336 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
1337 ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
1338 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1339 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
1340 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1341 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
1342 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1343 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
1344 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1345 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
1346 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1347 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
1348 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1349 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
1350 for (i = 0; i < 15; i++)
1351 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
1352 ipu_cm_read(ipu, IPU_INT_CTRL(i)));
1354 EXPORT_SYMBOL_GPL(ipu_dump);
1356 static int ipu_probe(struct platform_device *pdev)
1358 const struct of_device_id *of_id =
1359 of_match_device(imx_ipu_dt_ids, &pdev->dev);
1360 struct device_node *np = pdev->dev.of_node;
1361 struct ipu_soc *ipu;
1362 struct resource *res;
1363 unsigned long ipu_base;
1364 int i, ret, irq_sync, irq_err;
1365 const struct ipu_devtype *devtype;
1367 devtype = of_id->data;
1369 irq_sync = platform_get_irq(pdev, 0);
1370 irq_err = platform_get_irq(pdev, 1);
1371 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1373 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
1376 if (!res || irq_sync < 0 || irq_err < 0)
1379 ipu_base = res->start;
1381 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1385 for (i = 0; i < 64; i++)
1386 ipu->channel[i].ipu = ipu;
1387 ipu->devtype = devtype;
1388 ipu->ipu_type = devtype->type;
1389 ipu->id = of_alias_get_id(np, "ipu");
1391 spin_lock_init(&ipu->lock);
1392 mutex_init(&ipu->channel_lock);
1394 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
1395 ipu_base + devtype->cm_ofs);
1396 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n",
1397 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1398 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
1399 ipu_base + devtype->cpmem_ofs);
1400 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n",
1401 ipu_base + devtype->csi0_ofs);
1402 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n",
1403 ipu_base + devtype->csi1_ofs);
1404 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1405 ipu_base + devtype->ic_ofs);
1406 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
1407 ipu_base + devtype->disp0_ofs);
1408 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
1409 ipu_base + devtype->disp1_ofs);
1410 dev_dbg(&pdev->dev, "srm: 0x%08lx\n",
1411 ipu_base + devtype->srm_ofs);
1412 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n",
1413 ipu_base + devtype->tpm_ofs);
1414 dev_dbg(&pdev->dev, "dc: 0x%08lx\n",
1415 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1416 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1417 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1418 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n",
1419 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1420 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n",
1421 ipu_base + devtype->vdi_ofs);
1423 ipu->cm_reg = devm_ioremap(&pdev->dev,
1424 ipu_base + devtype->cm_ofs, PAGE_SIZE);
1425 ipu->idmac_reg = devm_ioremap(&pdev->dev,
1426 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1429 if (!ipu->cm_reg || !ipu->idmac_reg)
1432 ipu->clk = devm_clk_get(&pdev->dev, "bus");
1433 if (IS_ERR(ipu->clk)) {
1434 ret = PTR_ERR(ipu->clk);
1435 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1439 platform_set_drvdata(pdev, ipu);
1441 ret = clk_prepare_enable(ipu->clk);
1443 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1447 ipu->dev = &pdev->dev;
1448 ipu->irq_sync = irq_sync;
1449 ipu->irq_err = irq_err;
1451 ret = device_reset(&pdev->dev);
1453 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1454 goto out_failed_reset;
1456 ret = ipu_memory_reset(ipu);
1458 goto out_failed_reset;
1460 ret = ipu_irq_init(ipu);
1462 goto out_failed_irq;
1464 /* Set MCU_T to divide MCU access window into 2 */
1465 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1468 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1470 goto failed_submodules_init;
1472 ret = ipu_add_client_devices(ipu, ipu_base);
1474 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1476 goto failed_add_clients;
1479 dev_info(&pdev->dev, "%s probed\n", devtype->name);
1484 ipu_submodules_exit(ipu);
1485 failed_submodules_init:
1489 clk_disable_unprepare(ipu->clk);
1493 static int ipu_remove(struct platform_device *pdev)
1495 struct ipu_soc *ipu = platform_get_drvdata(pdev);
1497 platform_device_unregister_children(pdev);
1498 ipu_submodules_exit(ipu);
1501 clk_disable_unprepare(ipu->clk);
1506 static struct platform_driver imx_ipu_driver = {
1508 .name = "imx-ipuv3",
1509 .of_match_table = imx_ipu_dt_ids,
1512 .remove = ipu_remove,
1515 module_platform_driver(imx_ipu_driver);
1517 MODULE_ALIAS("platform:imx-ipuv3");
1518 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1519 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1520 MODULE_LICENSE("GPL");