drivers/gpu/host1x/drm/dc.c

   1 /*
   2  * Copyright (C) 2012 Avionic Design GmbH
   3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/clk/tegra.h>
  16
  17 #include "drm.h"
  18 #include "dc.h"
  19 #include "host1x_client.h"
  20
  21 struct tegra_plane {
  22         struct drm_plane base;
  23         unsigned int index;
  24 };
  25
  26 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
  27 {
  28         return container_of(plane, struct tegra_plane, base);
  29 }
  30
  31 static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
  32                               struct drm_framebuffer *fb, int crtc_x,
  33                               int crtc_y, unsigned int crtc_w,
  34                               unsigned int crtc_h, uint32_t src_x,
  35                               uint32_t src_y, uint32_t src_w, uint32_t src_h)
  36 {
  37         struct tegra_plane *p = to_tegra_plane(plane);
  38         struct tegra_dc *dc = to_tegra_dc(crtc);
  39         struct tegra_dc_window window;
  40         unsigned int i;
  41
  42         memset(&window, 0, sizeof(window));
  43         window.src.x = src_x >> 16;
  44         window.src.y = src_y >> 16;
  45         window.src.w = src_w >> 16;
  46         window.src.h = src_h >> 16;
  47         window.dst.x = crtc_x;
  48         window.dst.y = crtc_y;
  49         window.dst.w = crtc_w;
  50         window.dst.h = crtc_h;
  51         window.format = tegra_dc_format(fb->pixel_format);
  52         window.bits_per_pixel = fb->bits_per_pixel;
  53
  54         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
  55                 struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(fb, i);
  56
  57                 window.base[i] = gem->paddr + fb->offsets[i];
  58
  59                 /*
  60                  * Tegra doesn't support different strides for U and V planes
  61                  * so we display a warning if the user tries to display a
  62                  * framebuffer with such a configuration.
  63                  */
  64                 if (i >= 2) {
  65                         if (fb->pitches[i] != window.stride[1])
  66                                 DRM_ERROR("unsupported UV-plane configuration\n");
  67                 } else {
  68                         window.stride[i] = fb->pitches[i];
  69                 }
  70         }
  71
  72         return tegra_dc_setup_window(dc, p->index, &window);
  73 }
  74
  75 static int tegra_plane_disable(struct drm_plane *plane)
  76 {
  77         struct tegra_dc *dc = to_tegra_dc(plane->crtc);
  78         struct tegra_plane *p = to_tegra_plane(plane);
  79         unsigned long value;
  80
  81         value = WINDOW_A_SELECT << p->index;
  82         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
  83
  84         value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
  85         value &= ~WIN_ENABLE;
  86         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
  87
  88         tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
  89         tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
  90
  91         return 0;
  92 }
  93
  94 static void tegra_plane_destroy(struct drm_plane *plane)
  95 {
  96         tegra_plane_disable(plane);
  97         drm_plane_cleanup(plane);
  98 }
  99
 100 static const struct drm_plane_funcs tegra_plane_funcs = {
 101         .update_plane = tegra_plane_update,
 102         .disable_plane = tegra_plane_disable,
 103         .destroy = tegra_plane_destroy,
 104 };
 105
 106 static const uint32_t plane_formats[] = {
 107         DRM_FORMAT_XRGB8888,
 108         DRM_FORMAT_UYVY,
 109         DRM_FORMAT_YUV420,
 110         DRM_FORMAT_YUV422,
 111 };
 112
 113 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
 114 {
 115         unsigned int i;
 116         int err = 0;
 117
 118         for (i = 0; i < 2; i++) {
 119                 struct tegra_plane *plane;
 120
 121                 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
 122                 if (!plane)
 123                         return -ENOMEM;
 124
 125                 plane->index = 1 + i;
 126
 127                 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
 128                                      &tegra_plane_funcs, plane_formats,
 129                                      ARRAY_SIZE(plane_formats), false);
 130                 if (err < 0)
 131                         return err;
 132         }
 133
 134         return 0;
 135 }
 136
 137 static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
 138                              struct drm_framebuffer *fb)
 139 {
 140         struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(fb, 0);
 141         unsigned long value;
 142
 143         tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
 144
 145         value = fb->offsets[0] + y * fb->pitches[0] +
 146                 x * fb->bits_per_pixel / 8;
 147
 148         tegra_dc_writel(dc, gem->paddr + value, DC_WINBUF_START_ADDR);
 149         tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
 150
 151         value = GENERAL_UPDATE | WIN_A_UPDATE;
 152         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
 153
 154         value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
 155         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
 156
 157         return 0;
 158 }
 159
 160 void tegra_dc_enable_vblank(struct tegra_dc *dc)
 161 {
 162         unsigned long value, flags;
 163
 164         spin_lock_irqsave(&dc->lock, flags);
 165
 166         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 167         value |= VBLANK_INT;
 168         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 169
 170         spin_unlock_irqrestore(&dc->lock, flags);
 171 }
 172
 173 void tegra_dc_disable_vblank(struct tegra_dc *dc)
 174 {
 175         unsigned long value, flags;
 176
 177         spin_lock_irqsave(&dc->lock, flags);
 178
 179         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 180         value &= ~VBLANK_INT;
 181         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 182
 183         spin_unlock_irqrestore(&dc->lock, flags);
 184 }
 185
 186 static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
 187 {
 188         struct drm_device *drm = dc->base.dev;
 189         struct drm_crtc *crtc = &dc->base;
 190         struct drm_gem_cma_object *gem;
 191         unsigned long flags, base;
 192
 193         if (!dc->event)
 194                 return;
 195
 196         gem = drm_fb_cma_get_gem_obj(crtc->fb, 0);
 197
 198         /* check if new start address has been latched */
 199         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
 200         base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
 201         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
 202
 203         if (base == gem->paddr + crtc->fb->offsets[0]) {
 204                 spin_lock_irqsave(&drm->event_lock, flags);
 205                 drm_send_vblank_event(drm, dc->pipe, dc->event);
 206                 drm_vblank_put(drm, dc->pipe);
 207                 dc->event = NULL;
 208                 spin_unlock_irqrestore(&drm->event_lock, flags);
 209         }
 210 }
 211
 212 void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
 213 {
 214         struct tegra_dc *dc = to_tegra_dc(crtc);
 215         struct drm_device *drm = crtc->dev;
 216         unsigned long flags;
 217
 218         spin_lock_irqsave(&drm->event_lock, flags);
 219
 220         if (dc->event && dc->event->base.file_priv == file) {
 221                 dc->event->base.destroy(&dc->event->base);
 222                 drm_vblank_put(drm, dc->pipe);
 223                 dc->event = NULL;
 224         }
 225
 226         spin_unlock_irqrestore(&drm->event_lock, flags);
 227 }
 228
 229 static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 230                               struct drm_pending_vblank_event *event)
 231 {
 232         struct tegra_dc *dc = to_tegra_dc(crtc);
 233         struct drm_device *drm = crtc->dev;
 234
 235         if (dc->event)
 236                 return -EBUSY;
 237
 238         if (event) {
 239                 event->pipe = dc->pipe;
 240                 dc->event = event;
 241                 drm_vblank_get(drm, dc->pipe);
 242         }
 243
 244         tegra_dc_set_base(dc, 0, 0, fb);
 245         crtc->fb = fb;
 246
 247         return 0;
 248 }
 249
 250 static const struct drm_crtc_funcs tegra_crtc_funcs = {
 251         .page_flip = tegra_dc_page_flip,
 252         .set_config = drm_crtc_helper_set_config,
 253         .destroy = drm_crtc_cleanup,
 254 };
 255
 256 static void tegra_crtc_disable(struct drm_crtc *crtc)
 257 {
 258         struct drm_device *drm = crtc->dev;
 259         struct drm_plane *plane;
 260
 261         list_for_each_entry(plane, &drm->mode_config.plane_list, head) {
 262                 if (plane->crtc == crtc) {
 263                         tegra_plane_disable(plane);
 264                         plane->crtc = NULL;
 265
 266                         if (plane->fb) {
 267                                 drm_framebuffer_unreference(plane->fb);
 268                                 plane->fb = NULL;
 269                         }
 270                 }
 271         }
 272 }
 273
 274 static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
 275                                   const struct drm_display_mode *mode,
 276                                   struct drm_display_mode *adjusted)
 277 {
 278         return true;
 279 }
 280
 281 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 282                                   unsigned int bpp)
 283 {
 284         fixed20_12 outf = dfixed_init(out);
 285         fixed20_12 inf = dfixed_init(in);
 286         u32 dda_inc;
 287         int max;
 288
 289         if (v)
 290                 max = 15;
 291         else {
 292                 switch (bpp) {
 293                 case 2:
 294                         max = 8;
 295                         break;
 296
 297                 default:
 298                         WARN_ON_ONCE(1);
 299                         /* fallthrough */
 300                 case 4:
 301                         max = 4;
 302                         break;
 303                 }
 304         }
 305
 306         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 307         inf.full -= dfixed_const(1);
 308
 309         dda_inc = dfixed_div(inf, outf);
 310         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 311
 312         return dda_inc;
 313 }
 314
 315 static inline u32 compute_initial_dda(unsigned int in)
 316 {
 317         fixed20_12 inf = dfixed_init(in);
 318         return dfixed_frac(inf);
 319 }
 320
 321 static int tegra_dc_set_timings(struct tegra_dc *dc,
 322                                 struct drm_display_mode *mode)
 323 {
 324         /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
 325         unsigned int h_ref_to_sync = 0;
 326         unsigned int v_ref_to_sync = 0;
 327         unsigned long value;
 328
 329         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
 330
 331         value = (v_ref_to_sync << 16) | h_ref_to_sync;
 332         tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
 333
 334         value = ((mode->vsync_end - mode->vsync_start) << 16) |
 335                 ((mode->hsync_end - mode->hsync_start) <<  0);
 336         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
 337
 338         value = ((mode->vtotal - mode->vsync_end) << 16) |
 339                 ((mode->htotal - mode->hsync_end) <<  0);
 340         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
 341
 342         value = ((mode->vsync_start - mode->vdisplay) << 16) |
 343                 ((mode->hsync_start - mode->hdisplay) <<  0);
 344         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
 345
 346         value = (mode->vdisplay << 16) | mode->hdisplay;
 347         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
 348
 349         return 0;
 350 }
 351
 352 static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
 353                                 struct drm_display_mode *mode,
 354                                 unsigned long *div)
 355 {
 356         unsigned long pclk = mode->clock * 1000, rate;
 357         struct tegra_dc *dc = to_tegra_dc(crtc);
 358         struct tegra_output *output = NULL;
 359         struct drm_encoder *encoder;
 360         long err;
 361
 362         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
 363                 if (encoder->crtc == crtc) {
 364                         output = encoder_to_output(encoder);
 365                         break;
 366                 }
 367
 368         if (!output)
 369                 return -ENODEV;
 370
 371         /*
 372          * This assumes that the display controller will divide its parent
 373          * clock by 2 to generate the pixel clock.
 374          */
 375         err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
 376         if (err < 0) {
 377                 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
 378                 return err;
 379         }
 380
 381         rate = clk_get_rate(dc->clk);
 382         *div = (rate * 2 / pclk) - 2;
 383
 384         DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
 385
 386         return 0;
 387 }
 388
 389 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
 390 {
 391         switch (format) {
 392         case WIN_COLOR_DEPTH_YCbCr422:
 393         case WIN_COLOR_DEPTH_YUV422:
 394                 if (planar)
 395                         *planar = false;
 396
 397                 return true;
 398
 399         case WIN_COLOR_DEPTH_YCbCr420P:
 400         case WIN_COLOR_DEPTH_YUV420P:
 401         case WIN_COLOR_DEPTH_YCbCr422P:
 402         case WIN_COLOR_DEPTH_YUV422P:
 403         case WIN_COLOR_DEPTH_YCbCr422R:
 404         case WIN_COLOR_DEPTH_YUV422R:
 405         case WIN_COLOR_DEPTH_YCbCr422RA:
 406         case WIN_COLOR_DEPTH_YUV422RA:
 407                 if (planar)
 408                         *planar = true;
 409
 410                 return true;
 411         }
 412
 413         return false;
 414 }
 415
 416 int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
 417                           const struct tegra_dc_window *window)
 418 {
 419         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 420         unsigned long value;
 421         bool yuv, planar;
 422
 423         /*
 424          * For YUV planar modes, the number of bytes per pixel takes into
 425          * account only the luma component and therefore is 1.
 426          */
 427         yuv = tegra_dc_format_is_yuv(window->format, &planar);
 428         if (!yuv)
 429                 bpp = window->bits_per_pixel / 8;
 430         else
 431                 bpp = planar ? 1 : 2;
 432
 433         value = WINDOW_A_SELECT << index;
 434         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 435
 436         tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
 437         tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
 438
 439         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 440         tegra_dc_writel(dc, value, DC_WIN_POSITION);
 441
 442         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 443         tegra_dc_writel(dc, value, DC_WIN_SIZE);
 444
 445         h_offset = window->src.x * bpp;
 446         v_offset = window->src.y;
 447         h_size = window->src.w * bpp;
 448         v_size = window->src.h;
 449
 450         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 451         tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
 452
 453         /*
 454          * For DDA computations the number of bytes per pixel for YUV planar
 455          * modes needs to take into account all Y, U and V components.
 456          */
 457         if (yuv && planar)
 458                 bpp = 2;
 459
 460         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 461         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 462
 463         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 464         tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
 465
 466         h_dda = compute_initial_dda(window->src.x);
 467         v_dda = compute_initial_dda(window->src.y);
 468
 469         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
 470         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
 471
 472         tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
 473         tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
 474
 475         tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
 476
 477         if (yuv && planar) {
 478                 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
 479                 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
 480                 value = window->stride[1] << 16 | window->stride[0];
 481                 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
 482         } else {
 483                 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
 484         }
 485
 486         tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 487         tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 488
 489         value = WIN_ENABLE;
 490
 491         if (yuv) {
 492                 /* setup default colorspace conversion coefficients */
 493                 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
 494                 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
 495                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
 496                 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
 497                 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
 498                 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
 499                 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
 500                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
 501
 502                 value |= CSC_ENABLE;
 503         } else if (window->bits_per_pixel < 24) {
 504                 value |= COLOR_EXPAND;
 505         }
 506
 507         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 508
 509         /*
 510          * Disable blending and assume Window A is the bottom-most window,
 511          * Window C is the top-most window and Window B is in the middle.
 512          */
 513         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
 514         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
 515
 516         switch (index) {
 517         case 0:
 518                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
 519                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 520                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 521                 break;
 522
 523         case 1:
 524                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 525                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 526                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 527                 break;
 528
 529         case 2:
 530                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 531                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
 532                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
 533                 break;
 534         }
 535
 536         tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
 537         tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
 538
 539         return 0;
 540 }
 541
 542 unsigned int tegra_dc_format(uint32_t format)
 543 {
 544         switch (format) {
 545         case DRM_FORMAT_XRGB8888:
 546                 return WIN_COLOR_DEPTH_B8G8R8A8;
 547
 548         case DRM_FORMAT_RGB565:
 549                 return WIN_COLOR_DEPTH_B5G6R5;
 550
 551         case DRM_FORMAT_UYVY:
 552                 return WIN_COLOR_DEPTH_YCbCr422;
 553
 554         case DRM_FORMAT_YUV420:
 555                 return WIN_COLOR_DEPTH_YCbCr420P;
 556
 557         case DRM_FORMAT_YUV422:
 558                 return WIN_COLOR_DEPTH_YCbCr422P;
 559
 560         default:
 561                 break;
 562         }
 563
 564         WARN(1, "unsupported pixel format %u, using default\n", format);
 565         return WIN_COLOR_DEPTH_B8G8R8A8;
 566 }
 567
 568 static int tegra_crtc_mode_set(struct drm_crtc *crtc,
 569                                struct drm_display_mode *mode,
 570                                struct drm_display_mode *adjusted,
 571                                int x, int y, struct drm_framebuffer *old_fb)
 572 {
 573         struct drm_gem_cma_object *gem = drm_fb_cma_get_gem_obj(crtc->fb, 0);
 574         struct tegra_dc *dc = to_tegra_dc(crtc);
 575         struct tegra_dc_window window;
 576         unsigned long div, value;
 577         int err;
 578
 579         drm_vblank_pre_modeset(crtc->dev, dc->pipe);
 580
 581         err = tegra_crtc_setup_clk(crtc, mode, &div);
 582         if (err) {
 583                 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
 584                 return err;
 585         }
 586
 587         /* program display mode */
 588         tegra_dc_set_timings(dc, mode);
 589
 590         value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
 591         tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
 592
 593         value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1));
 594         value &= ~LVS_OUTPUT_POLARITY_LOW;
 595         value &= ~LHS_OUTPUT_POLARITY_LOW;
 596         tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
 597
 598         value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
 599                 DISP_ORDER_RED_BLUE;
 600         tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
 601
 602         tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS);
 603
 604         value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
 605         tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
 606
 607         /* setup window parameters */
 608         memset(&window, 0, sizeof(window));
 609         window.src.x = 0;
 610         window.src.y = 0;
 611         window.src.w = mode->hdisplay;
 612         window.src.h = mode->vdisplay;
 613         window.dst.x = 0;
 614         window.dst.y = 0;
 615         window.dst.w = mode->hdisplay;
 616         window.dst.h = mode->vdisplay;
 617         window.format = tegra_dc_format(crtc->fb->pixel_format);
 618         window.bits_per_pixel = crtc->fb->bits_per_pixel;
 619         window.stride[0] = crtc->fb->pitches[0];
 620         window.base[0] = gem->paddr;
 621
 622         err = tegra_dc_setup_window(dc, 0, &window);
 623         if (err < 0)
 624                 dev_err(dc->dev, "failed to enable root plane\n");
 625
 626         return 0;
 627 }
 628
 629 static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 630                                     struct drm_framebuffer *old_fb)
 631 {
 632         struct tegra_dc *dc = to_tegra_dc(crtc);
 633
 634         return tegra_dc_set_base(dc, x, y, crtc->fb);
 635 }
 636
 637 static void tegra_crtc_prepare(struct drm_crtc *crtc)
 638 {
 639         struct tegra_dc *dc = to_tegra_dc(crtc);
 640         unsigned int syncpt;
 641         unsigned long value;
 642
 643         /* hardware initialization */
 644         tegra_periph_reset_deassert(dc->clk);
 645         usleep_range(10000, 20000);
 646
 647         if (dc->pipe)
 648                 syncpt = SYNCPT_VBLANK1;
 649         else
 650                 syncpt = SYNCPT_VBLANK0;
 651
 652         /* initialize display controller */
 653         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
 654         tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
 655
 656         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
 657         tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
 658
 659         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
 660                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
 661         tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
 662
 663         value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
 664                 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
 665         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
 666
 667         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
 668         value |= DISP_CTRL_MODE_C_DISPLAY;
 669         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
 670
 671         /* initialize timer */
 672         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
 673                 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
 674         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
 675
 676         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
 677                 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
 678         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
 679
 680         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
 681         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
 682
 683         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
 684         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 685 }
 686
 687 static void tegra_crtc_commit(struct drm_crtc *crtc)
 688 {
 689         struct tegra_dc *dc = to_tegra_dc(crtc);
 690         unsigned long value;
 691
 692         value = GENERAL_UPDATE | WIN_A_UPDATE;
 693         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
 694
 695         value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
 696         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
 697
 698         drm_vblank_post_modeset(crtc->dev, dc->pipe);
 699 }
 700
 701 static void tegra_crtc_load_lut(struct drm_crtc *crtc)
 702 {
 703 }
 704
 705 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
 706         .disable = tegra_crtc_disable,
 707         .mode_fixup = tegra_crtc_mode_fixup,
 708         .mode_set = tegra_crtc_mode_set,
 709         .mode_set_base = tegra_crtc_mode_set_base,
 710         .prepare = tegra_crtc_prepare,
 711         .commit = tegra_crtc_commit,
 712         .load_lut = tegra_crtc_load_lut,
 713 };
 714
 715 static irqreturn_t tegra_dc_irq(int irq, void *data)
 716 {
 717         struct tegra_dc *dc = data;
 718         unsigned long status;
 719
 720         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
 721         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
 722
 723         if (status & FRAME_END_INT) {
 724                 /*
 725                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
 726                 */
 727         }
 728
 729         if (status & VBLANK_INT) {
 730                 /*
 731                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
 732                 */
 733                 drm_handle_vblank(dc->base.dev, dc->pipe);
 734                 tegra_dc_finish_page_flip(dc);
 735         }
 736
 737         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
 738                 /*
 739                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
 740                 */
 741         }
 742
 743         return IRQ_HANDLED;
 744 }
 745
 746 static int tegra_dc_show_regs(struct seq_file *s, void *data)
 747 {
 748         struct drm_info_node *node = s->private;
 749         struct tegra_dc *dc = node->info_ent->data;
 750
 751 #define DUMP_REG(name)                                          \
 752         seq_printf(s, "%-40s %#05x %08lx\n", #name, name,       \
 753                    tegra_dc_readl(dc, name))
 754
 755         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
 756         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
 757         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
 758         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
 759         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
 760         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
 761         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
 762         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
 763         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
 764         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
 765         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
 766         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
 767         DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
 768         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
 769         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
 770         DUMP_REG(DC_CMD_SIGNAL_RAISE);
 771         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
 772         DUMP_REG(DC_CMD_INT_STATUS);
 773         DUMP_REG(DC_CMD_INT_MASK);
 774         DUMP_REG(DC_CMD_INT_ENABLE);
 775         DUMP_REG(DC_CMD_INT_TYPE);
 776         DUMP_REG(DC_CMD_INT_POLARITY);
 777         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
 778         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
 779         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
 780         DUMP_REG(DC_CMD_STATE_ACCESS);
 781         DUMP_REG(DC_CMD_STATE_CONTROL);
 782         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 783         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
 784         DUMP_REG(DC_COM_CRC_CONTROL);
 785         DUMP_REG(DC_COM_CRC_CHECKSUM);
 786         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
 787         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
 788         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
 789         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
 790         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
 791         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
 792         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
 793         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
 794         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
 795         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
 796         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
 797         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
 798         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
 799         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
 800         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
 801         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
 802         DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
 803         DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
 804         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
 805         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
 806         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
 807         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
 808         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
 809         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
 810         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
 811         DUMP_REG(DC_COM_PIN_MISC_CONTROL);
 812         DUMP_REG(DC_COM_PIN_PM0_CONTROL);
 813         DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
 814         DUMP_REG(DC_COM_PIN_PM1_CONTROL);
 815         DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
 816         DUMP_REG(DC_COM_SPI_CONTROL);
 817         DUMP_REG(DC_COM_SPI_START_BYTE);
 818         DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
 819         DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
 820         DUMP_REG(DC_COM_HSPI_CS_DC);
 821         DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
 822         DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
 823         DUMP_REG(DC_COM_GPIO_CTRL);
 824         DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
 825         DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
 826         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
 827         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
 828         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
 829         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
 830         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
 831         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
 832         DUMP_REG(DC_DISP_REF_TO_SYNC);
 833         DUMP_REG(DC_DISP_SYNC_WIDTH);
 834         DUMP_REG(DC_DISP_BACK_PORCH);
 835         DUMP_REG(DC_DISP_ACTIVE);
 836         DUMP_REG(DC_DISP_FRONT_PORCH);
 837         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
 838         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
 839         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
 840         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
 841         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
 842         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
 843         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
 844         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
 845         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
 846         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
 847         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
 848         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
 849         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
 850         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
 851         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
 852         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
 853         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
 854         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
 855         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
 856         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
 857         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
 858         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
 859         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
 860         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
 861         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
 862         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
 863         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
 864         DUMP_REG(DC_DISP_M0_CONTROL);
 865         DUMP_REG(DC_DISP_M1_CONTROL);
 866         DUMP_REG(DC_DISP_DI_CONTROL);
 867         DUMP_REG(DC_DISP_PP_CONTROL);
 868         DUMP_REG(DC_DISP_PP_SELECT_A);
 869         DUMP_REG(DC_DISP_PP_SELECT_B);
 870         DUMP_REG(DC_DISP_PP_SELECT_C);
 871         DUMP_REG(DC_DISP_PP_SELECT_D);
 872         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
 873         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
 874         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
 875         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
 876         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
 877         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
 878         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
 879         DUMP_REG(DC_DISP_BORDER_COLOR);
 880         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
 881         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
 882         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
 883         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
 884         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
 885         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
 886         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
 887         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
 888         DUMP_REG(DC_DISP_CURSOR_POSITION);
 889         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
 890         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
 891         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
 892         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
 893         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
 894         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
 895         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
 896         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
 897         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
 898         DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
 899         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
 900         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
 901         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
 902         DUMP_REG(DC_DISP_SD_CONTROL);
 903         DUMP_REG(DC_DISP_SD_CSC_COEFF);
 904         DUMP_REG(DC_DISP_SD_LUT(0));
 905         DUMP_REG(DC_DISP_SD_LUT(1));
 906         DUMP_REG(DC_DISP_SD_LUT(2));
 907         DUMP_REG(DC_DISP_SD_LUT(3));
 908         DUMP_REG(DC_DISP_SD_LUT(4));
 909         DUMP_REG(DC_DISP_SD_LUT(5));
 910         DUMP_REG(DC_DISP_SD_LUT(6));
 911         DUMP_REG(DC_DISP_SD_LUT(7));
 912         DUMP_REG(DC_DISP_SD_LUT(8));
 913         DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
 914         DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
 915         DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
 916         DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
 917         DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
 918         DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
 919         DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
 920         DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
 921         DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
 922         DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
 923         DUMP_REG(DC_DISP_SD_BL_TF(0));
 924         DUMP_REG(DC_DISP_SD_BL_TF(1));
 925         DUMP_REG(DC_DISP_SD_BL_TF(2));
 926         DUMP_REG(DC_DISP_SD_BL_TF(3));
 927         DUMP_REG(DC_DISP_SD_BL_CONTROL);
 928         DUMP_REG(DC_DISP_SD_HW_K_VALUES);
 929         DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
 930         DUMP_REG(DC_WIN_WIN_OPTIONS);
 931         DUMP_REG(DC_WIN_BYTE_SWAP);
 932         DUMP_REG(DC_WIN_BUFFER_CONTROL);
 933         DUMP_REG(DC_WIN_COLOR_DEPTH);
 934         DUMP_REG(DC_WIN_POSITION);
 935         DUMP_REG(DC_WIN_SIZE);
 936         DUMP_REG(DC_WIN_PRESCALED_SIZE);
 937         DUMP_REG(DC_WIN_H_INITIAL_DDA);
 938         DUMP_REG(DC_WIN_V_INITIAL_DDA);
 939         DUMP_REG(DC_WIN_DDA_INC);
 940         DUMP_REG(DC_WIN_LINE_STRIDE);
 941         DUMP_REG(DC_WIN_BUF_STRIDE);
 942         DUMP_REG(DC_WIN_UV_BUF_STRIDE);
 943         DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
 944         DUMP_REG(DC_WIN_DV_CONTROL);
 945         DUMP_REG(DC_WIN_BLEND_NOKEY);
 946         DUMP_REG(DC_WIN_BLEND_1WIN);
 947         DUMP_REG(DC_WIN_BLEND_2WIN_X);
 948         DUMP_REG(DC_WIN_BLEND_2WIN_Y);
 949         DUMP_REG(DC_WIN_BLEND_3WIN_XY);
 950         DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
 951         DUMP_REG(DC_WINBUF_START_ADDR);
 952         DUMP_REG(DC_WINBUF_START_ADDR_NS);
 953         DUMP_REG(DC_WINBUF_START_ADDR_U);
 954         DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
 955         DUMP_REG(DC_WINBUF_START_ADDR_V);
 956         DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
 957         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
 958         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
 959         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
 960         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
 961         DUMP_REG(DC_WINBUF_UFLOW_STATUS);
 962         DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
 963         DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
 964         DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
 965
 966 #undef DUMP_REG
 967
 968         return 0;
 969 }
 970
 971 static struct drm_info_list debugfs_files[] = {
 972         { "regs", tegra_dc_show_regs, 0, NULL },
 973 };
 974
 975 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
 976 {
 977         unsigned int i;
 978         char *name;
 979         int err;
 980
 981         name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
 982         dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
 983         kfree(name);
 984
 985         if (!dc->debugfs)
 986                 return -ENOMEM;
 987
 988         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
 989                                     GFP_KERNEL);
 990         if (!dc->debugfs_files) {
 991                 err = -ENOMEM;
 992                 goto remove;
 993         }
 994
 995         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
 996                 dc->debugfs_files[i].data = dc;
 997
 998         err = drm_debugfs_create_files(dc->debugfs_files,
 999                                        ARRAY_SIZE(debugfs_files),
1000                                        dc->debugfs, minor);
1001         if (err < 0)
1002                 goto free;
1003
1004         dc->minor = minor;
1005
1006         return 0;
1007
1008 free:
1009         kfree(dc->debugfs_files);
1010         dc->debugfs_files = NULL;
1011 remove:
1012         debugfs_remove(dc->debugfs);
1013         dc->debugfs = NULL;
1014
1015         return err;
1016 }
1017
1018 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1019 {
1020         drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1021                                  dc->minor);
1022         dc->minor = NULL;
1023
1024         kfree(dc->debugfs_files);
1025         dc->debugfs_files = NULL;
1026
1027         debugfs_remove(dc->debugfs);
1028         dc->debugfs = NULL;
1029
1030         return 0;
1031 }
1032
1033 static int tegra_dc_drm_init(struct host1x_client *client,
1034                              struct drm_device *drm)
1035 {
1036         struct tegra_dc *dc = host1x_client_to_dc(client);
1037         int err;
1038
1039         dc->pipe = drm->mode_config.num_crtc;
1040
1041         drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
1042         drm_mode_crtc_set_gamma_size(&dc->base, 256);
1043         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1044
1045         err = tegra_dc_rgb_init(drm, dc);
1046         if (err < 0 && err != -ENODEV) {
1047                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1048                 return err;
1049         }
1050
1051         err = tegra_dc_add_planes(drm, dc);
1052         if (err < 0)
1053                 return err;
1054
1055         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1056                 err = tegra_dc_debugfs_init(dc, drm->primary);
1057                 if (err < 0)
1058                         dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1059         }
1060
1061         err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1062                                dev_name(dc->dev), dc);
1063         if (err < 0) {
1064                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1065                         err);
1066                 return err;
1067         }
1068
1069         return 0;
1070 }
1071
1072 static int tegra_dc_drm_exit(struct host1x_client *client)
1073 {
1074         struct tegra_dc *dc = host1x_client_to_dc(client);
1075         int err;
1076
1077         devm_free_irq(dc->dev, dc->irq, dc);
1078
1079         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1080                 err = tegra_dc_debugfs_exit(dc);
1081                 if (err < 0)
1082                         dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1083         }
1084
1085         err = tegra_dc_rgb_exit(dc);
1086         if (err) {
1087                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1088                 return err;
1089         }
1090
1091         return 0;
1092 }
1093
1094 static const struct host1x_client_ops dc_client_ops = {
1095         .drm_init = tegra_dc_drm_init,
1096         .drm_exit = tegra_dc_drm_exit,
1097 };
1098
1099 static int tegra_dc_probe(struct platform_device *pdev)
1100 {
1101         struct host1x_drm *host1x = host1x_get_drm_data(pdev->dev.parent);
1102         struct resource *regs;
1103         struct tegra_dc *dc;
1104         int err;
1105
1106         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1107         if (!dc)
1108                 return -ENOMEM;
1109
1110         spin_lock_init(&dc->lock);
1111         INIT_LIST_HEAD(&dc->list);
1112         dc->dev = &pdev->dev;
1113
1114         dc->clk = devm_clk_get(&pdev->dev, NULL);
1115         if (IS_ERR(dc->clk)) {
1116                 dev_err(&pdev->dev, "failed to get clock\n");
1117                 return PTR_ERR(dc->clk);
1118         }
1119
1120         err = clk_prepare_enable(dc->clk);
1121         if (err < 0)
1122                 return err;
1123
1124         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1125         if (!regs) {
1126                 dev_err(&pdev->dev, "failed to get registers\n");
1127                 return -ENXIO;
1128         }
1129
1130         dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1131         if (IS_ERR(dc->regs))
1132                 return PTR_ERR(dc->regs);
1133
1134         dc->irq = platform_get_irq(pdev, 0);
1135         if (dc->irq < 0) {
1136                 dev_err(&pdev->dev, "failed to get IRQ\n");
1137                 return -ENXIO;
1138         }
1139
1140         INIT_LIST_HEAD(&dc->client.list);
1141         dc->client.ops = &dc_client_ops;
1142         dc->client.dev = &pdev->dev;
1143
1144         err = tegra_dc_rgb_probe(dc);
1145         if (err < 0 && err != -ENODEV) {
1146                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1147                 return err;
1148         }
1149
1150         err = host1x_register_client(host1x, &dc->client);
1151         if (err < 0) {
1152                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1153                         err);
1154                 return err;
1155         }
1156
1157         platform_set_drvdata(pdev, dc);
1158
1159         return 0;
1160 }
1161
1162 static int tegra_dc_remove(struct platform_device *pdev)
1163 {
1164         struct host1x_drm *host1x = host1x_get_drm_data(pdev->dev.parent);
1165         struct tegra_dc *dc = platform_get_drvdata(pdev);
1166         int err;
1167
1168         err = host1x_unregister_client(host1x, &dc->client);
1169         if (err < 0) {
1170                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1171                         err);
1172                 return err;
1173         }
1174
1175         clk_disable_unprepare(dc->clk);
1176
1177         return 0;
1178 }
1179
1180 static struct of_device_id tegra_dc_of_match[] = {
1181         { .compatible = "nvidia,tegra30-dc", },
1182         { .compatible = "nvidia,tegra20-dc", },
1183         { },
1184 };
1185
1186 struct platform_driver tegra_dc_driver = {
1187         .driver = {
1188                 .name = "tegra-dc",
1189                 .owner = THIS_MODULE,
1190                 .of_match_table = tegra_dc_of_match,
1191         },
1192         .probe = tegra_dc_probe,
1193         .remove = tegra_dc_remove,
1194 };