drivers/gpu/host1x/dev.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Tegra host1x driver
   4  *
   5  * Copyright (c) 2010-2013, NVIDIA Corporation.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/io.h>
  12 #include <linux/list.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/slab.h>
  18
  19 #include <soc/tegra/common.h>
  20
  21 #define CREATE_TRACE_POINTS
  22 #include <trace/events/host1x.h>
  23 #undef CREATE_TRACE_POINTS
  24
  25 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
  26 #include <asm/dma-iommu.h>
  27 #endif
  28
  29 #include "bus.h"
  30 #include "channel.h"
  31 #include "context.h"
  32 #include "debug.h"
  33 #include "dev.h"
  34 #include "intr.h"
  35
  36 #include "hw/host1x01.h"
  37 #include "hw/host1x02.h"
  38 #include "hw/host1x04.h"
  39 #include "hw/host1x05.h"
  40 #include "hw/host1x06.h"
  41 #include "hw/host1x07.h"
  42 #include "hw/host1x08.h"
  43
  44 void host1x_common_writel(struct host1x *host1x, u32 v, u32 r)
  45 {
  46         writel(v, host1x->common_regs + r);
  47 }
  48
  49 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)
  50 {
  51         writel(v, host1x->hv_regs + r);
  52 }
  53
  54 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)
  55 {
  56         return readl(host1x->hv_regs + r);
  57 }
  58
  59 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
  60 {
  61         void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  62
  63         writel(v, sync_regs + r);
  64 }
  65
  66 u32 host1x_sync_readl(struct host1x *host1x, u32 r)
  67 {
  68         void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;
  69
  70         return readl(sync_regs + r);
  71 }
  72
  73 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r)
  74 {
  75         writel(v, ch->regs + r);
  76 }
  77
  78 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r)
  79 {
  80         return readl(ch->regs + r);
  81 }
  82
  83 static const struct host1x_info host1x01_info = {
  84         .nb_channels = 8,
  85         .nb_pts = 32,
  86         .nb_mlocks = 16,
  87         .nb_bases = 8,
  88         .init = host1x01_init,
  89         .sync_offset = 0x3000,
  90         .dma_mask = DMA_BIT_MASK(32),
  91         .has_wide_gather = false,
  92         .has_hypervisor = false,
  93         .num_sid_entries = 0,
  94         .sid_table = NULL,
  95         .reserve_vblank_syncpts = true,
  96 };
  97
  98 static const struct host1x_info host1x02_info = {
  99         .nb_channels = 9,
 100         .nb_pts = 32,
 101         .nb_mlocks = 16,
 102         .nb_bases = 12,
 103         .init = host1x02_init,
 104         .sync_offset = 0x3000,
 105         .dma_mask = DMA_BIT_MASK(32),
 106         .has_wide_gather = false,
 107         .has_hypervisor = false,
 108         .num_sid_entries = 0,
 109         .sid_table = NULL,
 110         .reserve_vblank_syncpts = true,
 111 };
 112
 113 static const struct host1x_info host1x04_info = {
 114         .nb_channels = 12,
 115         .nb_pts = 192,
 116         .nb_mlocks = 16,
 117         .nb_bases = 64,
 118         .init = host1x04_init,
 119         .sync_offset = 0x2100,
 120         .dma_mask = DMA_BIT_MASK(34),
 121         .has_wide_gather = false,
 122         .has_hypervisor = false,
 123         .num_sid_entries = 0,
 124         .sid_table = NULL,
 125         .reserve_vblank_syncpts = false,
 126 };
 127
 128 static const struct host1x_info host1x05_info = {
 129         .nb_channels = 14,
 130         .nb_pts = 192,
 131         .nb_mlocks = 16,
 132         .nb_bases = 64,
 133         .init = host1x05_init,
 134         .sync_offset = 0x2100,
 135         .dma_mask = DMA_BIT_MASK(34),
 136         .has_wide_gather = false,
 137         .has_hypervisor = false,
 138         .num_sid_entries = 0,
 139         .sid_table = NULL,
 140         .reserve_vblank_syncpts = false,
 141 };
 142
 143 static const struct host1x_sid_entry tegra186_sid_table[] = {
 144         {
 145                 /* VIC */
 146                 .base = 0x1af0,
 147                 .offset = 0x30,
 148                 .limit = 0x34
 149         },
 150         {
 151                 /* NVDEC */
 152                 .base = 0x1b00,
 153                 .offset = 0x30,
 154                 .limit = 0x34
 155         },
 156 };
 157
 158 static const struct host1x_info host1x06_info = {
 159         .nb_channels = 63,
 160         .nb_pts = 576,
 161         .nb_mlocks = 24,
 162         .nb_bases = 16,
 163         .init = host1x06_init,
 164         .sync_offset = 0x0,
 165         .dma_mask = DMA_BIT_MASK(40),
 166         .has_wide_gather = true,
 167         .has_hypervisor = true,
 168         .num_sid_entries = ARRAY_SIZE(tegra186_sid_table),
 169         .sid_table = tegra186_sid_table,
 170         .reserve_vblank_syncpts = false,
 171 };
 172
 173 static const struct host1x_sid_entry tegra194_sid_table[] = {
 174         {
 175                 /* VIC */
 176                 .base = 0x1af0,
 177                 .offset = 0x30,
 178                 .limit = 0x34
 179         },
 180         {
 181                 /* NVDEC */
 182                 .base = 0x1b00,
 183                 .offset = 0x30,
 184                 .limit = 0x34
 185         },
 186         {
 187                 /* NVDEC1 */
 188                 .base = 0x1bc0,
 189                 .offset = 0x30,
 190                 .limit = 0x34
 191         },
 192 };
 193
 194 static const struct host1x_info host1x07_info = {
 195         .nb_channels = 63,
 196         .nb_pts = 704,
 197         .nb_mlocks = 32,
 198         .nb_bases = 0,
 199         .init = host1x07_init,
 200         .sync_offset = 0x0,
 201         .dma_mask = DMA_BIT_MASK(40),
 202         .has_wide_gather = true,
 203         .has_hypervisor = true,
 204         .num_sid_entries = ARRAY_SIZE(tegra194_sid_table),
 205         .sid_table = tegra194_sid_table,
 206         .reserve_vblank_syncpts = false,
 207 };
 208
 209 /*
 210  * Tegra234 has two stream ID protection tables, one for setting stream IDs
 211  * through the channel path via SETSTREAMID, and one for setting them via
 212  * MMIO. We program each engine's data stream ID in the channel path table
 213  * and firmware stream ID in the MMIO path table.
 214  */
 215 static const struct host1x_sid_entry tegra234_sid_table[] = {
 216         {
 217                 /* VIC channel */
 218                 .base = 0x17b8,
 219                 .offset = 0x30,
 220                 .limit = 0x30
 221         },
 222         {
 223                 /* VIC MMIO */
 224                 .base = 0x1688,
 225                 .offset = 0x34,
 226                 .limit = 0x34
 227         },
 228 };
 229
 230 static const struct host1x_info host1x08_info = {
 231         .nb_channels = 63,
 232         .nb_pts = 1024,
 233         .nb_mlocks = 24,
 234         .nb_bases = 0,
 235         .init = host1x08_init,
 236         .sync_offset = 0x0,
 237         .dma_mask = DMA_BIT_MASK(40),
 238         .has_wide_gather = true,
 239         .has_hypervisor = true,
 240         .has_common = true,
 241         .num_sid_entries = ARRAY_SIZE(tegra234_sid_table),
 242         .sid_table = tegra234_sid_table,
 243         .streamid_vm_table = { 0x1004, 128 },
 244         .classid_vm_table = { 0x1404, 25 },
 245         .mmio_vm_table = { 0x1504, 25 },
 246         .reserve_vblank_syncpts = false,
 247 };
 248
 249 static const struct of_device_id host1x_of_match[] = {
 250         { .compatible = "nvidia,tegra234-host1x", .data = &host1x08_info, },
 251         { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
 252         { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
 253         { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
 254         { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
 255         { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
 256         { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
 257         { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
 258         { },
 259 };
 260 MODULE_DEVICE_TABLE(of, host1x_of_match);
 261
 262 static void host1x_setup_virtualization_tables(struct host1x *host)
 263 {
 264         const struct host1x_info *info = host->info;
 265         unsigned int i;
 266
 267         if (!info->has_hypervisor)
 268                 return;
 269
 270         for (i = 0; i < info->num_sid_entries; i++) {
 271                 const struct host1x_sid_entry *entry = &info->sid_table[i];
 272
 273                 host1x_hypervisor_writel(host, entry->offset, entry->base);
 274                 host1x_hypervisor_writel(host, entry->limit, entry->base + 4);
 275         }
 276
 277         for (i = 0; i < info->streamid_vm_table.count; i++) {
 278                 /* Allow access to all stream IDs to all VMs. */
 279                 host1x_hypervisor_writel(host, 0xff, info->streamid_vm_table.base + 4 * i);
 280         }
 281
 282         for (i = 0; i < info->classid_vm_table.count; i++) {
 283                 /* Allow access to all classes to all VMs. */
 284                 host1x_hypervisor_writel(host, 0xff, info->classid_vm_table.base + 4 * i);
 285         }
 286
 287         for (i = 0; i < info->mmio_vm_table.count; i++) {
 288                 /* Use VM1 (that's us) as originator VMID for engine MMIO accesses. */
 289                 host1x_hypervisor_writel(host, 0x1, info->mmio_vm_table.base + 4 * i);
 290         }
 291 }
 292
 293 static bool host1x_wants_iommu(struct host1x *host1x)
 294 {
 295         /* Our IOMMU usage policy doesn't currently play well with GART */
 296         if (of_machine_is_compatible("nvidia,tegra20"))
 297                 return false;
 298
 299         /*
 300          * If we support addressing a maximum of 32 bits of physical memory
 301          * and if the host1x firewall is enabled, there's no need to enable
 302          * IOMMU support. This can happen for example on Tegra20, Tegra30
 303          * and Tegra114.
 304          *
 305          * Tegra124 and later can address up to 34 bits of physical memory and
 306          * many platforms come equipped with more than 2 GiB of system memory,
 307          * which requires crossing the 4 GiB boundary. But there's a catch: on
 308          * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can
 309          * only address up to 32 bits of memory in GATHER opcodes, which means
 310          * that command buffers need to either be in the first 2 GiB of system
 311          * memory (which could quickly lead to memory exhaustion), or command
 312          * buffers need to be treated differently from other buffers (which is
 313          * not possible with the current ABI).
 314          *
 315          * A third option is to use the IOMMU in these cases to make sure all
 316          * buffers will be mapped into a 32-bit IOVA space that host1x can
 317          * address. This allows all of the system memory to be used and works
 318          * within the limitations of the host1x on these SoCs.
 319          *
 320          * In summary, default to enable IOMMU on Tegra124 and later. For any
 321          * of the earlier SoCs, only use the IOMMU for additional safety when
 322          * the host1x firewall is disabled.
 323          */
 324         if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) {
 325                 if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL))
 326                         return false;
 327         }
 328
 329         return true;
 330 }
 331
 332 static struct iommu_domain *host1x_iommu_attach(struct host1x *host)
 333 {
 334         struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev);
 335         int err;
 336
 337 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
 338         if (host->dev->archdata.mapping) {
 339                 struct dma_iommu_mapping *mapping =
 340                                 to_dma_iommu_mapping(host->dev);
 341                 arm_iommu_detach_device(host->dev);
 342                 arm_iommu_release_mapping(mapping);
 343
 344                 domain = iommu_get_domain_for_dev(host->dev);
 345         }
 346 #endif
 347
 348         /*
 349          * We may not always want to enable IOMMU support (for example if the
 350          * host1x firewall is already enabled and we don't support addressing
 351          * more than 32 bits of physical memory), so check for that first.
 352          *
 353          * Similarly, if host1x is already attached to an IOMMU (via the DMA
 354          * API), don't try to attach again.
 355          */
 356         if (!host1x_wants_iommu(host) || domain)
 357                 return domain;
 358
 359         host->group = iommu_group_get(host->dev);
 360         if (host->group) {
 361                 struct iommu_domain_geometry *geometry;
 362                 dma_addr_t start, end;
 363                 unsigned long order;
 364
 365                 err = iova_cache_get();
 366                 if (err < 0)
 367                         goto put_group;
 368
 369                 host->domain = iommu_domain_alloc(&platform_bus_type);
 370                 if (!host->domain) {
 371                         err = -ENOMEM;
 372                         goto put_cache;
 373                 }
 374
 375                 err = iommu_attach_group(host->domain, host->group);
 376                 if (err) {
 377                         if (err == -ENODEV)
 378                                 err = 0;
 379
 380                         goto free_domain;
 381                 }
 382
 383                 geometry = &host->domain->geometry;
 384                 start = geometry->aperture_start & host->info->dma_mask;
 385                 end = geometry->aperture_end & host->info->dma_mask;
 386
 387                 order = __ffs(host->domain->pgsize_bitmap);
 388                 init_iova_domain(&host->iova, 1UL << order, start >> order);
 389                 host->iova_end = end;
 390
 391                 domain = host->domain;
 392         }
 393
 394         return domain;
 395
 396 free_domain:
 397         iommu_domain_free(host->domain);
 398         host->domain = NULL;
 399 put_cache:
 400         iova_cache_put();
 401 put_group:
 402         iommu_group_put(host->group);
 403         host->group = NULL;
 404
 405         return ERR_PTR(err);
 406 }
 407
 408 static int host1x_iommu_init(struct host1x *host)
 409 {
 410         u64 mask = host->info->dma_mask;
 411         struct iommu_domain *domain;
 412         int err;
 413
 414         domain = host1x_iommu_attach(host);
 415         if (IS_ERR(domain)) {
 416                 err = PTR_ERR(domain);
 417                 dev_err(host->dev, "failed to attach to IOMMU: %d\n", err);
 418                 return err;
 419         }
 420
 421         /*
 422          * If we're not behind an IOMMU make sure we don't get push buffers
 423          * that are allocated outside of the range addressable by the GATHER
 424          * opcode.
 425          *
 426          * Newer generations of Tegra (Tegra186 and later) support a wide
 427          * variant of the GATHER opcode that allows addressing more bits.
 428          */
 429         if (!domain && !host->info->has_wide_gather)
 430                 mask = DMA_BIT_MASK(32);
 431
 432         err = dma_coerce_mask_and_coherent(host->dev, mask);
 433         if (err < 0) {
 434                 dev_err(host->dev, "failed to set DMA mask: %d\n", err);
 435                 return err;
 436         }
 437
 438         return 0;
 439 }
 440
 441 static void host1x_iommu_exit(struct host1x *host)
 442 {
 443         if (host->domain) {
 444                 put_iova_domain(&host->iova);
 445                 iommu_detach_group(host->domain, host->group);
 446
 447                 iommu_domain_free(host->domain);
 448                 host->domain = NULL;
 449
 450                 iova_cache_put();
 451
 452                 iommu_group_put(host->group);
 453                 host->group = NULL;
 454         }
 455 }
 456
 457 static int host1x_get_resets(struct host1x *host)
 458 {
 459         int err;
 460
 461         host->resets[0].id = "mc";
 462         host->resets[1].id = "host1x";
 463         host->nresets = ARRAY_SIZE(host->resets);
 464
 465         err = devm_reset_control_bulk_get_optional_exclusive_released(
 466                                 host->dev, host->nresets, host->resets);
 467         if (err) {
 468                 dev_err(host->dev, "failed to get reset: %d\n", err);
 469                 return err;
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int host1x_probe(struct platform_device *pdev)
 476 {
 477         struct host1x *host;
 478         int syncpt_irq;
 479         int err;
 480
 481         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 482         if (!host)
 483                 return -ENOMEM;
 484
 485         host->info = of_device_get_match_data(&pdev->dev);
 486
 487         if (host->info->has_hypervisor) {
 488                 host->regs = devm_platform_ioremap_resource_byname(pdev, "vm");
 489                 if (IS_ERR(host->regs))
 490                         return PTR_ERR(host->regs);
 491
 492                 host->hv_regs = devm_platform_ioremap_resource_byname(pdev, "hypervisor");
 493                 if (IS_ERR(host->hv_regs))
 494                         return PTR_ERR(host->hv_regs);
 495
 496                 if (host->info->has_common) {
 497                         host->common_regs = devm_platform_ioremap_resource_byname(pdev, "common");
 498                         if (IS_ERR(host->common_regs))
 499                                 return PTR_ERR(host->common_regs);
 500                 }
 501         } else {
 502                 host->regs = devm_platform_ioremap_resource(pdev, 0);
 503                 if (IS_ERR(host->regs))
 504                         return PTR_ERR(host->regs);
 505         }
 506
 507         syncpt_irq = platform_get_irq(pdev, 0);
 508         if (syncpt_irq < 0)
 509                 return syncpt_irq;
 510
 511         mutex_init(&host->devices_lock);
 512         INIT_LIST_HEAD(&host->devices);
 513         INIT_LIST_HEAD(&host->list);
 514         host->dev = &pdev->dev;
 515
 516         /* set common host1x device data */
 517         platform_set_drvdata(pdev, host);
 518
 519         host->dev->dma_parms = &host->dma_parms;
 520         dma_set_max_seg_size(host->dev, UINT_MAX);
 521
 522         if (host->info->init) {
 523                 err = host->info->init(host);
 524                 if (err)
 525                         return err;
 526         }
 527
 528         host->clk = devm_clk_get(&pdev->dev, NULL);
 529         if (IS_ERR(host->clk)) {
 530                 err = PTR_ERR(host->clk);
 531
 532                 if (err != -EPROBE_DEFER)
 533                         dev_err(&pdev->dev, "failed to get clock: %d\n", err);
 534
 535                 return err;
 536         }
 537
 538         err = host1x_get_resets(host);
 539         if (err)
 540                 return err;
 541
 542         host1x_bo_cache_init(&host->cache);
 543
 544         err = host1x_iommu_init(host);
 545         if (err < 0) {
 546                 dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err);
 547                 goto destroy_cache;
 548         }
 549
 550         err = host1x_channel_list_init(&host->channel_list,
 551                                        host->info->nb_channels);
 552         if (err) {
 553                 dev_err(&pdev->dev, "failed to initialize channel list\n");
 554                 goto iommu_exit;
 555         }
 556
 557         err = host1x_memory_context_list_init(host);
 558         if (err) {
 559                 dev_err(&pdev->dev, "failed to initialize context list\n");
 560                 goto free_channels;
 561         }
 562
 563         err = host1x_syncpt_init(host);
 564         if (err) {
 565                 dev_err(&pdev->dev, "failed to initialize syncpts\n");
 566                 goto free_contexts;
 567         }
 568
 569         err = host1x_intr_init(host, syncpt_irq);
 570         if (err) {
 571                 dev_err(&pdev->dev, "failed to initialize interrupts\n");
 572                 goto deinit_syncpt;
 573         }
 574
 575         pm_runtime_enable(&pdev->dev);
 576
 577         err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
 578         if (err)
 579                 goto pm_disable;
 580
 581         /* the driver's code isn't ready yet for the dynamic RPM */
 582         err = pm_runtime_resume_and_get(&pdev->dev);
 583         if (err)
 584                 goto pm_disable;
 585
 586         host1x_debug_init(host);
 587
 588         err = host1x_register(host);
 589         if (err < 0)
 590                 goto deinit_debugfs;
 591
 592         err = devm_of_platform_populate(&pdev->dev);
 593         if (err < 0)
 594                 goto unregister;
 595
 596         return 0;
 597
 598 unregister:
 599         host1x_unregister(host);
 600 deinit_debugfs:
 601         host1x_debug_deinit(host);
 602
 603         pm_runtime_put_sync_suspend(&pdev->dev);
 604 pm_disable:
 605         pm_runtime_disable(&pdev->dev);
 606
 607         host1x_intr_deinit(host);
 608 deinit_syncpt:
 609         host1x_syncpt_deinit(host);
 610 free_contexts:
 611         host1x_memory_context_list_free(&host->context_list);
 612 free_channels:
 613         host1x_channel_list_free(&host->channel_list);
 614 iommu_exit:
 615         host1x_iommu_exit(host);
 616 destroy_cache:
 617         host1x_bo_cache_destroy(&host->cache);
 618
 619         return err;
 620 }
 621
 622 static int host1x_remove(struct platform_device *pdev)
 623 {
 624         struct host1x *host = platform_get_drvdata(pdev);
 625
 626         host1x_unregister(host);
 627         host1x_debug_deinit(host);
 628
 629         pm_runtime_force_suspend(&pdev->dev);
 630
 631         host1x_intr_deinit(host);
 632         host1x_syncpt_deinit(host);
 633         host1x_memory_context_list_free(&host->context_list);
 634         host1x_channel_list_free(&host->channel_list);
 635         host1x_iommu_exit(host);
 636         host1x_bo_cache_destroy(&host->cache);
 637
 638         return 0;
 639 }
 640
 641 static int __maybe_unused host1x_runtime_suspend(struct device *dev)
 642 {
 643         struct host1x *host = dev_get_drvdata(dev);
 644         int err;
 645
 646         host1x_intr_stop(host);
 647         host1x_syncpt_save(host);
 648
 649         err = reset_control_bulk_assert(host->nresets, host->resets);
 650         if (err) {
 651                 dev_err(dev, "failed to assert reset: %d\n", err);
 652                 goto resume_host1x;
 653         }
 654
 655         usleep_range(1000, 2000);
 656
 657         clk_disable_unprepare(host->clk);
 658         reset_control_bulk_release(host->nresets, host->resets);
 659
 660         return 0;
 661
 662 resume_host1x:
 663         host1x_setup_virtualization_tables(host);
 664         host1x_syncpt_restore(host);
 665         host1x_intr_start(host);
 666
 667         return err;
 668 }
 669
 670 static int __maybe_unused host1x_runtime_resume(struct device *dev)
 671 {
 672         struct host1x *host = dev_get_drvdata(dev);
 673         int err;
 674
 675         err = reset_control_bulk_acquire(host->nresets, host->resets);
 676         if (err) {
 677                 dev_err(dev, "failed to acquire reset: %d\n", err);
 678                 return err;
 679         }
 680
 681         err = clk_prepare_enable(host->clk);
 682         if (err) {
 683                 dev_err(dev, "failed to enable clock: %d\n", err);
 684                 goto release_reset;
 685         }
 686
 687         err = reset_control_bulk_deassert(host->nresets, host->resets);
 688         if (err < 0) {
 689                 dev_err(dev, "failed to deassert reset: %d\n", err);
 690                 goto disable_clk;
 691         }
 692
 693         host1x_setup_virtualization_tables(host);
 694         host1x_syncpt_restore(host);
 695         host1x_intr_start(host);
 696
 697         return 0;
 698
 699 disable_clk:
 700         clk_disable_unprepare(host->clk);
 701 release_reset:
 702         reset_control_bulk_release(host->nresets, host->resets);
 703
 704         return err;
 705 }
 706
 707 static const struct dev_pm_ops host1x_pm_ops = {
 708         SET_RUNTIME_PM_OPS(host1x_runtime_suspend, host1x_runtime_resume,
 709                            NULL)
 710         /* TODO: add system suspend-resume once driver will be ready for that */
 711 };
 712
 713 static struct platform_driver tegra_host1x_driver = {
 714         .driver = {
 715                 .name = "tegra-host1x",
 716                 .of_match_table = host1x_of_match,
 717                 .pm = &host1x_pm_ops,
 718         },
 719         .probe = host1x_probe,
 720         .remove = host1x_remove,
 721 };
 722
 723 static struct platform_driver * const drivers[] = {
 724         &tegra_host1x_driver,
 725         &tegra_mipi_driver,
 726 };
 727
 728 static int __init tegra_host1x_init(void)
 729 {
 730         int err;
 731
 732         err = bus_register(&host1x_bus_type);
 733         if (err < 0)
 734                 return err;
 735
 736         err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
 737         if (err < 0)
 738                 bus_unregister(&host1x_bus_type);
 739
 740         return err;
 741 }
 742 module_init(tegra_host1x_init);
 743
 744 static void __exit tegra_host1x_exit(void)
 745 {
 746         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
 747         bus_unregister(&host1x_bus_type);
 748 }
 749 module_exit(tegra_host1x_exit);
 750
 751 /**
 752  * host1x_get_dma_mask() - query the supported DMA mask for host1x
 753  * @host1x: host1x instance
 754  *
 755  * Note that this returns the supported DMA mask for host1x, which can be
 756  * different from the applicable DMA mask under certain circumstances.
 757  */
 758 u64 host1x_get_dma_mask(struct host1x *host1x)
 759 {
 760         return host1x->info->dma_mask;
 761 }
 762 EXPORT_SYMBOL(host1x_get_dma_mask);
 763
 764 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
 765 MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>");
 766 MODULE_DESCRIPTION("Host1x driver for Tegra products");
 767 MODULE_LICENSE("GPL");