drivers/gpu/drm/xlnx/zynqmp_dp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ZynqMP DisplayPort Driver
   4  *
   5  * Copyright (C) 2017 - 2020 Xilinx, Inc.
   6  *
   7  * Authors:
   8  * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
   9  * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10  */
  11
  12 #include <drm/display/drm_dp_helper.h>
  13 #include <drm/drm_atomic_helper.h>
  14 #include <drm/drm_connector.h>
  15 #include <drm/drm_crtc.h>
  16 #include <drm/drm_device.h>
  17 #include <drm/drm_edid.h>
  18 #include <drm/drm_encoder.h>
  19 #include <drm/drm_managed.h>
  20 #include <drm/drm_modes.h>
  21 #include <drm/drm_of.h>
  22 #include <drm/drm_probe_helper.h>
  23 #include <drm/drm_simple_kms_helper.h>
  24
  25 #include <linux/clk.h>
  26 #include <linux/delay.h>
  27 #include <linux/device.h>
  28 #include <linux/io.h>
  29 #include <linux/module.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/phy/phy.h>
  33 #include <linux/reset.h>
  34
  35 #include "zynqmp_disp.h"
  36 #include "zynqmp_dp.h"
  37 #include "zynqmp_dpsub.h"
  38
  39 static uint zynqmp_dp_aux_timeout_ms = 50;
  40 module_param_named(aux_timeout_ms, zynqmp_dp_aux_timeout_ms, uint, 0444);
  41 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
  42
  43 /*
  44  * Some sink requires a delay after power on request
  45  */
  46 static uint zynqmp_dp_power_on_delay_ms = 4;
  47 module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444);
  48 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
  49
  50 /* Link configuration registers */
  51 #define ZYNQMP_DP_LINK_BW_SET                           0x0
  52 #define ZYNQMP_DP_LANE_COUNT_SET                        0x4
  53 #define ZYNQMP_DP_ENHANCED_FRAME_EN                     0x8
  54 #define ZYNQMP_DP_TRAINING_PATTERN_SET                  0xc
  55 #define ZYNQMP_DP_SCRAMBLING_DISABLE                    0x14
  56 #define ZYNQMP_DP_DOWNSPREAD_CTL                        0x18
  57 #define ZYNQMP_DP_SOFTWARE_RESET                        0x1c
  58 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM1                BIT(0)
  59 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM2                BIT(1)
  60 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM3                BIT(2)
  61 #define ZYNQMP_DP_SOFTWARE_RESET_STREAM4                BIT(3)
  62 #define ZYNQMP_DP_SOFTWARE_RESET_AUX                    BIT(7)
  63 #define ZYNQMP_DP_SOFTWARE_RESET_ALL                    (ZYNQMP_DP_SOFTWARE_RESET_STREAM1 | \
  64                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM2 | \
  65                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM3 | \
  66                                                          ZYNQMP_DP_SOFTWARE_RESET_STREAM4 | \
  67                                                          ZYNQMP_DP_SOFTWARE_RESET_AUX)
  68
  69 /* Core enable registers */
  70 #define ZYNQMP_DP_TRANSMITTER_ENABLE                    0x80
  71 #define ZYNQMP_DP_MAIN_STREAM_ENABLE                    0x84
  72 #define ZYNQMP_DP_FORCE_SCRAMBLER_RESET                 0xc0
  73 #define ZYNQMP_DP_VERSION                               0xf8
  74 #define ZYNQMP_DP_VERSION_MAJOR_MASK                    GENMASK(31, 24)
  75 #define ZYNQMP_DP_VERSION_MAJOR_SHIFT                   24
  76 #define ZYNQMP_DP_VERSION_MINOR_MASK                    GENMASK(23, 16)
  77 #define ZYNQMP_DP_VERSION_MINOR_SHIFT                   16
  78 #define ZYNQMP_DP_VERSION_REVISION_MASK                 GENMASK(15, 12)
  79 #define ZYNQMP_DP_VERSION_REVISION_SHIFT                12
  80 #define ZYNQMP_DP_VERSION_PATCH_MASK                    GENMASK(11, 8)
  81 #define ZYNQMP_DP_VERSION_PATCH_SHIFT                   8
  82 #define ZYNQMP_DP_VERSION_INTERNAL_MASK                 GENMASK(7, 0)
  83 #define ZYNQMP_DP_VERSION_INTERNAL_SHIFT                0
  84
  85 /* Core ID registers */
  86 #define ZYNQMP_DP_CORE_ID                               0xfc
  87 #define ZYNQMP_DP_CORE_ID_MAJOR_MASK                    GENMASK(31, 24)
  88 #define ZYNQMP_DP_CORE_ID_MAJOR_SHIFT                   24
  89 #define ZYNQMP_DP_CORE_ID_MINOR_MASK                    GENMASK(23, 16)
  90 #define ZYNQMP_DP_CORE_ID_MINOR_SHIFT                   16
  91 #define ZYNQMP_DP_CORE_ID_REVISION_MASK                 GENMASK(15, 8)
  92 #define ZYNQMP_DP_CORE_ID_REVISION_SHIFT                8
  93 #define ZYNQMP_DP_CORE_ID_DIRECTION                     GENMASK(1)
  94
  95 /* AUX channel interface registers */
  96 #define ZYNQMP_DP_AUX_COMMAND                           0x100
  97 #define ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT                 8
  98 #define ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY              BIT(12)
  99 #define ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT               0
 100 #define ZYNQMP_DP_AUX_WRITE_FIFO                        0x104
 101 #define ZYNQMP_DP_AUX_ADDRESS                           0x108
 102 #define ZYNQMP_DP_AUX_CLK_DIVIDER                       0x10c
 103 #define ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT      8
 104 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE                0x130
 105 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD            BIT(0)
 106 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST        BIT(1)
 107 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY          BIT(2)
 108 #define ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT  BIT(3)
 109 #define ZYNQMP_DP_AUX_REPLY_DATA                        0x134
 110 #define ZYNQMP_DP_AUX_REPLY_CODE                        0x138
 111 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK                (0)
 112 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_NACK               BIT(0)
 113 #define ZYNQMP_DP_AUX_REPLY_CODE_AUX_DEFER              BIT(1)
 114 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK                (0)
 115 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_NACK               BIT(2)
 116 #define ZYNQMP_DP_AUX_REPLY_CODE_I2C_DEFER              BIT(3)
 117 #define ZYNQMP_DP_AUX_REPLY_COUNT                       0x13c
 118 #define ZYNQMP_DP_REPLY_DATA_COUNT                      0x148
 119 #define ZYNQMP_DP_REPLY_DATA_COUNT_MASK                 0xff
 120 #define ZYNQMP_DP_INT_STATUS                            0x3a0
 121 #define ZYNQMP_DP_INT_MASK                              0x3a4
 122 #define ZYNQMP_DP_INT_EN                                0x3a8
 123 #define ZYNQMP_DP_INT_DS                                0x3ac
 124 #define ZYNQMP_DP_INT_HPD_IRQ                           BIT(0)
 125 #define ZYNQMP_DP_INT_HPD_EVENT                         BIT(1)
 126 #define ZYNQMP_DP_INT_REPLY_RECEIVED                    BIT(2)
 127 #define ZYNQMP_DP_INT_REPLY_TIMEOUT                     BIT(3)
 128 #define ZYNQMP_DP_INT_HPD_PULSE_DET                     BIT(4)
 129 #define ZYNQMP_DP_INT_EXT_PKT_TXD                       BIT(5)
 130 #define ZYNQMP_DP_INT_LIV_ABUF_UNDRFLW                  BIT(12)
 131 #define ZYNQMP_DP_INT_VBLANK_START                      BIT(13)
 132 #define ZYNQMP_DP_INT_PIXEL1_MATCH                      BIT(14)
 133 #define ZYNQMP_DP_INT_PIXEL0_MATCH                      BIT(15)
 134 #define ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK               0x3f0000
 135 #define ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK                0xfc00000
 136 #define ZYNQMP_DP_INT_CUST_TS_2                         BIT(28)
 137 #define ZYNQMP_DP_INT_CUST_TS                           BIT(29)
 138 #define ZYNQMP_DP_INT_EXT_VSYNC_TS                      BIT(30)
 139 #define ZYNQMP_DP_INT_VSYNC_TS                          BIT(31)
 140 #define ZYNQMP_DP_INT_ALL                               (ZYNQMP_DP_INT_HPD_IRQ | \
 141                                                          ZYNQMP_DP_INT_HPD_EVENT | \
 142                                                          ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK | \
 143                                                          ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK)
 144
 145 /* Main stream attribute registers */
 146 #define ZYNQMP_DP_MAIN_STREAM_HTOTAL                    0x180
 147 #define ZYNQMP_DP_MAIN_STREAM_VTOTAL                    0x184
 148 #define ZYNQMP_DP_MAIN_STREAM_POLARITY                  0x188
 149 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT      0
 150 #define ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT      1
 151 #define ZYNQMP_DP_MAIN_STREAM_HSWIDTH                   0x18c
 152 #define ZYNQMP_DP_MAIN_STREAM_VSWIDTH                   0x190
 153 #define ZYNQMP_DP_MAIN_STREAM_HRES                      0x194
 154 #define ZYNQMP_DP_MAIN_STREAM_VRES                      0x198
 155 #define ZYNQMP_DP_MAIN_STREAM_HSTART                    0x19c
 156 #define ZYNQMP_DP_MAIN_STREAM_VSTART                    0x1a0
 157 #define ZYNQMP_DP_MAIN_STREAM_MISC0                     0x1a4
 158 #define ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK           BIT(0)
 159 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB     (0 << 1)
 160 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422       (5 << 1)
 161 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444       (6 << 1)
 162 #define ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK    (7 << 1)
 163 #define ZYNQMP_DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE       BIT(3)
 164 #define ZYNQMP_DP_MAIN_STREAM_MISC0_YCBCR_COLR          BIT(4)
 165 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6               (0 << 5)
 166 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8               (1 << 5)
 167 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10              (2 << 5)
 168 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12              (3 << 5)
 169 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16              (4 << 5)
 170 #define ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK            (7 << 5)
 171 #define ZYNQMP_DP_MAIN_STREAM_MISC1                     0x1a8
 172 #define ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN           BIT(7)
 173 #define ZYNQMP_DP_MAIN_STREAM_M_VID                     0x1ac
 174 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE                0x1b0
 175 #define ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF    64
 176 #define ZYNQMP_DP_MAIN_STREAM_N_VID                     0x1b4
 177 #define ZYNQMP_DP_USER_PIX_WIDTH                        0x1b8
 178 #define ZYNQMP_DP_USER_DATA_COUNT_PER_LANE              0x1bc
 179 #define ZYNQMP_DP_MIN_BYTES_PER_TU                      0x1c4
 180 #define ZYNQMP_DP_FRAC_BYTES_PER_TU                     0x1c8
 181 #define ZYNQMP_DP_INIT_WAIT                             0x1cc
 182
 183 /* PHY configuration and status registers */
 184 #define ZYNQMP_DP_PHY_RESET                             0x200
 185 #define ZYNQMP_DP_PHY_RESET_PHY_RESET                   BIT(0)
 186 #define ZYNQMP_DP_PHY_RESET_GTTX_RESET                  BIT(1)
 187 #define ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET               BIT(8)
 188 #define ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET               BIT(9)
 189 #define ZYNQMP_DP_PHY_RESET_ALL_RESET                   (ZYNQMP_DP_PHY_RESET_PHY_RESET | \
 190                                                          ZYNQMP_DP_PHY_RESET_GTTX_RESET | \
 191                                                          ZYNQMP_DP_PHY_RESET_PHY_PMA_RESET | \
 192                                                          ZYNQMP_DP_PHY_RESET_PHY_PCS_RESET)
 193 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_0                0x210
 194 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_1                0x214
 195 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_2                0x218
 196 #define ZYNQMP_DP_PHY_PREEMPHASIS_LANE_3                0x21c
 197 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_0               0x220
 198 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_1               0x224
 199 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_2               0x228
 200 #define ZYNQMP_DP_PHY_VOLTAGE_DIFF_LANE_3               0x22c
 201 #define ZYNQMP_DP_PHY_CLOCK_SELECT                      0x234
 202 #define ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G                0x1
 203 #define ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G                0x3
 204 #define ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G                0x5
 205 #define ZYNQMP_DP_TX_PHY_POWER_DOWN                     0x238
 206 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_0              BIT(0)
 207 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_1              BIT(1)
 208 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_2              BIT(2)
 209 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_LANE_3              BIT(3)
 210 #define ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL                 0xf
 211 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_0                  0x23c
 212 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_1                  0x240
 213 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_2                  0x244
 214 #define ZYNQMP_DP_PHY_PRECURSOR_LANE_3                  0x248
 215 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_0                 0x24c
 216 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_1                 0x250
 217 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_2                 0x254
 218 #define ZYNQMP_DP_PHY_POSTCURSOR_LANE_3                 0x258
 219 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0           0x24c
 220 #define ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_1           0x250
 221 #define ZYNQMP_DP_PHY_STATUS                            0x280
 222 #define ZYNQMP_DP_PHY_STATUS_PLL_LOCKED_SHIFT           4
 223 #define ZYNQMP_DP_PHY_STATUS_FPGA_PLL_LOCKED            BIT(6)
 224
 225 /* Audio registers */
 226 #define ZYNQMP_DP_TX_AUDIO_CONTROL                      0x300
 227 #define ZYNQMP_DP_TX_AUDIO_CHANNELS                     0x304
 228 #define ZYNQMP_DP_TX_AUDIO_INFO_DATA                    0x308
 229 #define ZYNQMP_DP_TX_M_AUD                              0x328
 230 #define ZYNQMP_DP_TX_N_AUD                              0x32c
 231 #define ZYNQMP_DP_TX_AUDIO_EXT_DATA                     0x330
 232
 233 #define ZYNQMP_DP_MAX_LANES                             2
 234 #define ZYNQMP_MAX_FREQ                                 3000000
 235
 236 #define DP_REDUCED_BIT_RATE                             162000
 237 #define DP_HIGH_BIT_RATE                                270000
 238 #define DP_HIGH_BIT_RATE2                               540000
 239 #define DP_MAX_TRAINING_TRIES                           5
 240 #define DP_V1_2                                         0x12
 241
 242 /**
 243  * struct zynqmp_dp_link_config - Common link config between source and sink
 244  * @max_rate: maximum link rate
 245  * @max_lanes: maximum number of lanes
 246  */
 247 struct zynqmp_dp_link_config {
 248         int max_rate;
 249         u8 max_lanes;
 250 };
 251
 252 /**
 253  * struct zynqmp_dp_mode - Configured mode of DisplayPort
 254  * @bw_code: code for bandwidth(link rate)
 255  * @lane_cnt: number of lanes
 256  * @pclock: pixel clock frequency of current mode
 257  * @fmt: format identifier string
 258  */
 259 struct zynqmp_dp_mode {
 260         u8 bw_code;
 261         u8 lane_cnt;
 262         int pclock;
 263         const char *fmt;
 264 };
 265
 266 /**
 267  * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
 268  * @misc0: misc0 configuration (per DP v1.2 spec)
 269  * @misc1: misc1 configuration (per DP v1.2 spec)
 270  * @bpp: bits per pixel
 271  */
 272 struct zynqmp_dp_config {
 273         u8 misc0;
 274         u8 misc1;
 275         u8 bpp;
 276 };
 277
 278 /**
 279  * struct zynqmp_dp - Xilinx DisplayPort core
 280  * @encoder: the drm encoder structure
 281  * @connector: the drm connector structure
 282  * @dev: device structure
 283  * @dpsub: Display subsystem
 284  * @drm: DRM core
 285  * @iomem: device I/O memory for register access
 286  * @reset: reset controller
 287  * @irq: irq
 288  * @config: IP core configuration from DTS
 289  * @aux: aux channel
 290  * @phy: PHY handles for DP lanes
 291  * @num_lanes: number of enabled phy lanes
 292  * @hpd_work: hot plug detection worker
 293  * @status: connection status
 294  * @enabled: flag to indicate if the device is enabled
 295  * @dpcd: DP configuration data from currently connected sink device
 296  * @link_config: common link configuration between IP core and sink device
 297  * @mode: current mode between IP core and sink device
 298  * @train_set: set of training data
 299  */
 300 struct zynqmp_dp {
 301         struct drm_encoder encoder;
 302         struct drm_connector connector;
 303         struct device *dev;
 304         struct zynqmp_dpsub *dpsub;
 305         struct drm_device *drm;
 306         void __iomem *iomem;
 307         struct reset_control *reset;
 308         int irq;
 309
 310         struct zynqmp_dp_config config;
 311         struct drm_dp_aux aux;
 312         struct phy *phy[ZYNQMP_DP_MAX_LANES];
 313         u8 num_lanes;
 314         struct delayed_work hpd_work;
 315         enum drm_connector_status status;
 316         bool enabled;
 317
 318         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 319         struct zynqmp_dp_link_config link_config;
 320         struct zynqmp_dp_mode mode;
 321         u8 train_set[ZYNQMP_DP_MAX_LANES];
 322 };
 323
 324 static inline struct zynqmp_dp *encoder_to_dp(struct drm_encoder *encoder)
 325 {
 326         return container_of(encoder, struct zynqmp_dp, encoder);
 327 }
 328
 329 static inline struct zynqmp_dp *connector_to_dp(struct drm_connector *connector)
 330 {
 331         return container_of(connector, struct zynqmp_dp, connector);
 332 }
 333
 334 static void zynqmp_dp_write(struct zynqmp_dp *dp, int offset, u32 val)
 335 {
 336         writel(val, dp->iomem + offset);
 337 }
 338
 339 static u32 zynqmp_dp_read(struct zynqmp_dp *dp, int offset)
 340 {
 341         return readl(dp->iomem + offset);
 342 }
 343
 344 static void zynqmp_dp_clr(struct zynqmp_dp *dp, int offset, u32 clr)
 345 {
 346         zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) & ~clr);
 347 }
 348
 349 static void zynqmp_dp_set(struct zynqmp_dp *dp, int offset, u32 set)
 350 {
 351         zynqmp_dp_write(dp, offset, zynqmp_dp_read(dp, offset) | set);
 352 }
 353
 354 /* -----------------------------------------------------------------------------
 355  * PHY Handling
 356  */
 357
 358 #define RST_TIMEOUT_MS                  1000
 359
 360 static int zynqmp_dp_reset(struct zynqmp_dp *dp, bool assert)
 361 {
 362         unsigned long timeout;
 363
 364         if (assert)
 365                 reset_control_assert(dp->reset);
 366         else
 367                 reset_control_deassert(dp->reset);
 368
 369         /* Wait for the (de)assert to complete. */
 370         timeout = jiffies + msecs_to_jiffies(RST_TIMEOUT_MS);
 371         while (!time_after_eq(jiffies, timeout)) {
 372                 bool status = !!reset_control_status(dp->reset);
 373
 374                 if (assert == status)
 375                         return 0;
 376
 377                 cpu_relax();
 378         }
 379
 380         dev_err(dp->dev, "reset %s timeout\n", assert ? "assert" : "deassert");
 381         return -ETIMEDOUT;
 382 }
 383
 384 /**
 385  * zynqmp_dp_phy_init - Initialize the phy
 386  * @dp: DisplayPort IP core structure
 387  *
 388  * Initialize the phy.
 389  *
 390  * Return: 0 if the phy instances are initialized correctly, or the error code
 391  * returned from the callee functions.
 392  */
 393 static int zynqmp_dp_phy_init(struct zynqmp_dp *dp)
 394 {
 395         int ret;
 396         int i;
 397
 398         for (i = 0; i < dp->num_lanes; i++) {
 399                 ret = phy_init(dp->phy[i]);
 400                 if (ret) {
 401                         dev_err(dp->dev, "failed to init phy lane %d\n", i);
 402                         return ret;
 403                 }
 404         }
 405
 406         zynqmp_dp_clr(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET);
 407
 408         /*
 409          * Power on lanes in reverse order as only lane 0 waits for the PLL to
 410          * lock.
 411          */
 412         for (i = dp->num_lanes - 1; i >= 0; i--) {
 413                 ret = phy_power_on(dp->phy[i]);
 414                 if (ret) {
 415                         dev_err(dp->dev, "failed to power on phy lane %d\n", i);
 416                         return ret;
 417                 }
 418         }
 419
 420         return 0;
 421 }
 422
 423 /**
 424  * zynqmp_dp_phy_exit - Exit the phy
 425  * @dp: DisplayPort IP core structure
 426  *
 427  * Exit the phy.
 428  */
 429 static void zynqmp_dp_phy_exit(struct zynqmp_dp *dp)
 430 {
 431         unsigned int i;
 432         int ret;
 433
 434         for (i = 0; i < dp->num_lanes; i++) {
 435                 ret = phy_power_off(dp->phy[i]);
 436                 if (ret)
 437                         dev_err(dp->dev, "failed to power off phy(%d) %d\n", i,
 438                                 ret);
 439         }
 440
 441         for (i = 0; i < dp->num_lanes; i++) {
 442                 ret = phy_exit(dp->phy[i]);
 443                 if (ret)
 444                         dev_err(dp->dev, "failed to exit phy(%d) %d\n", i, ret);
 445         }
 446 }
 447
 448 /**
 449  * zynqmp_dp_phy_probe - Probe the PHYs
 450  * @dp: DisplayPort IP core structure
 451  *
 452  * Probe PHYs for all lanes. Less PHYs may be available than the number of
 453  * lanes, which is not considered an error as long as at least one PHY is
 454  * found. The caller can check dp->num_lanes to check how many PHYs were found.
 455  *
 456  * Return:
 457  * * 0                          - Success
 458  * * -ENXIO                     - No PHY found
 459  * * -EPROBE_DEFER              - Probe deferral requested
 460  * * Other negative value       - PHY retrieval failure
 461  */
 462 static int zynqmp_dp_phy_probe(struct zynqmp_dp *dp)
 463 {
 464         unsigned int i;
 465
 466         for (i = 0; i < ZYNQMP_DP_MAX_LANES; i++) {
 467                 char phy_name[16];
 468                 struct phy *phy;
 469
 470                 snprintf(phy_name, sizeof(phy_name), "dp-phy%d", i);
 471                 phy = devm_phy_get(dp->dev, phy_name);
 472
 473                 if (IS_ERR(phy)) {
 474                         switch (PTR_ERR(phy)) {
 475                         case -ENODEV:
 476                                 if (dp->num_lanes)
 477                                         return 0;
 478
 479                                 dev_err(dp->dev, "no PHY found\n");
 480                                 return -ENXIO;
 481
 482                         case -EPROBE_DEFER:
 483                                 return -EPROBE_DEFER;
 484
 485                         default:
 486                                 dev_err(dp->dev, "failed to get PHY lane %u\n",
 487                                         i);
 488                                 return PTR_ERR(phy);
 489                         }
 490                 }
 491
 492                 dp->phy[i] = phy;
 493                 dp->num_lanes++;
 494         }
 495
 496         return 0;
 497 }
 498
 499 /**
 500  * zynqmp_dp_phy_ready - Check if PHY is ready
 501  * @dp: DisplayPort IP core structure
 502  *
 503  * Check if PHY is ready. If PHY is not ready, wait 1ms to check for 100 times.
 504  * This amount of delay was suggested by IP designer.
 505  *
 506  * Return: 0 if PHY is ready, or -ENODEV if PHY is not ready.
 507  */
 508 static int zynqmp_dp_phy_ready(struct zynqmp_dp *dp)
 509 {
 510         u32 i, reg, ready;
 511
 512         ready = (1 << dp->num_lanes) - 1;
 513
 514         /* Wait for 100 * 1ms. This should be enough time for PHY to be ready */
 515         for (i = 0; ; i++) {
 516                 reg = zynqmp_dp_read(dp, ZYNQMP_DP_PHY_STATUS);
 517                 if ((reg & ready) == ready)
 518                         return 0;
 519
 520                 if (i == 100) {
 521                         dev_err(dp->dev, "PHY isn't ready\n");
 522                         return -ENODEV;
 523                 }
 524
 525                 usleep_range(1000, 1100);
 526         }
 527
 528         return 0;
 529 }
 530
 531 /* -----------------------------------------------------------------------------
 532  * DisplayPort Link Training
 533  */
 534
 535 /**
 536  * zynqmp_dp_max_rate - Calculate and return available max pixel clock
 537  * @link_rate: link rate (Kilo-bytes / sec)
 538  * @lane_num: number of lanes
 539  * @bpp: bits per pixel
 540  *
 541  * Return: max pixel clock (KHz) supported by current link config.
 542  */
 543 static inline int zynqmp_dp_max_rate(int link_rate, u8 lane_num, u8 bpp)
 544 {
 545         return link_rate * lane_num * 8 / bpp;
 546 }
 547
 548 /**
 549  * zynqmp_dp_mode_configure - Configure the link values
 550  * @dp: DisplayPort IP core structure
 551  * @pclock: pixel clock for requested display mode
 552  * @current_bw: current link rate
 553  *
 554  * Find the link configuration values, rate and lane count for requested pixel
 555  * clock @pclock. The @pclock is stored in the mode to be used in other
 556  * functions later. The returned rate is downshifted from the current rate
 557  * @current_bw.
 558  *
 559  * Return: Current link rate code, or -EINVAL.
 560  */
 561 static int zynqmp_dp_mode_configure(struct zynqmp_dp *dp, int pclock,
 562                                     u8 current_bw)
 563 {
 564         int max_rate = dp->link_config.max_rate;
 565         u8 bw_code;
 566         u8 max_lanes = dp->link_config.max_lanes;
 567         u8 max_link_rate_code = drm_dp_link_rate_to_bw_code(max_rate);
 568         u8 bpp = dp->config.bpp;
 569         u8 lane_cnt;
 570
 571         /* Downshift from current bandwidth */
 572         switch (current_bw) {
 573         case DP_LINK_BW_5_4:
 574                 bw_code = DP_LINK_BW_2_7;
 575                 break;
 576         case DP_LINK_BW_2_7:
 577                 bw_code = DP_LINK_BW_1_62;
 578                 break;
 579         case DP_LINK_BW_1_62:
 580                 dev_err(dp->dev, "can't downshift. already lowest link rate\n");
 581                 return -EINVAL;
 582         default:
 583                 /* If not given, start with max supported */
 584                 bw_code = max_link_rate_code;
 585                 break;
 586         }
 587
 588         for (lane_cnt = 1; lane_cnt <= max_lanes; lane_cnt <<= 1) {
 589                 int bw;
 590                 u32 rate;
 591
 592                 bw = drm_dp_bw_code_to_link_rate(bw_code);
 593                 rate = zynqmp_dp_max_rate(bw, lane_cnt, bpp);
 594                 if (pclock <= rate) {
 595                         dp->mode.bw_code = bw_code;
 596                         dp->mode.lane_cnt = lane_cnt;
 597                         dp->mode.pclock = pclock;
 598                         return dp->mode.bw_code;
 599                 }
 600         }
 601
 602         dev_err(dp->dev, "failed to configure link values\n");
 603
 604         return -EINVAL;
 605 }
 606
 607 /**
 608  * zynqmp_dp_adjust_train - Adjust train values
 609  * @dp: DisplayPort IP core structure
 610  * @link_status: link status from sink which contains requested training values
 611  */
 612 static void zynqmp_dp_adjust_train(struct zynqmp_dp *dp,
 613                                    u8 link_status[DP_LINK_STATUS_SIZE])
 614 {
 615         u8 *train_set = dp->train_set;
 616         u8 voltage = 0, preemphasis = 0;
 617         u8 i;
 618
 619         for (i = 0; i < dp->mode.lane_cnt; i++) {
 620                 u8 v = drm_dp_get_adjust_request_voltage(link_status, i);
 621                 u8 p = drm_dp_get_adjust_request_pre_emphasis(link_status, i);
 622
 623                 if (v > voltage)
 624                         voltage = v;
 625
 626                 if (p > preemphasis)
 627                         preemphasis = p;
 628         }
 629
 630         if (voltage >= DP_TRAIN_VOLTAGE_SWING_LEVEL_3)
 631                 voltage |= DP_TRAIN_MAX_SWING_REACHED;
 632
 633         if (preemphasis >= DP_TRAIN_PRE_EMPH_LEVEL_2)
 634                 preemphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 635
 636         for (i = 0; i < dp->mode.lane_cnt; i++)
 637                 train_set[i] = voltage | preemphasis;
 638 }
 639
 640 /**
 641  * zynqmp_dp_update_vs_emph - Update the training values
 642  * @dp: DisplayPort IP core structure
 643  *
 644  * Update the training values based on the request from sink. The mapped values
 645  * are predefined, and values(vs, pe, pc) are from the device manual.
 646  *
 647  * Return: 0 if vs and emph are updated successfully, or the error code returned
 648  * by drm_dp_dpcd_write().
 649  */
 650 static int zynqmp_dp_update_vs_emph(struct zynqmp_dp *dp)
 651 {
 652         unsigned int i;
 653         int ret;
 654
 655         ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set,
 656                                 dp->mode.lane_cnt);
 657         if (ret < 0)
 658                 return ret;
 659
 660         for (i = 0; i < dp->mode.lane_cnt; i++) {
 661                 u32 reg = ZYNQMP_DP_SUB_TX_PHY_PRECURSOR_LANE_0 + i * 4;
 662                 union phy_configure_opts opts = { 0 };
 663                 u8 train = dp->train_set[i];
 664
 665                 opts.dp.voltage[0] = (train & DP_TRAIN_VOLTAGE_SWING_MASK)
 666                                    >> DP_TRAIN_VOLTAGE_SWING_SHIFT;
 667                 opts.dp.pre[0] = (train & DP_TRAIN_PRE_EMPHASIS_MASK)
 668                                >> DP_TRAIN_PRE_EMPHASIS_SHIFT;
 669
 670                 phy_configure(dp->phy[i], &opts);
 671
 672                 zynqmp_dp_write(dp, reg, 0x2);
 673         }
 674
 675         return 0;
 676 }
 677
 678 /**
 679  * zynqmp_dp_link_train_cr - Train clock recovery
 680  * @dp: DisplayPort IP core structure
 681  *
 682  * Return: 0 if clock recovery train is done successfully, or corresponding
 683  * error code.
 684  */
 685 static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp)
 686 {
 687         u8 link_status[DP_LINK_STATUS_SIZE];
 688         u8 lane_cnt = dp->mode.lane_cnt;
 689         u8 vs = 0, tries = 0;
 690         u16 max_tries, i;
 691         bool cr_done;
 692         int ret;
 693
 694         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET,
 695                         DP_TRAINING_PATTERN_1);
 696         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 697                                  DP_TRAINING_PATTERN_1 |
 698                                  DP_LINK_SCRAMBLING_DISABLE);
 699         if (ret < 0)
 700                 return ret;
 701
 702         /*
 703          * 256 loops should be maximum iterations for 4 lanes and 4 values.
 704          * So, This loop should exit before 512 iterations
 705          */
 706         for (max_tries = 0; max_tries < 512; max_tries++) {
 707                 ret = zynqmp_dp_update_vs_emph(dp);
 708                 if (ret)
 709                         return ret;
 710
 711                 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd);
 712                 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
 713                 if (ret < 0)
 714                         return ret;
 715
 716                 cr_done = drm_dp_clock_recovery_ok(link_status, lane_cnt);
 717                 if (cr_done)
 718                         break;
 719
 720                 for (i = 0; i < lane_cnt; i++)
 721                         if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED))
 722                                 break;
 723                 if (i == lane_cnt)
 724                         break;
 725
 726                 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs)
 727                         tries++;
 728                 else
 729                         tries = 0;
 730
 731                 if (tries == DP_MAX_TRAINING_TRIES)
 732                         break;
 733
 734                 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 735                 zynqmp_dp_adjust_train(dp, link_status);
 736         }
 737
 738         if (!cr_done)
 739                 return -EIO;
 740
 741         return 0;
 742 }
 743
 744 /**
 745  * zynqmp_dp_link_train_ce - Train channel equalization
 746  * @dp: DisplayPort IP core structure
 747  *
 748  * Return: 0 if channel equalization train is done successfully, or
 749  * corresponding error code.
 750  */
 751 static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp)
 752 {
 753         u8 link_status[DP_LINK_STATUS_SIZE];
 754         u8 lane_cnt = dp->mode.lane_cnt;
 755         u32 pat, tries;
 756         int ret;
 757         bool ce_done;
 758
 759         if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 &&
 760             dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED)
 761                 pat = DP_TRAINING_PATTERN_3;
 762         else
 763                 pat = DP_TRAINING_PATTERN_2;
 764
 765         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET, pat);
 766         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 767                                  pat | DP_LINK_SCRAMBLING_DISABLE);
 768         if (ret < 0)
 769                 return ret;
 770
 771         for (tries = 0; tries < DP_MAX_TRAINING_TRIES; tries++) {
 772                 ret = zynqmp_dp_update_vs_emph(dp);
 773                 if (ret)
 774                         return ret;
 775
 776                 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd);
 777                 ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status);
 778                 if (ret < 0)
 779                         return ret;
 780
 781                 ce_done = drm_dp_channel_eq_ok(link_status, lane_cnt);
 782                 if (ce_done)
 783                         break;
 784
 785                 zynqmp_dp_adjust_train(dp, link_status);
 786         }
 787
 788         if (!ce_done)
 789                 return -EIO;
 790
 791         return 0;
 792 }
 793
 794 /**
 795  * zynqmp_dp_link_train - Train the link
 796  * @dp: DisplayPort IP core structure
 797  *
 798  * Return: 0 if all trains are done successfully, or corresponding error code.
 799  */
 800 static int zynqmp_dp_train(struct zynqmp_dp *dp)
 801 {
 802         u32 reg;
 803         u8 bw_code = dp->mode.bw_code;
 804         u8 lane_cnt = dp->mode.lane_cnt;
 805         u8 aux_lane_cnt = lane_cnt;
 806         bool enhanced;
 807         int ret;
 808
 809         zynqmp_dp_write(dp, ZYNQMP_DP_LANE_COUNT_SET, lane_cnt);
 810         enhanced = drm_dp_enhanced_frame_cap(dp->dpcd);
 811         if (enhanced) {
 812                 zynqmp_dp_write(dp, ZYNQMP_DP_ENHANCED_FRAME_EN, 1);
 813                 aux_lane_cnt |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 814         }
 815
 816         if (dp->dpcd[3] & 0x1) {
 817                 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 1);
 818                 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL,
 819                                    DP_SPREAD_AMP_0_5);
 820         } else {
 821                 zynqmp_dp_write(dp, ZYNQMP_DP_DOWNSPREAD_CTL, 0);
 822                 drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0);
 823         }
 824
 825         ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt);
 826         if (ret < 0) {
 827                 dev_err(dp->dev, "failed to set lane count\n");
 828                 return ret;
 829         }
 830
 831         ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
 832                                  DP_SET_ANSI_8B10B);
 833         if (ret < 0) {
 834                 dev_err(dp->dev, "failed to set ANSI 8B/10B encoding\n");
 835                 return ret;
 836         }
 837
 838         ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code);
 839         if (ret < 0) {
 840                 dev_err(dp->dev, "failed to set DP bandwidth\n");
 841                 return ret;
 842         }
 843
 844         zynqmp_dp_write(dp, ZYNQMP_DP_LINK_BW_SET, bw_code);
 845         switch (bw_code) {
 846         case DP_LINK_BW_1_62:
 847                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_1_62G;
 848                 break;
 849         case DP_LINK_BW_2_7:
 850                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_2_70G;
 851                 break;
 852         case DP_LINK_BW_5_4:
 853         default:
 854                 reg = ZYNQMP_DP_PHY_CLOCK_SELECT_5_40G;
 855                 break;
 856         }
 857
 858         zynqmp_dp_write(dp, ZYNQMP_DP_PHY_CLOCK_SELECT, reg);
 859         ret = zynqmp_dp_phy_ready(dp);
 860         if (ret < 0)
 861                 return ret;
 862
 863         zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 1);
 864         memset(dp->train_set, 0, sizeof(dp->train_set));
 865         ret = zynqmp_dp_link_train_cr(dp);
 866         if (ret)
 867                 return ret;
 868
 869         ret = zynqmp_dp_link_train_ce(dp);
 870         if (ret)
 871                 return ret;
 872
 873         ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 874                                  DP_TRAINING_PATTERN_DISABLE);
 875         if (ret < 0) {
 876                 dev_err(dp->dev, "failed to disable training pattern\n");
 877                 return ret;
 878         }
 879         zynqmp_dp_write(dp, ZYNQMP_DP_TRAINING_PATTERN_SET,
 880                         DP_TRAINING_PATTERN_DISABLE);
 881
 882         zynqmp_dp_write(dp, ZYNQMP_DP_SCRAMBLING_DISABLE, 0);
 883
 884         return 0;
 885 }
 886
 887 /**
 888  * zynqmp_dp_train_loop - Downshift the link rate during training
 889  * @dp: DisplayPort IP core structure
 890  *
 891  * Train the link by downshifting the link rate if training is not successful.
 892  */
 893 static void zynqmp_dp_train_loop(struct zynqmp_dp *dp)
 894 {
 895         struct zynqmp_dp_mode *mode = &dp->mode;
 896         u8 bw = mode->bw_code;
 897         int ret;
 898
 899         do {
 900                 if (dp->status == connector_status_disconnected ||
 901                     !dp->enabled)
 902                         return;
 903
 904                 ret = zynqmp_dp_train(dp);
 905                 if (!ret)
 906                         return;
 907
 908                 ret = zynqmp_dp_mode_configure(dp, mode->pclock, bw);
 909                 if (ret < 0)
 910                         goto err_out;
 911
 912                 bw = ret;
 913         } while (bw >= DP_LINK_BW_1_62);
 914
 915 err_out:
 916         dev_err(dp->dev, "failed to train the DP link\n");
 917 }
 918
 919 /* -----------------------------------------------------------------------------
 920  * DisplayPort AUX
 921  */
 922
 923 #define AUX_READ_BIT    0x1
 924
 925 /**
 926  * zynqmp_dp_aux_cmd_submit - Submit aux command
 927  * @dp: DisplayPort IP core structure
 928  * @cmd: aux command
 929  * @addr: aux address
 930  * @buf: buffer for command data
 931  * @bytes: number of bytes for @buf
 932  * @reply: reply code to be returned
 933  *
 934  * Submit an aux command. All aux related commands, native or i2c aux
 935  * read/write, are submitted through this function. The function is mapped to
 936  * the transfer function of struct drm_dp_aux. This function involves in
 937  * multiple register reads/writes, thus synchronization is needed, and it is
 938  * done by drm_dp_helper using @hw_mutex. The calling thread goes into sleep
 939  * if there's no immediate reply to the command submission. The reply code is
 940  * returned at @reply if @reply != NULL.
 941  *
 942  * Return: 0 if the command is submitted properly, or corresponding error code:
 943  * -EBUSY when there is any request already being processed
 944  * -ETIMEDOUT when receiving reply is timed out
 945  * -EIO when received bytes are less than requested
 946  */
 947 static int zynqmp_dp_aux_cmd_submit(struct zynqmp_dp *dp, u32 cmd, u16 addr,
 948                                     u8 *buf, u8 bytes, u8 *reply)
 949 {
 950         bool is_read = (cmd & AUX_READ_BIT) ? true : false;
 951         u32 reg, i;
 952
 953         reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
 954         if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REQUEST)
 955                 return -EBUSY;
 956
 957         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_ADDRESS, addr);
 958         if (!is_read)
 959                 for (i = 0; i < bytes; i++)
 960                         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_WRITE_FIFO,
 961                                         buf[i]);
 962
 963         reg = cmd << ZYNQMP_DP_AUX_COMMAND_CMD_SHIFT;
 964         if (!buf || !bytes)
 965                 reg |= ZYNQMP_DP_AUX_COMMAND_ADDRESS_ONLY;
 966         else
 967                 reg |= (bytes - 1) << ZYNQMP_DP_AUX_COMMAND_BYTES_SHIFT;
 968         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_COMMAND, reg);
 969
 970         /* Wait for reply to be delivered upto 2ms */
 971         for (i = 0; ; i++) {
 972                 reg = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
 973                 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY)
 974                         break;
 975
 976                 if (reg & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_REPLY_TIMEOUT ||
 977                     i == 2)
 978                         return -ETIMEDOUT;
 979
 980                 usleep_range(1000, 1100);
 981         }
 982
 983         reg = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_CODE);
 984         if (reply)
 985                 *reply = reg;
 986
 987         if (is_read &&
 988             (reg == ZYNQMP_DP_AUX_REPLY_CODE_AUX_ACK ||
 989              reg == ZYNQMP_DP_AUX_REPLY_CODE_I2C_ACK)) {
 990                 reg = zynqmp_dp_read(dp, ZYNQMP_DP_REPLY_DATA_COUNT);
 991                 if ((reg & ZYNQMP_DP_REPLY_DATA_COUNT_MASK) != bytes)
 992                         return -EIO;
 993
 994                 for (i = 0; i < bytes; i++)
 995                         buf[i] = zynqmp_dp_read(dp, ZYNQMP_DP_AUX_REPLY_DATA);
 996         }
 997
 998         return 0;
 999 }
1000
1001 static ssize_t
1002 zynqmp_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1003 {
1004         struct zynqmp_dp *dp = container_of(aux, struct zynqmp_dp, aux);
1005         int ret;
1006         unsigned int i, iter;
1007
1008         /* Number of loops = timeout in msec / aux delay (400 usec) */
1009         iter = zynqmp_dp_aux_timeout_ms * 1000 / 400;
1010         iter = iter ? iter : 1;
1011
1012         for (i = 0; i < iter; i++) {
1013                 ret = zynqmp_dp_aux_cmd_submit(dp, msg->request, msg->address,
1014                                                msg->buffer, msg->size,
1015                                                &msg->reply);
1016                 if (!ret) {
1017                         dev_dbg(dp->dev, "aux %d retries\n", i);
1018                         return msg->size;
1019                 }
1020
1021                 if (dp->status == connector_status_disconnected) {
1022                         dev_dbg(dp->dev, "no connected aux device\n");
1023                         return -ENODEV;
1024                 }
1025
1026                 usleep_range(400, 500);
1027         }
1028
1029         dev_dbg(dp->dev, "failed to do aux transfer (%d)\n", ret);
1030
1031         return ret;
1032 }
1033
1034 /**
1035  * zynqmp_dp_aux_init - Initialize and register the DP AUX
1036  * @dp: DisplayPort IP core structure
1037  *
1038  * Program the AUX clock divider and filter and register the DP AUX adapter.
1039  *
1040  * Return: 0 on success, error value otherwise
1041  */
1042 static int zynqmp_dp_aux_init(struct zynqmp_dp *dp)
1043 {
1044         unsigned long rate;
1045         unsigned int w;
1046
1047         /*
1048          * The AUX_SIGNAL_WIDTH_FILTER is the number of APB clock cycles
1049          * corresponding to the AUX pulse. Allowable values are 8, 16, 24, 32,
1050          * 40 and 48. The AUX pulse width must be between 0.4µs and 0.6µs,
1051          * compute the w / 8 value corresponding to 0.4µs rounded up, and make
1052          * sure it stays below 0.6µs and within the allowable values.
1053          */
1054         rate = clk_get_rate(dp->dpsub->apb_clk);
1055         w = DIV_ROUND_UP(4 * rate, 1000 * 1000 * 10 * 8) * 8;
1056         if (w > 6 * rate / (1000 * 1000 * 10) || w > 48) {
1057                 dev_err(dp->dev, "aclk frequency too high\n");
1058                 return -EINVAL;
1059         }
1060
1061         zynqmp_dp_write(dp, ZYNQMP_DP_AUX_CLK_DIVIDER,
1062                         (w << ZYNQMP_DP_AUX_CLK_DIVIDER_AUX_FILTER_SHIFT) |
1063                         (rate / (1000 * 1000)));
1064
1065         dp->aux.name = "ZynqMP DP AUX";
1066         dp->aux.dev = dp->dev;
1067         dp->aux.drm_dev = dp->drm;
1068         dp->aux.transfer = zynqmp_dp_aux_transfer;
1069
1070         return drm_dp_aux_register(&dp->aux);
1071 }
1072
1073 /**
1074  * zynqmp_dp_aux_cleanup - Cleanup the DP AUX
1075  * @dp: DisplayPort IP core structure
1076  *
1077  * Unregister the DP AUX adapter.
1078  */
1079 static void zynqmp_dp_aux_cleanup(struct zynqmp_dp *dp)
1080 {
1081         drm_dp_aux_unregister(&dp->aux);
1082 }
1083
1084 /* -----------------------------------------------------------------------------
1085  * DisplayPort Generic Support
1086  */
1087
1088 /**
1089  * zynqmp_dp_update_misc - Write the misc registers
1090  * @dp: DisplayPort IP core structure
1091  *
1092  * The misc register values are stored in the structure, and this
1093  * function applies the values into the registers.
1094  */
1095 static void zynqmp_dp_update_misc(struct zynqmp_dp *dp)
1096 {
1097         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC0, dp->config.misc0);
1098         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC1, dp->config.misc1);
1099 }
1100
1101 /**
1102  * zynqmp_dp_set_format - Set the input format
1103  * @dp: DisplayPort IP core structure
1104  * @format: input format
1105  * @bpc: bits per component
1106  *
1107  * Update misc register values based on input @format and @bpc.
1108  *
1109  * Return: 0 on success, or -EINVAL.
1110  */
1111 static int zynqmp_dp_set_format(struct zynqmp_dp *dp,
1112                                 enum zynqmp_dpsub_format format,
1113                                 unsigned int bpc)
1114 {
1115         static const struct drm_display_info *display;
1116         struct zynqmp_dp_config *config = &dp->config;
1117         unsigned int num_colors;
1118
1119         config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK;
1120         config->misc1 &= ~ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN;
1121
1122         switch (format) {
1123         case ZYNQMP_DPSUB_FORMAT_RGB:
1124                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB;
1125                 num_colors = 3;
1126                 break;
1127
1128         case ZYNQMP_DPSUB_FORMAT_YCRCB444:
1129                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444;
1130                 num_colors = 3;
1131                 break;
1132
1133         case ZYNQMP_DPSUB_FORMAT_YCRCB422:
1134                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422;
1135                 num_colors = 2;
1136                 break;
1137
1138         case ZYNQMP_DPSUB_FORMAT_YONLY:
1139                 config->misc1 |= ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN;
1140                 num_colors = 1;
1141                 break;
1142
1143         default:
1144                 dev_err(dp->dev, "Invalid colormetry in DT\n");
1145                 return -EINVAL;
1146         }
1147
1148         display = &dp->connector.display_info;
1149         if (display->bpc && bpc > display->bpc) {
1150                 dev_warn(dp->dev,
1151                          "downgrading requested %ubpc to display limit %ubpc\n",
1152                          bpc, display->bpc);
1153                 bpc = display->bpc;
1154         }
1155
1156         config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK;
1157
1158         switch (bpc) {
1159         case 6:
1160                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6;
1161                 break;
1162         case 8:
1163                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8;
1164                 break;
1165         case 10:
1166                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10;
1167                 break;
1168         case 12:
1169                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12;
1170                 break;
1171         case 16:
1172                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16;
1173                 break;
1174         default:
1175                 dev_warn(dp->dev, "Not supported bpc (%u). fall back to 8bpc\n",
1176                          bpc);
1177                 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8;
1178                 bpc = 8;
1179                 break;
1180         }
1181
1182         /* Update the current bpp based on the format. */
1183         config->bpp = bpc * num_colors;
1184
1185         return 0;
1186 }
1187
1188 /**
1189  * zynqmp_dp_encoder_mode_set_transfer_unit - Set the transfer unit values
1190  * @dp: DisplayPort IP core structure
1191  * @mode: requested display mode
1192  *
1193  * Set the transfer unit, and calculate all transfer unit size related values.
1194  * Calculation is based on DP and IP core specification.
1195  */
1196 static void
1197 zynqmp_dp_encoder_mode_set_transfer_unit(struct zynqmp_dp *dp,
1198                                          struct drm_display_mode *mode)
1199 {
1200         u32 tu = ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE_TU_SIZE_DEF;
1201         u32 bw, vid_kbytes, avg_bytes_per_tu, init_wait;
1202
1203         /* Use the max transfer unit size (default) */
1204         zynqmp_dp_write(dp, ZYNQMP_DP_MSA_TRANSFER_UNIT_SIZE, tu);
1205
1206         vid_kbytes = mode->clock * (dp->config.bpp / 8);
1207         bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1208         avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000);
1209         zynqmp_dp_write(dp, ZYNQMP_DP_MIN_BYTES_PER_TU,
1210                         avg_bytes_per_tu / 1000);
1211         zynqmp_dp_write(dp, ZYNQMP_DP_FRAC_BYTES_PER_TU,
1212                         avg_bytes_per_tu % 1000);
1213
1214         /* Configure the initial wait cycle based on transfer unit size */
1215         if (tu < (avg_bytes_per_tu / 1000))
1216                 init_wait = 0;
1217         else if ((avg_bytes_per_tu / 1000) <= 4)
1218                 init_wait = tu;
1219         else
1220                 init_wait = tu - avg_bytes_per_tu / 1000;
1221
1222         zynqmp_dp_write(dp, ZYNQMP_DP_INIT_WAIT, init_wait);
1223 }
1224
1225 /**
1226  * zynqmp_dp_encoder_mode_set_stream - Configure the main stream
1227  * @dp: DisplayPort IP core structure
1228  * @mode: requested display mode
1229  *
1230  * Configure the main stream based on the requested mode @mode. Calculation is
1231  * based on IP core specification.
1232  */
1233 static void zynqmp_dp_encoder_mode_set_stream(struct zynqmp_dp *dp,
1234                                               const struct drm_display_mode *mode)
1235 {
1236         u8 lane_cnt = dp->mode.lane_cnt;
1237         u32 reg, wpl;
1238         unsigned int rate;
1239
1240         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HTOTAL, mode->htotal);
1241         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VTOTAL, mode->vtotal);
1242         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_POLARITY,
1243                         (!!(mode->flags & DRM_MODE_FLAG_PVSYNC) <<
1244                          ZYNQMP_DP_MAIN_STREAM_POLARITY_VSYNC_SHIFT) |
1245                         (!!(mode->flags & DRM_MODE_FLAG_PHSYNC) <<
1246                          ZYNQMP_DP_MAIN_STREAM_POLARITY_HSYNC_SHIFT));
1247         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSWIDTH,
1248                         mode->hsync_end - mode->hsync_start);
1249         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSWIDTH,
1250                         mode->vsync_end - mode->vsync_start);
1251         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HRES, mode->hdisplay);
1252         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VRES, mode->vdisplay);
1253         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HSTART,
1254                         mode->htotal - mode->hsync_start);
1255         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VSTART,
1256                         mode->vtotal - mode->vsync_start);
1257
1258         /* In synchronous mode, set the diviers */
1259         if (dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK) {
1260                 reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1261                 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_N_VID, reg);
1262                 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_M_VID, mode->clock);
1263                 rate = zynqmp_disp_get_audio_clk_rate(dp->dpsub->disp);
1264                 if (rate) {
1265                         dev_dbg(dp->dev, "Audio rate: %d\n", rate / 512);
1266                         zynqmp_dp_write(dp, ZYNQMP_DP_TX_N_AUD, reg);
1267                         zynqmp_dp_write(dp, ZYNQMP_DP_TX_M_AUD, rate / 1000);
1268                 }
1269         }
1270
1271         /* Only 2 channel audio is supported now */
1272         if (zynqmp_disp_audio_enabled(dp->dpsub->disp))
1273                 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CHANNELS, 1);
1274
1275         zynqmp_dp_write(dp, ZYNQMP_DP_USER_PIX_WIDTH, 1);
1276
1277         /* Translate to the native 16 bit datapath based on IP core spec */
1278         wpl = (mode->hdisplay * dp->config.bpp + 15) / 16;
1279         reg = wpl + wpl % lane_cnt - lane_cnt;
1280         zynqmp_dp_write(dp, ZYNQMP_DP_USER_DATA_COUNT_PER_LANE, reg);
1281 }
1282
1283 /* -----------------------------------------------------------------------------
1284  * DRM Connector
1285  */
1286
1287 static enum drm_connector_status
1288 zynqmp_dp_connector_detect(struct drm_connector *connector, bool force)
1289 {
1290         struct zynqmp_dp *dp = connector_to_dp(connector);
1291         struct zynqmp_dp_link_config *link_config = &dp->link_config;
1292         u32 state, i;
1293         int ret;
1294
1295         /*
1296          * This is from heuristic. It takes some delay (ex, 100 ~ 500 msec) to
1297          * get the HPD signal with some monitors.
1298          */
1299         for (i = 0; i < 10; i++) {
1300                 state = zynqmp_dp_read(dp, ZYNQMP_DP_INTERRUPT_SIGNAL_STATE);
1301                 if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD)
1302                         break;
1303                 msleep(100);
1304         }
1305
1306         if (state & ZYNQMP_DP_INTERRUPT_SIGNAL_STATE_HPD) {
1307                 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd,
1308                                        sizeof(dp->dpcd));
1309                 if (ret < 0) {
1310                         dev_dbg(dp->dev, "DPCD read failed");
1311                         goto disconnected;
1312                 }
1313
1314                 link_config->max_rate = min_t(int,
1315                                               drm_dp_max_link_rate(dp->dpcd),
1316                                               DP_HIGH_BIT_RATE2);
1317                 link_config->max_lanes = min_t(u8,
1318                                                drm_dp_max_lane_count(dp->dpcd),
1319                                                dp->num_lanes);
1320
1321                 dp->status = connector_status_connected;
1322                 return connector_status_connected;
1323         }
1324
1325 disconnected:
1326         dp->status = connector_status_disconnected;
1327         return connector_status_disconnected;
1328 }
1329
1330 static int zynqmp_dp_connector_get_modes(struct drm_connector *connector)
1331 {
1332         struct zynqmp_dp *dp = connector_to_dp(connector);
1333         struct edid *edid;
1334         int ret;
1335
1336         edid = drm_get_edid(connector, &dp->aux.ddc);
1337         if (!edid)
1338                 return 0;
1339
1340         drm_connector_update_edid_property(connector, edid);
1341         ret = drm_add_edid_modes(connector, edid);
1342         kfree(edid);
1343
1344         return ret;
1345 }
1346
1347 static struct drm_encoder *
1348 zynqmp_dp_connector_best_encoder(struct drm_connector *connector)
1349 {
1350         struct zynqmp_dp *dp = connector_to_dp(connector);
1351
1352         return &dp->encoder;
1353 }
1354
1355 static int zynqmp_dp_connector_mode_valid(struct drm_connector *connector,
1356                                           struct drm_display_mode *mode)
1357 {
1358         struct zynqmp_dp *dp = connector_to_dp(connector);
1359         u8 max_lanes = dp->link_config.max_lanes;
1360         u8 bpp = dp->config.bpp;
1361         int max_rate = dp->link_config.max_rate;
1362         int rate;
1363
1364         if (mode->clock > ZYNQMP_MAX_FREQ) {
1365                 dev_dbg(dp->dev, "filtered the mode, %s,for high pixel rate\n",
1366                         mode->name);
1367                 drm_mode_debug_printmodeline(mode);
1368                 return MODE_CLOCK_HIGH;
1369         }
1370
1371         /* Check with link rate and lane count */
1372         rate = zynqmp_dp_max_rate(max_rate, max_lanes, bpp);
1373         if (mode->clock > rate) {
1374                 dev_dbg(dp->dev, "filtered the mode, %s,for high pixel rate\n",
1375                         mode->name);
1376                 drm_mode_debug_printmodeline(mode);
1377                 return MODE_CLOCK_HIGH;
1378         }
1379
1380         return MODE_OK;
1381 }
1382
1383 static const struct drm_connector_funcs zynqmp_dp_connector_funcs = {
1384         .detect                 = zynqmp_dp_connector_detect,
1385         .fill_modes             = drm_helper_probe_single_connector_modes,
1386         .destroy                = drm_connector_cleanup,
1387         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1388         .atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
1389         .reset                  = drm_atomic_helper_connector_reset,
1390 };
1391
1392 static const struct drm_connector_helper_funcs
1393 zynqmp_dp_connector_helper_funcs = {
1394         .get_modes      = zynqmp_dp_connector_get_modes,
1395         .best_encoder   = zynqmp_dp_connector_best_encoder,
1396         .mode_valid     = zynqmp_dp_connector_mode_valid,
1397 };
1398
1399 /* -----------------------------------------------------------------------------
1400  * DRM Encoder
1401  */
1402
1403 static void zynqmp_dp_encoder_enable(struct drm_encoder *encoder)
1404 {
1405         struct zynqmp_dp *dp = encoder_to_dp(encoder);
1406         unsigned int i;
1407         int ret = 0;
1408
1409         pm_runtime_get_sync(dp->dev);
1410         dp->enabled = true;
1411         zynqmp_dp_update_misc(dp);
1412         if (zynqmp_disp_audio_enabled(dp->dpsub->disp))
1413                 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 1);
1414         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN, 0);
1415         if (dp->status == connector_status_connected) {
1416                 for (i = 0; i < 3; i++) {
1417                         ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER,
1418                                                  DP_SET_POWER_D0);
1419                         if (ret == 1)
1420                                 break;
1421                         usleep_range(300, 500);
1422                 }
1423                 /* Some monitors take time to wake up properly */
1424                 msleep(zynqmp_dp_power_on_delay_ms);
1425         }
1426         if (ret != 1)
1427                 dev_dbg(dp->dev, "DP aux failed\n");
1428         else
1429                 zynqmp_dp_train_loop(dp);
1430         zynqmp_dp_write(dp, ZYNQMP_DP_SOFTWARE_RESET,
1431                         ZYNQMP_DP_SOFTWARE_RESET_ALL);
1432         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 1);
1433 }
1434
1435 static void zynqmp_dp_encoder_disable(struct drm_encoder *encoder)
1436 {
1437         struct zynqmp_dp *dp = encoder_to_dp(encoder);
1438
1439         dp->enabled = false;
1440         cancel_delayed_work(&dp->hpd_work);
1441         zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_ENABLE, 0);
1442         drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3);
1443         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN,
1444                         ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL);
1445         if (zynqmp_disp_audio_enabled(dp->dpsub->disp))
1446                 zynqmp_dp_write(dp, ZYNQMP_DP_TX_AUDIO_CONTROL, 0);
1447         pm_runtime_put_sync(dp->dev);
1448 }
1449
1450 static void
1451 zynqmp_dp_encoder_atomic_mode_set(struct drm_encoder *encoder,
1452                                   struct drm_crtc_state *crtc_state,
1453                                   struct drm_connector_state *connector_state)
1454 {
1455         struct zynqmp_dp *dp = encoder_to_dp(encoder);
1456         struct drm_display_mode *mode = &crtc_state->mode;
1457         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1458         u8 max_lanes = dp->link_config.max_lanes;
1459         u8 bpp = dp->config.bpp;
1460         int rate, max_rate = dp->link_config.max_rate;
1461         int ret;
1462
1463         zynqmp_dp_set_format(dp, ZYNQMP_DPSUB_FORMAT_RGB, 8);
1464
1465         /* Check again as bpp or format might have been chagned */
1466         rate = zynqmp_dp_max_rate(max_rate, max_lanes, bpp);
1467         if (mode->clock > rate) {
1468                 dev_err(dp->dev, "the mode, %s,has too high pixel rate\n",
1469                         mode->name);
1470                 drm_mode_debug_printmodeline(mode);
1471         }
1472
1473         ret = zynqmp_dp_mode_configure(dp, adjusted_mode->clock, 0);
1474         if (ret < 0)
1475                 return;
1476
1477         zynqmp_dp_encoder_mode_set_transfer_unit(dp, adjusted_mode);
1478         zynqmp_dp_encoder_mode_set_stream(dp, adjusted_mode);
1479 }
1480
1481 #define ZYNQMP_DP_MIN_H_BACKPORCH       20
1482
1483 static int
1484 zynqmp_dp_encoder_atomic_check(struct drm_encoder *encoder,
1485                                struct drm_crtc_state *crtc_state,
1486                                struct drm_connector_state *conn_state)
1487 {
1488         struct drm_display_mode *mode = &crtc_state->mode;
1489         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1490         int diff = mode->htotal - mode->hsync_end;
1491
1492         /*
1493          * ZynqMP DP requires horizontal backporch to be greater than 12.
1494          * This limitation may not be compatible with the sink device.
1495          */
1496         if (diff < ZYNQMP_DP_MIN_H_BACKPORCH) {
1497                 int vrefresh = (adjusted_mode->clock * 1000) /
1498                                (adjusted_mode->vtotal * adjusted_mode->htotal);
1499
1500                 dev_dbg(encoder->dev->dev, "hbackporch adjusted: %d to %d",
1501                         diff, ZYNQMP_DP_MIN_H_BACKPORCH - diff);
1502                 diff = ZYNQMP_DP_MIN_H_BACKPORCH - diff;
1503                 adjusted_mode->htotal += diff;
1504                 adjusted_mode->clock = adjusted_mode->vtotal *
1505                                        adjusted_mode->htotal * vrefresh / 1000;
1506         }
1507
1508         return 0;
1509 }
1510
1511 static const struct drm_encoder_helper_funcs zynqmp_dp_encoder_helper_funcs = {
1512         .enable                 = zynqmp_dp_encoder_enable,
1513         .disable                = zynqmp_dp_encoder_disable,
1514         .atomic_mode_set        = zynqmp_dp_encoder_atomic_mode_set,
1515         .atomic_check           = zynqmp_dp_encoder_atomic_check,
1516 };
1517
1518 /* -----------------------------------------------------------------------------
1519  * Interrupt Handling
1520  */
1521
1522 /**
1523  * zynqmp_dp_enable_vblank - Enable vblank
1524  * @dp: DisplayPort IP core structure
1525  *
1526  * Enable vblank interrupt
1527  */
1528 void zynqmp_dp_enable_vblank(struct zynqmp_dp *dp)
1529 {
1530         zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_VBLANK_START);
1531 }
1532
1533 /**
1534  * zynqmp_dp_disable_vblank - Disable vblank
1535  * @dp: DisplayPort IP core structure
1536  *
1537  * Disable vblank interrupt
1538  */
1539 void zynqmp_dp_disable_vblank(struct zynqmp_dp *dp)
1540 {
1541         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_VBLANK_START);
1542 }
1543
1544 static void zynqmp_dp_hpd_work_func(struct work_struct *work)
1545 {
1546         struct zynqmp_dp *dp;
1547
1548         dp = container_of(work, struct zynqmp_dp, hpd_work.work);
1549
1550         if (dp->drm)
1551                 drm_helper_hpd_irq_event(dp->drm);
1552 }
1553
1554 static irqreturn_t zynqmp_dp_irq_handler(int irq, void *data)
1555 {
1556         struct zynqmp_dp *dp = (struct zynqmp_dp *)data;
1557         u32 status, mask;
1558
1559         status = zynqmp_dp_read(dp, ZYNQMP_DP_INT_STATUS);
1560         mask = zynqmp_dp_read(dp, ZYNQMP_DP_INT_MASK);
1561         if (!(status & ~mask))
1562                 return IRQ_NONE;
1563
1564         /* dbg for diagnostic, but not much that the driver can do */
1565         if (status & ZYNQMP_DP_INT_CHBUF_UNDERFLW_MASK)
1566                 dev_dbg_ratelimited(dp->dev, "underflow interrupt\n");
1567         if (status & ZYNQMP_DP_INT_CHBUF_OVERFLW_MASK)
1568                 dev_dbg_ratelimited(dp->dev, "overflow interrupt\n");
1569
1570         zynqmp_dp_write(dp, ZYNQMP_DP_INT_STATUS, status);
1571
1572         if (status & ZYNQMP_DP_INT_VBLANK_START)
1573                 zynqmp_disp_handle_vblank(dp->dpsub->disp);
1574
1575         if (status & ZYNQMP_DP_INT_HPD_EVENT)
1576                 schedule_delayed_work(&dp->hpd_work, 0);
1577
1578         if (status & ZYNQMP_DP_INT_HPD_IRQ) {
1579                 int ret;
1580                 u8 status[DP_LINK_STATUS_SIZE + 2];
1581
1582                 ret = drm_dp_dpcd_read(&dp->aux, DP_SINK_COUNT, status,
1583                                        DP_LINK_STATUS_SIZE + 2);
1584                 if (ret < 0)
1585                         goto handled;
1586
1587                 if (status[4] & DP_LINK_STATUS_UPDATED ||
1588                     !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) ||
1589                     !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) {
1590                         zynqmp_dp_train_loop(dp);
1591                 }
1592         }
1593
1594 handled:
1595         return IRQ_HANDLED;
1596 }
1597
1598 /* -----------------------------------------------------------------------------
1599  * Initialization & Cleanup
1600  */
1601
1602 int zynqmp_dp_drm_init(struct zynqmp_dpsub *dpsub)
1603 {
1604         struct zynqmp_dp *dp = dpsub->dp;
1605         struct drm_encoder *encoder = &dp->encoder;
1606         struct drm_connector *connector = &dp->connector;
1607         int ret;
1608
1609         dp->config.misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK;
1610         zynqmp_dp_set_format(dp, ZYNQMP_DPSUB_FORMAT_RGB, 8);
1611
1612         /* Create the DRM encoder and connector. */
1613         encoder->possible_crtcs |= zynqmp_disp_get_crtc_mask(dpsub->disp);
1614         drm_simple_encoder_init(dp->drm, encoder, DRM_MODE_ENCODER_TMDS);
1615         drm_encoder_helper_add(encoder, &zynqmp_dp_encoder_helper_funcs);
1616
1617         connector->polled = DRM_CONNECTOR_POLL_HPD;
1618         ret = drm_connector_init(encoder->dev, connector,
1619                                  &zynqmp_dp_connector_funcs,
1620                                  DRM_MODE_CONNECTOR_DisplayPort);
1621         if (ret) {
1622                 dev_err(dp->dev, "failed to create the DRM connector\n");
1623                 return ret;
1624         }
1625
1626         drm_connector_helper_add(connector, &zynqmp_dp_connector_helper_funcs);
1627         drm_connector_register(connector);
1628         drm_connector_attach_encoder(connector, encoder);
1629
1630         /* Initialize and register the AUX adapter. */
1631         ret = zynqmp_dp_aux_init(dp);
1632         if (ret) {
1633                 dev_err(dp->dev, "failed to initialize DP aux\n");
1634                 return ret;
1635         }
1636
1637         /* Now that initialisation is complete, enable interrupts. */
1638         zynqmp_dp_write(dp, ZYNQMP_DP_INT_EN, ZYNQMP_DP_INT_ALL);
1639
1640         return 0;
1641 }
1642
1643 int zynqmp_dp_probe(struct zynqmp_dpsub *dpsub, struct drm_device *drm)
1644 {
1645         struct platform_device *pdev = to_platform_device(dpsub->dev);
1646         struct zynqmp_dp *dp;
1647         struct resource *res;
1648         int ret;
1649
1650         dp = drmm_kzalloc(drm, sizeof(*dp), GFP_KERNEL);
1651         if (!dp)
1652                 return -ENOMEM;
1653
1654         dp->dev = &pdev->dev;
1655         dp->dpsub = dpsub;
1656         dp->status = connector_status_disconnected;
1657         dp->drm = drm;
1658
1659         INIT_DELAYED_WORK(&dp->hpd_work, zynqmp_dp_hpd_work_func);
1660
1661         dpsub->dp = dp;
1662
1663         /* Acquire all resources (IOMEM, IRQ and PHYs). */
1664         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dp");
1665         dp->iomem = devm_ioremap_resource(dp->dev, res);
1666         if (IS_ERR(dp->iomem))
1667                 return PTR_ERR(dp->iomem);
1668
1669         dp->irq = platform_get_irq(pdev, 0);
1670         if (dp->irq < 0)
1671                 return dp->irq;
1672
1673         dp->reset = devm_reset_control_get(dp->dev, NULL);
1674         if (IS_ERR(dp->reset)) {
1675                 if (PTR_ERR(dp->reset) != -EPROBE_DEFER)
1676                         dev_err(dp->dev, "failed to get reset: %ld\n",
1677                                 PTR_ERR(dp->reset));
1678                 return PTR_ERR(dp->reset);
1679         }
1680
1681         ret = zynqmp_dp_reset(dp, false);
1682         if (ret < 0)
1683                 return ret;
1684
1685         ret = zynqmp_dp_phy_probe(dp);
1686         if (ret)
1687                 goto err_reset;
1688
1689         /* Initialize the hardware. */
1690         zynqmp_dp_write(dp, ZYNQMP_DP_TX_PHY_POWER_DOWN,
1691                         ZYNQMP_DP_TX_PHY_POWER_DOWN_ALL);
1692         zynqmp_dp_set(dp, ZYNQMP_DP_PHY_RESET, ZYNQMP_DP_PHY_RESET_ALL_RESET);
1693         zynqmp_dp_write(dp, ZYNQMP_DP_FORCE_SCRAMBLER_RESET, 1);
1694         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0);
1695         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff);
1696
1697         ret = zynqmp_dp_phy_init(dp);
1698         if (ret)
1699                 goto err_reset;
1700
1701         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 1);
1702
1703         /*
1704          * Now that the hardware is initialized and won't generate spurious
1705          * interrupts, request the IRQ.
1706          */
1707         ret = devm_request_threaded_irq(dp->dev, dp->irq, NULL,
1708                                         zynqmp_dp_irq_handler, IRQF_ONESHOT,
1709                                         dev_name(dp->dev), dp);
1710         if (ret < 0)
1711                 goto err_phy_exit;
1712
1713         dev_dbg(dp->dev, "ZynqMP DisplayPort Tx probed with %u lanes\n",
1714                 dp->num_lanes);
1715
1716         return 0;
1717
1718 err_phy_exit:
1719         zynqmp_dp_phy_exit(dp);
1720 err_reset:
1721         zynqmp_dp_reset(dp, true);
1722
1723         return ret;
1724 }
1725
1726 void zynqmp_dp_remove(struct zynqmp_dpsub *dpsub)
1727 {
1728         struct zynqmp_dp *dp = dpsub->dp;
1729
1730         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, ZYNQMP_DP_INT_ALL);
1731         disable_irq(dp->irq);
1732
1733         cancel_delayed_work_sync(&dp->hpd_work);
1734         zynqmp_dp_aux_cleanup(dp);
1735
1736         zynqmp_dp_write(dp, ZYNQMP_DP_TRANSMITTER_ENABLE, 0);
1737         zynqmp_dp_write(dp, ZYNQMP_DP_INT_DS, 0xffffffff);
1738
1739         zynqmp_dp_phy_exit(dp);
1740         zynqmp_dp_reset(dp, true);
1741 }