drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27 #include <linux/module.h>
  28
  29 #include <drm/drmP.h>
  30 #include "vmwgfx_drv.h"
  31 #include <drm/ttm/ttm_placement.h>
  32 #include <drm/ttm/ttm_bo_driver.h>
  33 #include <drm/ttm/ttm_object.h>
  34 #include <drm/ttm/ttm_module.h>
  35 #include <linux/dma_remapping.h>
  36
  37 #define VMWGFX_DRIVER_NAME "vmwgfx"
  38 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  39 #define VMWGFX_CHIP_SVGAII 0
  40 #define VMW_FB_RESERVATION 0
  41
  42 #define VMW_MIN_INITIAL_WIDTH 800
  43 #define VMW_MIN_INITIAL_HEIGHT 600
  44
  45
  46 /**
  47  * Fully encoded drm commands. Might move to vmw_drm.h
  48  */
  49
  50 #define DRM_IOCTL_VMW_GET_PARAM                                 \
  51         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
  52                  struct drm_vmw_getparam_arg)
  53 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
  54         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
  55                 union drm_vmw_alloc_dmabuf_arg)
  56 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
  57         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
  58                 struct drm_vmw_unref_dmabuf_arg)
  59 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
  60         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
  61                  struct drm_vmw_cursor_bypass_arg)
  62
  63 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
  64         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
  65                  struct drm_vmw_control_stream_arg)
  66 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
  67         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
  68                  struct drm_vmw_stream_arg)
  69 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
  70         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
  71                  struct drm_vmw_stream_arg)
  72
  73 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
  74         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
  75                 struct drm_vmw_context_arg)
  76 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
  77         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
  78                 struct drm_vmw_context_arg)
  79 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
  80         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
  81                  union drm_vmw_surface_create_arg)
  82 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
  83         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
  84                  struct drm_vmw_surface_arg)
  85 #define DRM_IOCTL_VMW_REF_SURFACE                               \
  86         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
  87                  union drm_vmw_surface_reference_arg)
  88 #define DRM_IOCTL_VMW_EXECBUF                                   \
  89         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
  90                 struct drm_vmw_execbuf_arg)
  91 #define DRM_IOCTL_VMW_GET_3D_CAP                                \
  92         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
  93                  struct drm_vmw_get_3d_cap_arg)
  94 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
  95         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
  96                  struct drm_vmw_fence_wait_arg)
  97 #define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
  98         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
  99                  struct drm_vmw_fence_signaled_arg)
 100 #define DRM_IOCTL_VMW_FENCE_UNREF                               \
 101         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
 102                  struct drm_vmw_fence_arg)
 103 #define DRM_IOCTL_VMW_FENCE_EVENT                               \
 104         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,         \
 105                  struct drm_vmw_fence_event_arg)
 106 #define DRM_IOCTL_VMW_PRESENT                                   \
 107         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,             \
 108                  struct drm_vmw_present_arg)
 109 #define DRM_IOCTL_VMW_PRESENT_READBACK                          \
 110         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,    \
 111                  struct drm_vmw_present_readback_arg)
 112 #define DRM_IOCTL_VMW_UPDATE_LAYOUT                             \
 113         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,       \
 114                  struct drm_vmw_update_layout_arg)
 115 #define DRM_IOCTL_VMW_CREATE_SHADER                             \
 116         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER,      \
 117                  struct drm_vmw_shader_create_arg)
 118 #define DRM_IOCTL_VMW_UNREF_SHADER                              \
 119         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER,        \
 120                  struct drm_vmw_shader_arg)
 121 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE                         \
 122         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE,  \
 123                  union drm_vmw_gb_surface_create_arg)
 124 #define DRM_IOCTL_VMW_GB_SURFACE_REF                            \
 125         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF,     \
 126                  union drm_vmw_gb_surface_reference_arg)
 127 #define DRM_IOCTL_VMW_SYNCCPU                                   \
 128         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU,             \
 129                  struct drm_vmw_synccpu_arg)
 130
 131 /**
 132  * The core DRM version of this macro doesn't account for
 133  * DRM_COMMAND_BASE.
 134  */
 135
 136 #define VMW_IOCTL_DEF(ioctl, func, flags) \
 137   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
 138
 139 /**
 140  * Ioctl definitions.
 141  */
 142
 143 static const struct drm_ioctl_desc vmw_ioctls[] = {
 144         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
 145                       DRM_AUTH | DRM_UNLOCKED),
 146         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
 147                       DRM_AUTH | DRM_UNLOCKED),
 148         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
 149                       DRM_AUTH | DRM_UNLOCKED),
 150         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
 151                       vmw_kms_cursor_bypass_ioctl,
 152                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 153
 154         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
 155                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 156         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
 157                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 158         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
 159                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 160
 161         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
 162                       DRM_AUTH | DRM_UNLOCKED),
 163         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
 164                       DRM_AUTH | DRM_UNLOCKED),
 165         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
 166                       DRM_AUTH | DRM_UNLOCKED),
 167         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
 168                       DRM_AUTH | DRM_UNLOCKED),
 169         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
 170                       DRM_AUTH | DRM_UNLOCKED),
 171         VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
 172                       DRM_AUTH | DRM_UNLOCKED),
 173         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
 174                       DRM_AUTH | DRM_UNLOCKED),
 175         VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
 176                       vmw_fence_obj_signaled_ioctl,
 177                       DRM_AUTH | DRM_UNLOCKED),
 178         VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
 179                       DRM_AUTH | DRM_UNLOCKED),
 180         VMW_IOCTL_DEF(VMW_FENCE_EVENT,
 181                       vmw_fence_event_ioctl,
 182                       DRM_AUTH | DRM_UNLOCKED),
 183         VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
 184                       DRM_AUTH | DRM_UNLOCKED),
 185
 186         /* these allow direct access to the framebuffers mark as master only */
 187         VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
 188                       DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
 189         VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
 190                       vmw_present_readback_ioctl,
 191                       DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
 192         VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
 193                       vmw_kms_update_layout_ioctl,
 194                       DRM_MASTER | DRM_UNLOCKED),
 195         VMW_IOCTL_DEF(VMW_CREATE_SHADER,
 196                       vmw_shader_define_ioctl,
 197                       DRM_AUTH | DRM_UNLOCKED),
 198         VMW_IOCTL_DEF(VMW_UNREF_SHADER,
 199                       vmw_shader_destroy_ioctl,
 200                       DRM_AUTH | DRM_UNLOCKED),
 201         VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
 202                       vmw_gb_surface_define_ioctl,
 203                       DRM_AUTH | DRM_UNLOCKED),
 204         VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
 205                       vmw_gb_surface_reference_ioctl,
 206                       DRM_AUTH | DRM_UNLOCKED),
 207         VMW_IOCTL_DEF(VMW_SYNCCPU,
 208                       vmw_user_dmabuf_synccpu_ioctl,
 209                       DRM_AUTH | DRM_UNLOCKED),
 210 };
 211
 212 static struct pci_device_id vmw_pci_id_list[] = {
 213         {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
 214         {0, 0, 0}
 215 };
 216 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
 217
 218 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
 219 static int vmw_force_iommu;
 220 static int vmw_restrict_iommu;
 221 static int vmw_force_coherent;
 222 static int vmw_restrict_dma_mask;
 223
 224 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
 225 static void vmw_master_init(struct vmw_master *);
 226 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 227                               void *ptr);
 228
 229 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
 230 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
 231 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
 232 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
 233 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
 234 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
 235 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
 236 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
 237 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
 238 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
 239
 240
 241 static void vmw_print_capabilities(uint32_t capabilities)
 242 {
 243         DRM_INFO("Capabilities:\n");
 244         if (capabilities & SVGA_CAP_RECT_COPY)
 245                 DRM_INFO("  Rect copy.\n");
 246         if (capabilities & SVGA_CAP_CURSOR)
 247                 DRM_INFO("  Cursor.\n");
 248         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
 249                 DRM_INFO("  Cursor bypass.\n");
 250         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
 251                 DRM_INFO("  Cursor bypass 2.\n");
 252         if (capabilities & SVGA_CAP_8BIT_EMULATION)
 253                 DRM_INFO("  8bit emulation.\n");
 254         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
 255                 DRM_INFO("  Alpha cursor.\n");
 256         if (capabilities & SVGA_CAP_3D)
 257                 DRM_INFO("  3D.\n");
 258         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
 259                 DRM_INFO("  Extended Fifo.\n");
 260         if (capabilities & SVGA_CAP_MULTIMON)
 261                 DRM_INFO("  Multimon.\n");
 262         if (capabilities & SVGA_CAP_PITCHLOCK)
 263                 DRM_INFO("  Pitchlock.\n");
 264         if (capabilities & SVGA_CAP_IRQMASK)
 265                 DRM_INFO("  Irq mask.\n");
 266         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
 267                 DRM_INFO("  Display Topology.\n");
 268         if (capabilities & SVGA_CAP_GMR)
 269                 DRM_INFO("  GMR.\n");
 270         if (capabilities & SVGA_CAP_TRACES)
 271                 DRM_INFO("  Traces.\n");
 272         if (capabilities & SVGA_CAP_GMR2)
 273                 DRM_INFO("  GMR2.\n");
 274         if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
 275                 DRM_INFO("  Screen Object 2.\n");
 276         if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
 277                 DRM_INFO("  Command Buffers.\n");
 278         if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
 279                 DRM_INFO("  Command Buffers 2.\n");
 280         if (capabilities & SVGA_CAP_GBOBJECTS)
 281                 DRM_INFO("  Guest Backed Resources.\n");
 282 }
 283
 284
 285 /**
 286  * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at
 287  * the start of a buffer object.
 288  *
 289  * @dev_priv: The device private structure.
 290  *
 291  * This function will idle the buffer using an uninterruptible wait, then
 292  * map the first page and initialize a pending occlusion query result structure,
 293  * Finally it will unmap the buffer.
 294  *
 295  * TODO: Since we're only mapping a single page, we should optimize the map
 296  * to use kmap_atomic / iomap_atomic.
 297  */
 298 static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv)
 299 {
 300         struct ttm_bo_kmap_obj map;
 301         volatile SVGA3dQueryResult *result;
 302         bool dummy;
 303         int ret;
 304         struct ttm_bo_device *bdev = &dev_priv->bdev;
 305         struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
 306
 307         ttm_bo_reserve(bo, false, false, false, 0);
 308         spin_lock(&bdev->fence_lock);
 309         ret = ttm_bo_wait(bo, false, false, false);
 310         spin_unlock(&bdev->fence_lock);
 311         if (unlikely(ret != 0))
 312                 (void) vmw_fallback_wait(dev_priv, false, true, 0, false,
 313                                          10*HZ);
 314
 315         ret = ttm_bo_kmap(bo, 0, 1, &map);
 316         if (likely(ret == 0)) {
 317                 result = ttm_kmap_obj_virtual(&map, &dummy);
 318                 result->totalSize = sizeof(*result);
 319                 result->state = SVGA3D_QUERYSTATE_PENDING;
 320                 result->result32 = 0xff;
 321                 ttm_bo_kunmap(&map);
 322         } else
 323                 DRM_ERROR("Dummy query buffer map failed.\n");
 324         ttm_bo_unreserve(bo);
 325 }
 326
 327
 328 /**
 329  * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
 330  *
 331  * @dev_priv: A device private structure.
 332  *
 333  * This function creates a small buffer object that holds the query
 334  * result for dummy queries emitted as query barriers.
 335  * No interruptible waits are done within this function.
 336  *
 337  * Returns an error if bo creation fails.
 338  */
 339 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
 340 {
 341         return ttm_bo_create(&dev_priv->bdev,
 342                              PAGE_SIZE,
 343                              ttm_bo_type_device,
 344                              &vmw_vram_sys_placement,
 345                              0, false, NULL,
 346                              &dev_priv->dummy_query_bo);
 347 }
 348
 349
 350 static int vmw_request_device(struct vmw_private *dev_priv)
 351 {
 352         int ret;
 353
 354         ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
 355         if (unlikely(ret != 0)) {
 356                 DRM_ERROR("Unable to initialize FIFO.\n");
 357                 return ret;
 358         }
 359         vmw_fence_fifo_up(dev_priv->fman);
 360         if (dev_priv->has_mob) {
 361                 ret = vmw_otables_setup(dev_priv);
 362                 if (unlikely(ret != 0)) {
 363                         DRM_ERROR("Unable to initialize "
 364                                   "guest Memory OBjects.\n");
 365                         goto out_no_mob;
 366                 }
 367         }
 368         ret = vmw_dummy_query_bo_create(dev_priv);
 369         if (unlikely(ret != 0))
 370                 goto out_no_query_bo;
 371         vmw_dummy_query_bo_prepare(dev_priv);
 372
 373         return 0;
 374
 375 out_no_query_bo:
 376         if (dev_priv->has_mob)
 377                 vmw_otables_takedown(dev_priv);
 378 out_no_mob:
 379         vmw_fence_fifo_down(dev_priv->fman);
 380         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 381         return ret;
 382 }
 383
 384 static void vmw_release_device(struct vmw_private *dev_priv)
 385 {
 386         /*
 387          * Previous destructions should've released
 388          * the pinned bo.
 389          */
 390
 391         BUG_ON(dev_priv->pinned_bo != NULL);
 392
 393         ttm_bo_unref(&dev_priv->dummy_query_bo);
 394         if (dev_priv->has_mob)
 395                 vmw_otables_takedown(dev_priv);
 396         vmw_fence_fifo_down(dev_priv->fman);
 397         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 398 }
 399
 400
 401 /**
 402  * Increase the 3d resource refcount.
 403  * If the count was prevously zero, initialize the fifo, switching to svga
 404  * mode. Note that the master holds a ref as well, and may request an
 405  * explicit switch to svga mode if fb is not running, using @unhide_svga.
 406  */
 407 int vmw_3d_resource_inc(struct vmw_private *dev_priv,
 408                         bool unhide_svga)
 409 {
 410         int ret = 0;
 411
 412         mutex_lock(&dev_priv->release_mutex);
 413         if (unlikely(dev_priv->num_3d_resources++ == 0)) {
 414                 ret = vmw_request_device(dev_priv);
 415                 if (unlikely(ret != 0))
 416                         --dev_priv->num_3d_resources;
 417         } else if (unhide_svga) {
 418                 mutex_lock(&dev_priv->hw_mutex);
 419                 vmw_write(dev_priv, SVGA_REG_ENABLE,
 420                           vmw_read(dev_priv, SVGA_REG_ENABLE) &
 421                           ~SVGA_REG_ENABLE_HIDE);
 422                 mutex_unlock(&dev_priv->hw_mutex);
 423         }
 424
 425         mutex_unlock(&dev_priv->release_mutex);
 426         return ret;
 427 }
 428
 429 /**
 430  * Decrease the 3d resource refcount.
 431  * If the count reaches zero, disable the fifo, switching to vga mode.
 432  * Note that the master holds a refcount as well, and may request an
 433  * explicit switch to vga mode when it releases its refcount to account
 434  * for the situation of an X server vt switch to VGA with 3d resources
 435  * active.
 436  */
 437 void vmw_3d_resource_dec(struct vmw_private *dev_priv,
 438                          bool hide_svga)
 439 {
 440         int32_t n3d;
 441
 442         mutex_lock(&dev_priv->release_mutex);
 443         if (unlikely(--dev_priv->num_3d_resources == 0))
 444                 vmw_release_device(dev_priv);
 445         else if (hide_svga) {
 446                 mutex_lock(&dev_priv->hw_mutex);
 447                 vmw_write(dev_priv, SVGA_REG_ENABLE,
 448                           vmw_read(dev_priv, SVGA_REG_ENABLE) |
 449                           SVGA_REG_ENABLE_HIDE);
 450                 mutex_unlock(&dev_priv->hw_mutex);
 451         }
 452
 453         n3d = (int32_t) dev_priv->num_3d_resources;
 454         mutex_unlock(&dev_priv->release_mutex);
 455
 456         BUG_ON(n3d < 0);
 457 }
 458
 459 /**
 460  * Sets the initial_[width|height] fields on the given vmw_private.
 461  *
 462  * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
 463  * clamping the value to fb_max_[width|height] fields and the
 464  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 465  * If the values appear to be invalid, set them to
 466  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 467  */
 468 static void vmw_get_initial_size(struct vmw_private *dev_priv)
 469 {
 470         uint32_t width;
 471         uint32_t height;
 472
 473         width = vmw_read(dev_priv, SVGA_REG_WIDTH);
 474         height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
 475
 476         width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
 477         height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
 478
 479         if (width > dev_priv->fb_max_width ||
 480             height > dev_priv->fb_max_height) {
 481
 482                 /*
 483                  * This is a host error and shouldn't occur.
 484                  */
 485
 486                 width = VMW_MIN_INITIAL_WIDTH;
 487                 height = VMW_MIN_INITIAL_HEIGHT;
 488         }
 489
 490         dev_priv->initial_width = width;
 491         dev_priv->initial_height = height;
 492 }
 493
 494 /**
 495  * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
 496  * system.
 497  *
 498  * @dev_priv: Pointer to a struct vmw_private
 499  *
 500  * This functions tries to determine the IOMMU setup and what actions
 501  * need to be taken by the driver to make system pages visible to the
 502  * device.
 503  * If this function decides that DMA is not possible, it returns -EINVAL.
 504  * The driver may then try to disable features of the device that require
 505  * DMA.
 506  */
 507 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
 508 {
 509         static const char *names[vmw_dma_map_max] = {
 510                 [vmw_dma_phys] = "Using physical TTM page addresses.",
 511                 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
 512                 [vmw_dma_map_populate] = "Keeping DMA mappings.",
 513                 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
 514 #ifdef CONFIG_X86
 515         const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
 516
 517 #ifdef CONFIG_INTEL_IOMMU
 518         if (intel_iommu_enabled) {
 519                 dev_priv->map_mode = vmw_dma_map_populate;
 520                 goto out_fixup;
 521         }
 522 #endif
 523
 524         if (!(vmw_force_iommu || vmw_force_coherent)) {
 525                 dev_priv->map_mode = vmw_dma_phys;
 526                 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 527                 return 0;
 528         }
 529
 530         dev_priv->map_mode = vmw_dma_map_populate;
 531
 532         if (dma_ops->sync_single_for_cpu)
 533                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 534 #ifdef CONFIG_SWIOTLB
 535         if (swiotlb_nr_tbl() == 0)
 536                 dev_priv->map_mode = vmw_dma_map_populate;
 537 #endif
 538
 539 #ifdef CONFIG_INTEL_IOMMU
 540 out_fixup:
 541 #endif
 542         if (dev_priv->map_mode == vmw_dma_map_populate &&
 543             vmw_restrict_iommu)
 544                 dev_priv->map_mode = vmw_dma_map_bind;
 545
 546         if (vmw_force_coherent)
 547                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 548
 549 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
 550         /*
 551          * No coherent page pool
 552          */
 553         if (dev_priv->map_mode == vmw_dma_alloc_coherent)
 554                 return -EINVAL;
 555 #endif
 556
 557 #else /* CONFIG_X86 */
 558         dev_priv->map_mode = vmw_dma_map_populate;
 559 #endif /* CONFIG_X86 */
 560
 561         DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 562
 563         return 0;
 564 }
 565
 566 /**
 567  * vmw_dma_masks - set required page- and dma masks
 568  *
 569  * @dev: Pointer to struct drm-device
 570  *
 571  * With 32-bit we can only handle 32 bit PFNs. Optionally set that
 572  * restriction also for 64-bit systems.
 573  */
 574 #ifdef CONFIG_INTEL_IOMMU
 575 static int vmw_dma_masks(struct vmw_private *dev_priv)
 576 {
 577         struct drm_device *dev = dev_priv->dev;
 578
 579         if (intel_iommu_enabled &&
 580             (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
 581                 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
 582                 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
 583         }
 584         return 0;
 585 }
 586 #else
 587 static int vmw_dma_masks(struct vmw_private *dev_priv)
 588 {
 589         return 0;
 590 }
 591 #endif
 592
 593 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
 594 {
 595         struct vmw_private *dev_priv;
 596         int ret;
 597         uint32_t svga_id;
 598         enum vmw_res_type i;
 599         bool refuse_dma = false;
 600
 601         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 602         if (unlikely(dev_priv == NULL)) {
 603                 DRM_ERROR("Failed allocating a device private struct.\n");
 604                 return -ENOMEM;
 605         }
 606
 607         pci_set_master(dev->pdev);
 608
 609         dev_priv->dev = dev;
 610         dev_priv->vmw_chipset = chipset;
 611         dev_priv->last_read_seqno = (uint32_t) -100;
 612         mutex_init(&dev_priv->hw_mutex);
 613         mutex_init(&dev_priv->cmdbuf_mutex);
 614         mutex_init(&dev_priv->release_mutex);
 615         rwlock_init(&dev_priv->resource_lock);
 616
 617         for (i = vmw_res_context; i < vmw_res_max; ++i) {
 618                 idr_init(&dev_priv->res_idr[i]);
 619                 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
 620         }
 621
 622         mutex_init(&dev_priv->init_mutex);
 623         init_waitqueue_head(&dev_priv->fence_queue);
 624         init_waitqueue_head(&dev_priv->fifo_queue);
 625         dev_priv->fence_queue_waiters = 0;
 626         atomic_set(&dev_priv->fifo_queue_waiters, 0);
 627
 628         dev_priv->used_memory_size = 0;
 629
 630         dev_priv->io_start = pci_resource_start(dev->pdev, 0);
 631         dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
 632         dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
 633
 634         dev_priv->enable_fb = enable_fbdev;
 635
 636         mutex_lock(&dev_priv->hw_mutex);
 637
 638         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
 639         svga_id = vmw_read(dev_priv, SVGA_REG_ID);
 640         if (svga_id != SVGA_ID_2) {
 641                 ret = -ENOSYS;
 642                 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
 643                 mutex_unlock(&dev_priv->hw_mutex);
 644                 goto out_err0;
 645         }
 646
 647         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
 648         ret = vmw_dma_select_mode(dev_priv);
 649         if (unlikely(ret != 0)) {
 650                 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
 651                 refuse_dma = true;
 652         }
 653
 654         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
 655         dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
 656         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
 657         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
 658
 659         vmw_get_initial_size(dev_priv);
 660
 661         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 662                 dev_priv->max_gmr_ids =
 663                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
 664                 dev_priv->max_gmr_pages =
 665                         vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
 666                 dev_priv->memory_size =
 667                         vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
 668                 dev_priv->memory_size -= dev_priv->vram_size;
 669         } else {
 670                 /*
 671                  * An arbitrary limit of 512MiB on surface
 672                  * memory. But all HWV8 hardware supports GMR2.
 673                  */
 674                 dev_priv->memory_size = 512*1024*1024;
 675         }
 676         dev_priv->max_mob_pages = 0;
 677         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 678                 uint64_t mem_size =
 679                         vmw_read(dev_priv,
 680                                  SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
 681
 682                 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
 683                 dev_priv->prim_bb_mem =
 684                         vmw_read(dev_priv,
 685                                  SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
 686         } else
 687                 dev_priv->prim_bb_mem = dev_priv->vram_size;
 688
 689         ret = vmw_dma_masks(dev_priv);
 690         if (unlikely(ret != 0))
 691                 goto out_err0;
 692
 693         if (unlikely(dev_priv->prim_bb_mem < dev_priv->vram_size))
 694                 dev_priv->prim_bb_mem = dev_priv->vram_size;
 695
 696         mutex_unlock(&dev_priv->hw_mutex);
 697
 698         vmw_print_capabilities(dev_priv->capabilities);
 699
 700         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 701                 DRM_INFO("Max GMR ids is %u\n",
 702                          (unsigned)dev_priv->max_gmr_ids);
 703                 DRM_INFO("Max number of GMR pages is %u\n",
 704                          (unsigned)dev_priv->max_gmr_pages);
 705                 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
 706                          (unsigned)dev_priv->memory_size / 1024);
 707         }
 708         DRM_INFO("Maximum display memory size is %u kiB\n",
 709                  dev_priv->prim_bb_mem / 1024);
 710         DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
 711                  dev_priv->vram_start, dev_priv->vram_size / 1024);
 712         DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
 713                  dev_priv->mmio_start, dev_priv->mmio_size / 1024);
 714
 715         ret = vmw_ttm_global_init(dev_priv);
 716         if (unlikely(ret != 0))
 717                 goto out_err0;
 718
 719
 720         vmw_master_init(&dev_priv->fbdev_master);
 721         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 722         dev_priv->active_master = &dev_priv->fbdev_master;
 723
 724
 725         ret = ttm_bo_device_init(&dev_priv->bdev,
 726                                  dev_priv->bo_global_ref.ref.object,
 727                                  &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
 728                                  false);
 729         if (unlikely(ret != 0)) {
 730                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
 731                 goto out_err1;
 732         }
 733
 734         ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
 735                              (dev_priv->vram_size >> PAGE_SHIFT));
 736         if (unlikely(ret != 0)) {
 737                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
 738                 goto out_err2;
 739         }
 740
 741         dev_priv->has_gmr = true;
 742         if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
 743             refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
 744                                          VMW_PL_GMR) != 0) {
 745                 DRM_INFO("No GMR memory available. "
 746                          "Graphics memory resources are very limited.\n");
 747                 dev_priv->has_gmr = false;
 748         }
 749
 750         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 751                 dev_priv->has_mob = true;
 752                 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
 753                                    VMW_PL_MOB) != 0) {
 754                         DRM_INFO("No MOB memory available. "
 755                                  "3D will be disabled.\n");
 756                         dev_priv->has_mob = false;
 757                 }
 758         }
 759
 760         dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
 761                                                dev_priv->mmio_size);
 762
 763         dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
 764                                          dev_priv->mmio_size);
 765
 766         if (unlikely(dev_priv->mmio_virt == NULL)) {
 767                 ret = -ENOMEM;
 768                 DRM_ERROR("Failed mapping MMIO.\n");
 769                 goto out_err3;
 770         }
 771
 772         /* Need mmio memory to check for fifo pitchlock cap. */
 773         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
 774             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
 775             !vmw_fifo_have_pitchlock(dev_priv)) {
 776                 ret = -ENOSYS;
 777                 DRM_ERROR("Hardware has no pitchlock\n");
 778                 goto out_err4;
 779         }
 780
 781         dev_priv->tdev = ttm_object_device_init
 782                 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
 783
 784         if (unlikely(dev_priv->tdev == NULL)) {
 785                 DRM_ERROR("Unable to initialize TTM object management.\n");
 786                 ret = -ENOMEM;
 787                 goto out_err4;
 788         }
 789
 790         dev->dev_private = dev_priv;
 791
 792         ret = pci_request_regions(dev->pdev, "vmwgfx probe");
 793         dev_priv->stealth = (ret != 0);
 794         if (dev_priv->stealth) {
 795                 /**
 796                  * Request at least the mmio PCI resource.
 797                  */
 798
 799                 DRM_INFO("It appears like vesafb is loaded. "
 800                          "Ignore above error if any.\n");
 801                 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
 802                 if (unlikely(ret != 0)) {
 803                         DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
 804                         goto out_no_device;
 805                 }
 806         }
 807
 808         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
 809                 ret = drm_irq_install(dev);
 810                 if (ret != 0) {
 811                         DRM_ERROR("Failed installing irq: %d\n", ret);
 812                         goto out_no_irq;
 813                 }
 814         }
 815
 816         dev_priv->fman = vmw_fence_manager_init(dev_priv);
 817         if (unlikely(dev_priv->fman == NULL)) {
 818                 ret = -ENOMEM;
 819                 goto out_no_fman;
 820         }
 821
 822         vmw_kms_save_vga(dev_priv);
 823
 824         /* Start kms and overlay systems, needs fifo. */
 825         ret = vmw_kms_init(dev_priv);
 826         if (unlikely(ret != 0))
 827                 goto out_no_kms;
 828         vmw_overlay_init(dev_priv);
 829
 830         if (dev_priv->enable_fb) {
 831                 ret = vmw_3d_resource_inc(dev_priv, true);
 832                 if (unlikely(ret != 0))
 833                         goto out_no_fifo;
 834                 vmw_fb_init(dev_priv);
 835         }
 836
 837         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
 838         register_pm_notifier(&dev_priv->pm_nb);
 839
 840         return 0;
 841
 842 out_no_fifo:
 843         vmw_overlay_close(dev_priv);
 844         vmw_kms_close(dev_priv);
 845 out_no_kms:
 846         vmw_kms_restore_vga(dev_priv);
 847         vmw_fence_manager_takedown(dev_priv->fman);
 848 out_no_fman:
 849         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 850                 drm_irq_uninstall(dev_priv->dev);
 851 out_no_irq:
 852         if (dev_priv->stealth)
 853                 pci_release_region(dev->pdev, 2);
 854         else
 855                 pci_release_regions(dev->pdev);
 856 out_no_device:
 857         ttm_object_device_release(&dev_priv->tdev);
 858 out_err4:
 859         iounmap(dev_priv->mmio_virt);
 860 out_err3:
 861         arch_phys_wc_del(dev_priv->mmio_mtrr);
 862         if (dev_priv->has_mob)
 863                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
 864         if (dev_priv->has_gmr)
 865                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 866         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 867 out_err2:
 868         (void)ttm_bo_device_release(&dev_priv->bdev);
 869 out_err1:
 870         vmw_ttm_global_release(dev_priv);
 871 out_err0:
 872         for (i = vmw_res_context; i < vmw_res_max; ++i)
 873                 idr_destroy(&dev_priv->res_idr[i]);
 874
 875         kfree(dev_priv);
 876         return ret;
 877 }
 878
 879 static int vmw_driver_unload(struct drm_device *dev)
 880 {
 881         struct vmw_private *dev_priv = vmw_priv(dev);
 882         enum vmw_res_type i;
 883
 884         unregister_pm_notifier(&dev_priv->pm_nb);
 885
 886         if (dev_priv->ctx.res_ht_initialized)
 887                 drm_ht_remove(&dev_priv->ctx.res_ht);
 888         if (dev_priv->ctx.cmd_bounce)
 889                 vfree(dev_priv->ctx.cmd_bounce);
 890         if (dev_priv->enable_fb) {
 891                 vmw_fb_close(dev_priv);
 892                 vmw_kms_restore_vga(dev_priv);
 893                 vmw_3d_resource_dec(dev_priv, false);
 894         }
 895         vmw_kms_close(dev_priv);
 896         vmw_overlay_close(dev_priv);
 897         vmw_fence_manager_takedown(dev_priv->fman);
 898         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 899                 drm_irq_uninstall(dev_priv->dev);
 900         if (dev_priv->stealth)
 901                 pci_release_region(dev->pdev, 2);
 902         else
 903                 pci_release_regions(dev->pdev);
 904
 905         ttm_object_device_release(&dev_priv->tdev);
 906         iounmap(dev_priv->mmio_virt);
 907         arch_phys_wc_del(dev_priv->mmio_mtrr);
 908         if (dev_priv->has_mob)
 909                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
 910         if (dev_priv->has_gmr)
 911                 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 912         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 913         (void)ttm_bo_device_release(&dev_priv->bdev);
 914         vmw_ttm_global_release(dev_priv);
 915
 916         for (i = vmw_res_context; i < vmw_res_max; ++i)
 917                 idr_destroy(&dev_priv->res_idr[i]);
 918
 919         kfree(dev_priv);
 920
 921         return 0;
 922 }
 923
 924 static void vmw_preclose(struct drm_device *dev,
 925                          struct drm_file *file_priv)
 926 {
 927         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
 928         struct vmw_private *dev_priv = vmw_priv(dev);
 929
 930         vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
 931 }
 932
 933 static void vmw_postclose(struct drm_device *dev,
 934                          struct drm_file *file_priv)
 935 {
 936         struct vmw_fpriv *vmw_fp;
 937
 938         vmw_fp = vmw_fpriv(file_priv);
 939
 940         if (vmw_fp->locked_master) {
 941                 struct vmw_master *vmaster =
 942                         vmw_master(vmw_fp->locked_master);
 943
 944                 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
 945                 ttm_vt_unlock(&vmaster->lock);
 946                 drm_master_put(&vmw_fp->locked_master);
 947         }
 948
 949         ttm_object_file_release(&vmw_fp->tfile);
 950         kfree(vmw_fp);
 951 }
 952
 953 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
 954 {
 955         struct vmw_private *dev_priv = vmw_priv(dev);
 956         struct vmw_fpriv *vmw_fp;
 957         int ret = -ENOMEM;
 958
 959         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
 960         if (unlikely(vmw_fp == NULL))
 961                 return ret;
 962
 963         INIT_LIST_HEAD(&vmw_fp->fence_events);
 964         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
 965         if (unlikely(vmw_fp->tfile == NULL))
 966                 goto out_no_tfile;
 967
 968         file_priv->driver_priv = vmw_fp;
 969         dev_priv->bdev.dev_mapping = dev->dev_mapping;
 970
 971         return 0;
 972
 973 out_no_tfile:
 974         kfree(vmw_fp);
 975         return ret;
 976 }
 977
 978 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
 979                                unsigned long arg)
 980 {
 981         struct drm_file *file_priv = filp->private_data;
 982         struct drm_device *dev = file_priv->minor->dev;
 983         unsigned int nr = DRM_IOCTL_NR(cmd);
 984
 985         /*
 986          * Do extra checking on driver private ioctls.
 987          */
 988
 989         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
 990             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
 991                 const struct drm_ioctl_desc *ioctl =
 992                     &vmw_ioctls[nr - DRM_COMMAND_BASE];
 993
 994                 if (unlikely(ioctl->cmd_drv != cmd)) {
 995                         DRM_ERROR("Invalid command format, ioctl %d\n",
 996                                   nr - DRM_COMMAND_BASE);
 997                         return -EINVAL;
 998                 }
 999         }
1000
1001         return drm_ioctl(filp, cmd, arg);
1002 }
1003
1004 static void vmw_lastclose(struct drm_device *dev)
1005 {
1006         struct drm_crtc *crtc;
1007         struct drm_mode_set set;
1008         int ret;
1009
1010         set.x = 0;
1011         set.y = 0;
1012         set.fb = NULL;
1013         set.mode = NULL;
1014         set.connectors = NULL;
1015         set.num_connectors = 0;
1016
1017         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1018                 set.crtc = crtc;
1019                 ret = drm_mode_set_config_internal(&set);
1020                 WARN_ON(ret != 0);
1021         }
1022
1023 }
1024
1025 static void vmw_master_init(struct vmw_master *vmaster)
1026 {
1027         ttm_lock_init(&vmaster->lock);
1028         INIT_LIST_HEAD(&vmaster->fb_surf);
1029         mutex_init(&vmaster->fb_surf_mutex);
1030 }
1031
1032 static int vmw_master_create(struct drm_device *dev,
1033                              struct drm_master *master)
1034 {
1035         struct vmw_master *vmaster;
1036
1037         vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1038         if (unlikely(vmaster == NULL))
1039                 return -ENOMEM;
1040
1041         vmw_master_init(vmaster);
1042         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1043         master->driver_priv = vmaster;
1044
1045         return 0;
1046 }
1047
1048 static void vmw_master_destroy(struct drm_device *dev,
1049                                struct drm_master *master)
1050 {
1051         struct vmw_master *vmaster = vmw_master(master);
1052
1053         master->driver_priv = NULL;
1054         kfree(vmaster);
1055 }
1056
1057
1058 static int vmw_master_set(struct drm_device *dev,
1059                           struct drm_file *file_priv,
1060                           bool from_open)
1061 {
1062         struct vmw_private *dev_priv = vmw_priv(dev);
1063         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1064         struct vmw_master *active = dev_priv->active_master;
1065         struct vmw_master *vmaster = vmw_master(file_priv->master);
1066         int ret = 0;
1067
1068         if (!dev_priv->enable_fb) {
1069                 ret = vmw_3d_resource_inc(dev_priv, true);
1070                 if (unlikely(ret != 0))
1071                         return ret;
1072                 vmw_kms_save_vga(dev_priv);
1073                 mutex_lock(&dev_priv->hw_mutex);
1074                 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
1075                 mutex_unlock(&dev_priv->hw_mutex);
1076         }
1077
1078         if (active) {
1079                 BUG_ON(active != &dev_priv->fbdev_master);
1080                 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1081                 if (unlikely(ret != 0))
1082                         goto out_no_active_lock;
1083
1084                 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1085                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1086                 if (unlikely(ret != 0)) {
1087                         DRM_ERROR("Unable to clean VRAM on "
1088                                   "master drop.\n");
1089                 }
1090
1091                 dev_priv->active_master = NULL;
1092         }
1093
1094         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1095         if (!from_open) {
1096                 ttm_vt_unlock(&vmaster->lock);
1097                 BUG_ON(vmw_fp->locked_master != file_priv->master);
1098                 drm_master_put(&vmw_fp->locked_master);
1099         }
1100
1101         dev_priv->active_master = vmaster;
1102
1103         return 0;
1104
1105 out_no_active_lock:
1106         if (!dev_priv->enable_fb) {
1107                 vmw_kms_restore_vga(dev_priv);
1108                 vmw_3d_resource_dec(dev_priv, true);
1109                 mutex_lock(&dev_priv->hw_mutex);
1110                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1111                 mutex_unlock(&dev_priv->hw_mutex);
1112         }
1113         return ret;
1114 }
1115
1116 static void vmw_master_drop(struct drm_device *dev,
1117                             struct drm_file *file_priv,
1118                             bool from_release)
1119 {
1120         struct vmw_private *dev_priv = vmw_priv(dev);
1121         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1122         struct vmw_master *vmaster = vmw_master(file_priv->master);
1123         int ret;
1124
1125         /**
1126          * Make sure the master doesn't disappear while we have
1127          * it locked.
1128          */
1129
1130         vmw_fp->locked_master = drm_master_get(file_priv->master);
1131         ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1132         if (unlikely((ret != 0))) {
1133                 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1134                 drm_master_put(&vmw_fp->locked_master);
1135         }
1136
1137         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1138         vmw_execbuf_release_pinned_bo(dev_priv);
1139
1140         if (!dev_priv->enable_fb) {
1141                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1142                 if (unlikely(ret != 0))
1143                         DRM_ERROR("Unable to clean VRAM on master drop.\n");
1144                 vmw_kms_restore_vga(dev_priv);
1145                 vmw_3d_resource_dec(dev_priv, true);
1146                 mutex_lock(&dev_priv->hw_mutex);
1147                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1148                 mutex_unlock(&dev_priv->hw_mutex);
1149         }
1150
1151         dev_priv->active_master = &dev_priv->fbdev_master;
1152         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1153         ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1154
1155         if (dev_priv->enable_fb)
1156                 vmw_fb_on(dev_priv);
1157 }
1158
1159
1160 static void vmw_remove(struct pci_dev *pdev)
1161 {
1162         struct drm_device *dev = pci_get_drvdata(pdev);
1163
1164         drm_put_dev(dev);
1165 }
1166
1167 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1168                               void *ptr)
1169 {
1170         struct vmw_private *dev_priv =
1171                 container_of(nb, struct vmw_private, pm_nb);
1172         struct vmw_master *vmaster = dev_priv->active_master;
1173
1174         switch (val) {
1175         case PM_HIBERNATION_PREPARE:
1176         case PM_SUSPEND_PREPARE:
1177                 ttm_suspend_lock(&vmaster->lock);
1178
1179                 /**
1180                  * This empties VRAM and unbinds all GMR bindings.
1181                  * Buffer contents is moved to swappable memory.
1182                  */
1183                 vmw_execbuf_release_pinned_bo(dev_priv);
1184                 vmw_resource_evict_all(dev_priv);
1185                 ttm_bo_swapout_all(&dev_priv->bdev);
1186
1187                 break;
1188         case PM_POST_HIBERNATION:
1189         case PM_POST_SUSPEND:
1190         case PM_POST_RESTORE:
1191                 ttm_suspend_unlock(&vmaster->lock);
1192
1193                 break;
1194         case PM_RESTORE_PREPARE:
1195                 break;
1196         default:
1197                 break;
1198         }
1199         return 0;
1200 }
1201
1202 /**
1203  * These might not be needed with the virtual SVGA device.
1204  */
1205
1206 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1207 {
1208         struct drm_device *dev = pci_get_drvdata(pdev);
1209         struct vmw_private *dev_priv = vmw_priv(dev);
1210
1211         if (dev_priv->num_3d_resources != 0) {
1212                 DRM_INFO("Can't suspend or hibernate "
1213                          "while 3D resources are active.\n");
1214                 return -EBUSY;
1215         }
1216
1217         pci_save_state(pdev);
1218         pci_disable_device(pdev);
1219         pci_set_power_state(pdev, PCI_D3hot);
1220         return 0;
1221 }
1222
1223 static int vmw_pci_resume(struct pci_dev *pdev)
1224 {
1225         pci_set_power_state(pdev, PCI_D0);
1226         pci_restore_state(pdev);
1227         return pci_enable_device(pdev);
1228 }
1229
1230 static int vmw_pm_suspend(struct device *kdev)
1231 {
1232         struct pci_dev *pdev = to_pci_dev(kdev);
1233         struct pm_message dummy;
1234
1235         dummy.event = 0;
1236
1237         return vmw_pci_suspend(pdev, dummy);
1238 }
1239
1240 static int vmw_pm_resume(struct device *kdev)
1241 {
1242         struct pci_dev *pdev = to_pci_dev(kdev);
1243
1244         return vmw_pci_resume(pdev);
1245 }
1246
1247 static int vmw_pm_prepare(struct device *kdev)
1248 {
1249         struct pci_dev *pdev = to_pci_dev(kdev);
1250         struct drm_device *dev = pci_get_drvdata(pdev);
1251         struct vmw_private *dev_priv = vmw_priv(dev);
1252
1253         /**
1254          * Release 3d reference held by fbdev and potentially
1255          * stop fifo.
1256          */
1257         dev_priv->suspended = true;
1258         if (dev_priv->enable_fb)
1259                         vmw_3d_resource_dec(dev_priv, true);
1260
1261         if (dev_priv->num_3d_resources != 0) {
1262
1263                 DRM_INFO("Can't suspend or hibernate "
1264                          "while 3D resources are active.\n");
1265
1266                 if (dev_priv->enable_fb)
1267                         vmw_3d_resource_inc(dev_priv, true);
1268                 dev_priv->suspended = false;
1269                 return -EBUSY;
1270         }
1271
1272         return 0;
1273 }
1274
1275 static void vmw_pm_complete(struct device *kdev)
1276 {
1277         struct pci_dev *pdev = to_pci_dev(kdev);
1278         struct drm_device *dev = pci_get_drvdata(pdev);
1279         struct vmw_private *dev_priv = vmw_priv(dev);
1280
1281         mutex_lock(&dev_priv->hw_mutex);
1282         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1283         (void) vmw_read(dev_priv, SVGA_REG_ID);
1284         mutex_unlock(&dev_priv->hw_mutex);
1285
1286         /**
1287          * Reclaim 3d reference held by fbdev and potentially
1288          * start fifo.
1289          */
1290         if (dev_priv->enable_fb)
1291                         vmw_3d_resource_inc(dev_priv, false);
1292
1293         dev_priv->suspended = false;
1294 }
1295
1296 static const struct dev_pm_ops vmw_pm_ops = {
1297         .prepare = vmw_pm_prepare,
1298         .complete = vmw_pm_complete,
1299         .suspend = vmw_pm_suspend,
1300         .resume = vmw_pm_resume,
1301 };
1302
1303 static const struct file_operations vmwgfx_driver_fops = {
1304         .owner = THIS_MODULE,
1305         .open = drm_open,
1306         .release = drm_release,
1307         .unlocked_ioctl = vmw_unlocked_ioctl,
1308         .mmap = vmw_mmap,
1309         .poll = vmw_fops_poll,
1310         .read = vmw_fops_read,
1311 #if defined(CONFIG_COMPAT)
1312         .compat_ioctl = drm_compat_ioctl,
1313 #endif
1314         .llseek = noop_llseek,
1315 };
1316
1317 static struct drm_driver driver = {
1318         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1319         DRIVER_MODESET | DRIVER_PRIME,
1320         .load = vmw_driver_load,
1321         .unload = vmw_driver_unload,
1322         .lastclose = vmw_lastclose,
1323         .irq_preinstall = vmw_irq_preinstall,
1324         .irq_postinstall = vmw_irq_postinstall,
1325         .irq_uninstall = vmw_irq_uninstall,
1326         .irq_handler = vmw_irq_handler,
1327         .get_vblank_counter = vmw_get_vblank_counter,
1328         .enable_vblank = vmw_enable_vblank,
1329         .disable_vblank = vmw_disable_vblank,
1330         .ioctls = vmw_ioctls,
1331         .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
1332         .master_create = vmw_master_create,
1333         .master_destroy = vmw_master_destroy,
1334         .master_set = vmw_master_set,
1335         .master_drop = vmw_master_drop,
1336         .open = vmw_driver_open,
1337         .preclose = vmw_preclose,
1338         .postclose = vmw_postclose,
1339
1340         .dumb_create = vmw_dumb_create,
1341         .dumb_map_offset = vmw_dumb_map_offset,
1342         .dumb_destroy = vmw_dumb_destroy,
1343
1344         .prime_fd_to_handle = vmw_prime_fd_to_handle,
1345         .prime_handle_to_fd = vmw_prime_handle_to_fd,
1346
1347         .fops = &vmwgfx_driver_fops,
1348         .name = VMWGFX_DRIVER_NAME,
1349         .desc = VMWGFX_DRIVER_DESC,
1350         .date = VMWGFX_DRIVER_DATE,
1351         .major = VMWGFX_DRIVER_MAJOR,
1352         .minor = VMWGFX_DRIVER_MINOR,
1353         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1354 };
1355
1356 static struct pci_driver vmw_pci_driver = {
1357         .name = VMWGFX_DRIVER_NAME,
1358         .id_table = vmw_pci_id_list,
1359         .probe = vmw_probe,
1360         .remove = vmw_remove,
1361         .driver = {
1362                 .pm = &vmw_pm_ops
1363         }
1364 };
1365
1366 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1367 {
1368         return drm_get_pci_dev(pdev, ent, &driver);
1369 }
1370
1371 static int __init vmwgfx_init(void)
1372 {
1373         int ret;
1374         ret = drm_pci_init(&driver, &vmw_pci_driver);
1375         if (ret)
1376                 DRM_ERROR("Failed initializing DRM.\n");
1377         return ret;
1378 }
1379
1380 static void __exit vmwgfx_exit(void)
1381 {
1382         drm_pci_exit(&driver, &vmw_pci_driver);
1383 }
1384
1385 module_init(vmwgfx_init);
1386 module_exit(vmwgfx_exit);
1387
1388 MODULE_AUTHOR("VMware Inc. and others");
1389 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1390 MODULE_LICENSE("GPL and additional rights");
1391 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1392                __stringify(VMWGFX_DRIVER_MINOR) "."
1393                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1394                "0");