1 /**************************************************************************
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
27 #include <linux/module.h>
30 #include "vmwgfx_drv.h"
31 #include <drm/ttm/ttm_placement.h>
32 #include <drm/ttm/ttm_bo_driver.h>
33 #include <drm/ttm/ttm_object.h>
34 #include <drm/ttm/ttm_module.h>
35 #include <linux/dma_remapping.h>
37 #define VMWGFX_DRIVER_NAME "vmwgfx"
38 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
39 #define VMWGFX_CHIP_SVGAII 0
40 #define VMW_FB_RESERVATION 0
42 #define VMW_MIN_INITIAL_WIDTH 800
43 #define VMW_MIN_INITIAL_HEIGHT 600
47 * Fully encoded drm commands. Might move to vmw_drm.h
50 #define DRM_IOCTL_VMW_GET_PARAM \
51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
52 struct drm_vmw_getparam_arg)
53 #define DRM_IOCTL_VMW_ALLOC_DMABUF \
54 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
55 union drm_vmw_alloc_dmabuf_arg)
56 #define DRM_IOCTL_VMW_UNREF_DMABUF \
57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
58 struct drm_vmw_unref_dmabuf_arg)
59 #define DRM_IOCTL_VMW_CURSOR_BYPASS \
60 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
61 struct drm_vmw_cursor_bypass_arg)
63 #define DRM_IOCTL_VMW_CONTROL_STREAM \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
65 struct drm_vmw_control_stream_arg)
66 #define DRM_IOCTL_VMW_CLAIM_STREAM \
67 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
68 struct drm_vmw_stream_arg)
69 #define DRM_IOCTL_VMW_UNREF_STREAM \
70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
71 struct drm_vmw_stream_arg)
73 #define DRM_IOCTL_VMW_CREATE_CONTEXT \
74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
75 struct drm_vmw_context_arg)
76 #define DRM_IOCTL_VMW_UNREF_CONTEXT \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
78 struct drm_vmw_context_arg)
79 #define DRM_IOCTL_VMW_CREATE_SURFACE \
80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
81 union drm_vmw_surface_create_arg)
82 #define DRM_IOCTL_VMW_UNREF_SURFACE \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
84 struct drm_vmw_surface_arg)
85 #define DRM_IOCTL_VMW_REF_SURFACE \
86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
87 union drm_vmw_surface_reference_arg)
88 #define DRM_IOCTL_VMW_EXECBUF \
89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
90 struct drm_vmw_execbuf_arg)
91 #define DRM_IOCTL_VMW_GET_3D_CAP \
92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
93 struct drm_vmw_get_3d_cap_arg)
94 #define DRM_IOCTL_VMW_FENCE_WAIT \
95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
96 struct drm_vmw_fence_wait_arg)
97 #define DRM_IOCTL_VMW_FENCE_SIGNALED \
98 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
99 struct drm_vmw_fence_signaled_arg)
100 #define DRM_IOCTL_VMW_FENCE_UNREF \
101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
102 struct drm_vmw_fence_arg)
103 #define DRM_IOCTL_VMW_FENCE_EVENT \
104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
105 struct drm_vmw_fence_event_arg)
106 #define DRM_IOCTL_VMW_PRESENT \
107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
108 struct drm_vmw_present_arg)
109 #define DRM_IOCTL_VMW_PRESENT_READBACK \
110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
111 struct drm_vmw_present_readback_arg)
112 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
114 struct drm_vmw_update_layout_arg)
115 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
116 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
117 union drm_vmw_gb_surface_create_arg)
118 #define DRM_IOCTL_VMW_GB_SURFACE_REF \
119 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
120 union drm_vmw_gb_surface_reference_arg)
123 * The core DRM version of this macro doesn't account for
127 #define VMW_IOCTL_DEF(ioctl, func, flags) \
128 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
134 static const struct drm_ioctl_desc vmw_ioctls[] = {
135 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
136 DRM_AUTH | DRM_UNLOCKED),
137 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
138 DRM_AUTH | DRM_UNLOCKED),
139 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
140 DRM_AUTH | DRM_UNLOCKED),
141 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
142 vmw_kms_cursor_bypass_ioctl,
143 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
145 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
146 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
147 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
148 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
149 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
150 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
152 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
153 DRM_AUTH | DRM_UNLOCKED),
154 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
155 DRM_AUTH | DRM_UNLOCKED),
156 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
157 DRM_AUTH | DRM_UNLOCKED),
158 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
159 DRM_AUTH | DRM_UNLOCKED),
160 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
161 DRM_AUTH | DRM_UNLOCKED),
162 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
163 DRM_AUTH | DRM_UNLOCKED),
164 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
165 DRM_AUTH | DRM_UNLOCKED),
166 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
167 vmw_fence_obj_signaled_ioctl,
168 DRM_AUTH | DRM_UNLOCKED),
169 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
170 DRM_AUTH | DRM_UNLOCKED),
171 VMW_IOCTL_DEF(VMW_FENCE_EVENT,
172 vmw_fence_event_ioctl,
173 DRM_AUTH | DRM_UNLOCKED),
174 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
175 DRM_AUTH | DRM_UNLOCKED),
177 /* these allow direct access to the framebuffers mark as master only */
178 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
179 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
180 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
181 vmw_present_readback_ioctl,
182 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
183 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
184 vmw_kms_update_layout_ioctl,
185 DRM_MASTER | DRM_UNLOCKED),
186 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
187 vmw_gb_surface_define_ioctl,
188 DRM_AUTH | DRM_UNLOCKED),
189 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
190 vmw_gb_surface_reference_ioctl,
191 DRM_AUTH | DRM_UNLOCKED),
194 static struct pci_device_id vmw_pci_id_list[] = {
195 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
198 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
200 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
201 static int vmw_force_iommu;
202 static int vmw_restrict_iommu;
203 static int vmw_force_coherent;
204 static int vmw_restrict_dma_mask;
206 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
207 static void vmw_master_init(struct vmw_master *);
208 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
211 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
212 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
213 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
214 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
215 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
216 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
217 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
218 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
219 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
220 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
223 static void vmw_print_capabilities(uint32_t capabilities)
225 DRM_INFO("Capabilities:\n");
226 if (capabilities & SVGA_CAP_RECT_COPY)
227 DRM_INFO(" Rect copy.\n");
228 if (capabilities & SVGA_CAP_CURSOR)
229 DRM_INFO(" Cursor.\n");
230 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
231 DRM_INFO(" Cursor bypass.\n");
232 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
233 DRM_INFO(" Cursor bypass 2.\n");
234 if (capabilities & SVGA_CAP_8BIT_EMULATION)
235 DRM_INFO(" 8bit emulation.\n");
236 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
237 DRM_INFO(" Alpha cursor.\n");
238 if (capabilities & SVGA_CAP_3D)
240 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
241 DRM_INFO(" Extended Fifo.\n");
242 if (capabilities & SVGA_CAP_MULTIMON)
243 DRM_INFO(" Multimon.\n");
244 if (capabilities & SVGA_CAP_PITCHLOCK)
245 DRM_INFO(" Pitchlock.\n");
246 if (capabilities & SVGA_CAP_IRQMASK)
247 DRM_INFO(" Irq mask.\n");
248 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
249 DRM_INFO(" Display Topology.\n");
250 if (capabilities & SVGA_CAP_GMR)
252 if (capabilities & SVGA_CAP_TRACES)
253 DRM_INFO(" Traces.\n");
254 if (capabilities & SVGA_CAP_GMR2)
255 DRM_INFO(" GMR2.\n");
256 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
257 DRM_INFO(" Screen Object 2.\n");
258 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
259 DRM_INFO(" Command Buffers.\n");
260 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
261 DRM_INFO(" Command Buffers 2.\n");
262 if (capabilities & SVGA_CAP_GBOBJECTS)
263 DRM_INFO(" Guest Backed Resources.\n");
268 * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at
269 * the start of a buffer object.
271 * @dev_priv: The device private structure.
273 * This function will idle the buffer using an uninterruptible wait, then
274 * map the first page and initialize a pending occlusion query result structure,
275 * Finally it will unmap the buffer.
277 * TODO: Since we're only mapping a single page, we should optimize the map
278 * to use kmap_atomic / iomap_atomic.
280 static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv)
282 struct ttm_bo_kmap_obj map;
283 volatile SVGA3dQueryResult *result;
286 struct ttm_bo_device *bdev = &dev_priv->bdev;
287 struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
289 ttm_bo_reserve(bo, false, false, false, 0);
290 spin_lock(&bdev->fence_lock);
291 ret = ttm_bo_wait(bo, false, false, false);
292 spin_unlock(&bdev->fence_lock);
293 if (unlikely(ret != 0))
294 (void) vmw_fallback_wait(dev_priv, false, true, 0, false,
297 ret = ttm_bo_kmap(bo, 0, 1, &map);
298 if (likely(ret == 0)) {
299 result = ttm_kmap_obj_virtual(&map, &dummy);
300 result->totalSize = sizeof(*result);
301 result->state = SVGA3D_QUERYSTATE_PENDING;
302 result->result32 = 0xff;
305 DRM_ERROR("Dummy query buffer map failed.\n");
306 ttm_bo_unreserve(bo);
311 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
313 * @dev_priv: A device private structure.
315 * This function creates a small buffer object that holds the query
316 * result for dummy queries emitted as query barriers.
317 * No interruptible waits are done within this function.
319 * Returns an error if bo creation fails.
321 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
323 return ttm_bo_create(&dev_priv->bdev,
326 &vmw_vram_sys_placement,
328 &dev_priv->dummy_query_bo);
332 static int vmw_request_device(struct vmw_private *dev_priv)
336 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
337 if (unlikely(ret != 0)) {
338 DRM_ERROR("Unable to initialize FIFO.\n");
341 vmw_fence_fifo_up(dev_priv->fman);
342 if (dev_priv->has_mob) {
343 ret = vmw_otables_setup(dev_priv);
344 if (unlikely(ret != 0)) {
345 DRM_ERROR("Unable to initialize "
346 "guest Memory OBjects.\n");
350 ret = vmw_dummy_query_bo_create(dev_priv);
351 if (unlikely(ret != 0))
352 goto out_no_query_bo;
353 vmw_dummy_query_bo_prepare(dev_priv);
358 if (dev_priv->has_mob)
359 vmw_otables_takedown(dev_priv);
361 vmw_fence_fifo_down(dev_priv->fman);
362 vmw_fifo_release(dev_priv, &dev_priv->fifo);
366 static void vmw_release_device(struct vmw_private *dev_priv)
369 * Previous destructions should've released
373 BUG_ON(dev_priv->pinned_bo != NULL);
375 ttm_bo_unref(&dev_priv->dummy_query_bo);
376 if (dev_priv->has_mob)
377 vmw_otables_takedown(dev_priv);
378 vmw_fence_fifo_down(dev_priv->fman);
379 vmw_fifo_release(dev_priv, &dev_priv->fifo);
384 * Increase the 3d resource refcount.
385 * If the count was prevously zero, initialize the fifo, switching to svga
386 * mode. Note that the master holds a ref as well, and may request an
387 * explicit switch to svga mode if fb is not running, using @unhide_svga.
389 int vmw_3d_resource_inc(struct vmw_private *dev_priv,
394 mutex_lock(&dev_priv->release_mutex);
395 if (unlikely(dev_priv->num_3d_resources++ == 0)) {
396 ret = vmw_request_device(dev_priv);
397 if (unlikely(ret != 0))
398 --dev_priv->num_3d_resources;
399 } else if (unhide_svga) {
400 mutex_lock(&dev_priv->hw_mutex);
401 vmw_write(dev_priv, SVGA_REG_ENABLE,
402 vmw_read(dev_priv, SVGA_REG_ENABLE) &
403 ~SVGA_REG_ENABLE_HIDE);
404 mutex_unlock(&dev_priv->hw_mutex);
407 mutex_unlock(&dev_priv->release_mutex);
412 * Decrease the 3d resource refcount.
413 * If the count reaches zero, disable the fifo, switching to vga mode.
414 * Note that the master holds a refcount as well, and may request an
415 * explicit switch to vga mode when it releases its refcount to account
416 * for the situation of an X server vt switch to VGA with 3d resources
419 void vmw_3d_resource_dec(struct vmw_private *dev_priv,
424 mutex_lock(&dev_priv->release_mutex);
425 if (unlikely(--dev_priv->num_3d_resources == 0))
426 vmw_release_device(dev_priv);
427 else if (hide_svga) {
428 mutex_lock(&dev_priv->hw_mutex);
429 vmw_write(dev_priv, SVGA_REG_ENABLE,
430 vmw_read(dev_priv, SVGA_REG_ENABLE) |
431 SVGA_REG_ENABLE_HIDE);
432 mutex_unlock(&dev_priv->hw_mutex);
435 n3d = (int32_t) dev_priv->num_3d_resources;
436 mutex_unlock(&dev_priv->release_mutex);
442 * Sets the initial_[width|height] fields on the given vmw_private.
444 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
445 * clamping the value to fb_max_[width|height] fields and the
446 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
447 * If the values appear to be invalid, set them to
448 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
450 static void vmw_get_initial_size(struct vmw_private *dev_priv)
455 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
456 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
458 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
459 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
461 if (width > dev_priv->fb_max_width ||
462 height > dev_priv->fb_max_height) {
465 * This is a host error and shouldn't occur.
468 width = VMW_MIN_INITIAL_WIDTH;
469 height = VMW_MIN_INITIAL_HEIGHT;
472 dev_priv->initial_width = width;
473 dev_priv->initial_height = height;
477 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
480 * @dev_priv: Pointer to a struct vmw_private
482 * This functions tries to determine the IOMMU setup and what actions
483 * need to be taken by the driver to make system pages visible to the
485 * If this function decides that DMA is not possible, it returns -EINVAL.
486 * The driver may then try to disable features of the device that require
489 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
491 static const char *names[vmw_dma_map_max] = {
492 [vmw_dma_phys] = "Using physical TTM page addresses.",
493 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
494 [vmw_dma_map_populate] = "Keeping DMA mappings.",
495 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
497 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
499 #ifdef CONFIG_INTEL_IOMMU
500 if (intel_iommu_enabled) {
501 dev_priv->map_mode = vmw_dma_map_populate;
506 if (!(vmw_force_iommu || vmw_force_coherent)) {
507 dev_priv->map_mode = vmw_dma_phys;
508 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
512 dev_priv->map_mode = vmw_dma_map_populate;
514 if (dma_ops->sync_single_for_cpu)
515 dev_priv->map_mode = vmw_dma_alloc_coherent;
516 #ifdef CONFIG_SWIOTLB
517 if (swiotlb_nr_tbl() == 0)
518 dev_priv->map_mode = vmw_dma_map_populate;
521 #ifdef CONFIG_INTEL_IOMMU
524 if (dev_priv->map_mode == vmw_dma_map_populate &&
526 dev_priv->map_mode = vmw_dma_map_bind;
528 if (vmw_force_coherent)
529 dev_priv->map_mode = vmw_dma_alloc_coherent;
531 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
533 * No coherent page pool
535 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
539 #else /* CONFIG_X86 */
540 dev_priv->map_mode = vmw_dma_map_populate;
541 #endif /* CONFIG_X86 */
543 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
549 * vmw_dma_masks - set required page- and dma masks
551 * @dev: Pointer to struct drm-device
553 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
554 * restriction also for 64-bit systems.
556 #ifdef CONFIG_INTEL_IOMMU
557 static int vmw_dma_masks(struct vmw_private *dev_priv)
559 struct drm_device *dev = dev_priv->dev;
561 if (intel_iommu_enabled &&
562 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
563 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
564 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
569 static int vmw_dma_masks(struct vmw_private *dev_priv)
575 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
577 struct vmw_private *dev_priv;
581 bool refuse_dma = false;
583 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
584 if (unlikely(dev_priv == NULL)) {
585 DRM_ERROR("Failed allocating a device private struct.\n");
589 pci_set_master(dev->pdev);
592 dev_priv->vmw_chipset = chipset;
593 dev_priv->last_read_seqno = (uint32_t) -100;
594 mutex_init(&dev_priv->hw_mutex);
595 mutex_init(&dev_priv->cmdbuf_mutex);
596 mutex_init(&dev_priv->release_mutex);
597 rwlock_init(&dev_priv->resource_lock);
599 for (i = vmw_res_context; i < vmw_res_max; ++i) {
600 idr_init(&dev_priv->res_idr[i]);
601 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
604 mutex_init(&dev_priv->init_mutex);
605 init_waitqueue_head(&dev_priv->fence_queue);
606 init_waitqueue_head(&dev_priv->fifo_queue);
607 dev_priv->fence_queue_waiters = 0;
608 atomic_set(&dev_priv->fifo_queue_waiters, 0);
610 dev_priv->used_memory_size = 0;
612 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
613 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
614 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
616 dev_priv->enable_fb = enable_fbdev;
618 mutex_lock(&dev_priv->hw_mutex);
620 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
621 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
622 if (svga_id != SVGA_ID_2) {
624 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
625 mutex_unlock(&dev_priv->hw_mutex);
629 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
630 ret = vmw_dma_select_mode(dev_priv);
631 if (unlikely(ret != 0)) {
632 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
636 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
637 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
638 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
639 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
641 vmw_get_initial_size(dev_priv);
643 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
644 dev_priv->max_gmr_ids =
645 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
646 dev_priv->max_gmr_pages =
647 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
648 dev_priv->memory_size =
649 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
650 dev_priv->memory_size -= dev_priv->vram_size;
653 * An arbitrary limit of 512MiB on surface
654 * memory. But all HWV8 hardware supports GMR2.
656 dev_priv->memory_size = 512*1024*1024;
658 dev_priv->max_mob_pages = 0;
659 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
662 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
664 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
665 dev_priv->prim_bb_mem =
667 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
669 dev_priv->prim_bb_mem = dev_priv->vram_size;
671 ret = vmw_dma_masks(dev_priv);
672 if (unlikely(ret != 0))
675 if (unlikely(dev_priv->prim_bb_mem < dev_priv->vram_size))
676 dev_priv->prim_bb_mem = dev_priv->vram_size;
678 mutex_unlock(&dev_priv->hw_mutex);
680 vmw_print_capabilities(dev_priv->capabilities);
682 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
683 DRM_INFO("Max GMR ids is %u\n",
684 (unsigned)dev_priv->max_gmr_ids);
685 DRM_INFO("Max number of GMR pages is %u\n",
686 (unsigned)dev_priv->max_gmr_pages);
687 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
688 (unsigned)dev_priv->memory_size / 1024);
690 DRM_INFO("Maximum display memory size is %u kiB\n",
691 dev_priv->prim_bb_mem / 1024);
692 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
693 dev_priv->vram_start, dev_priv->vram_size / 1024);
694 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
695 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
697 ret = vmw_ttm_global_init(dev_priv);
698 if (unlikely(ret != 0))
702 vmw_master_init(&dev_priv->fbdev_master);
703 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
704 dev_priv->active_master = &dev_priv->fbdev_master;
707 ret = ttm_bo_device_init(&dev_priv->bdev,
708 dev_priv->bo_global_ref.ref.object,
709 &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
711 if (unlikely(ret != 0)) {
712 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
716 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
717 (dev_priv->vram_size >> PAGE_SHIFT));
718 if (unlikely(ret != 0)) {
719 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
723 dev_priv->has_gmr = true;
724 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
725 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
727 DRM_INFO("No GMR memory available. "
728 "Graphics memory resources are very limited.\n");
729 dev_priv->has_gmr = false;
732 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
733 dev_priv->has_mob = true;
734 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
736 DRM_INFO("No MOB memory available. "
737 "3D will be disabled.\n");
738 dev_priv->has_mob = false;
742 dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
743 dev_priv->mmio_size);
745 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
746 dev_priv->mmio_size);
748 if (unlikely(dev_priv->mmio_virt == NULL)) {
750 DRM_ERROR("Failed mapping MMIO.\n");
754 /* Need mmio memory to check for fifo pitchlock cap. */
755 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
756 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
757 !vmw_fifo_have_pitchlock(dev_priv)) {
759 DRM_ERROR("Hardware has no pitchlock\n");
763 dev_priv->tdev = ttm_object_device_init
764 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
766 if (unlikely(dev_priv->tdev == NULL)) {
767 DRM_ERROR("Unable to initialize TTM object management.\n");
772 dev->dev_private = dev_priv;
774 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
775 dev_priv->stealth = (ret != 0);
776 if (dev_priv->stealth) {
778 * Request at least the mmio PCI resource.
781 DRM_INFO("It appears like vesafb is loaded. "
782 "Ignore above error if any.\n");
783 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
784 if (unlikely(ret != 0)) {
785 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
790 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
791 ret = drm_irq_install(dev);
793 DRM_ERROR("Failed installing irq: %d\n", ret);
798 dev_priv->fman = vmw_fence_manager_init(dev_priv);
799 if (unlikely(dev_priv->fman == NULL)) {
804 vmw_kms_save_vga(dev_priv);
806 /* Start kms and overlay systems, needs fifo. */
807 ret = vmw_kms_init(dev_priv);
808 if (unlikely(ret != 0))
810 vmw_overlay_init(dev_priv);
812 if (dev_priv->enable_fb) {
813 ret = vmw_3d_resource_inc(dev_priv, true);
814 if (unlikely(ret != 0))
816 vmw_fb_init(dev_priv);
819 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
820 register_pm_notifier(&dev_priv->pm_nb);
825 vmw_overlay_close(dev_priv);
826 vmw_kms_close(dev_priv);
828 vmw_kms_restore_vga(dev_priv);
829 vmw_fence_manager_takedown(dev_priv->fman);
831 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
832 drm_irq_uninstall(dev_priv->dev);
834 if (dev_priv->stealth)
835 pci_release_region(dev->pdev, 2);
837 pci_release_regions(dev->pdev);
839 ttm_object_device_release(&dev_priv->tdev);
841 iounmap(dev_priv->mmio_virt);
843 arch_phys_wc_del(dev_priv->mmio_mtrr);
844 if (dev_priv->has_mob)
845 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
846 if (dev_priv->has_gmr)
847 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
848 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
850 (void)ttm_bo_device_release(&dev_priv->bdev);
852 vmw_ttm_global_release(dev_priv);
854 for (i = vmw_res_context; i < vmw_res_max; ++i)
855 idr_destroy(&dev_priv->res_idr[i]);
861 static int vmw_driver_unload(struct drm_device *dev)
863 struct vmw_private *dev_priv = vmw_priv(dev);
866 unregister_pm_notifier(&dev_priv->pm_nb);
868 if (dev_priv->ctx.res_ht_initialized)
869 drm_ht_remove(&dev_priv->ctx.res_ht);
870 if (dev_priv->ctx.cmd_bounce)
871 vfree(dev_priv->ctx.cmd_bounce);
872 if (dev_priv->enable_fb) {
873 vmw_fb_close(dev_priv);
874 vmw_kms_restore_vga(dev_priv);
875 vmw_3d_resource_dec(dev_priv, false);
877 vmw_kms_close(dev_priv);
878 vmw_overlay_close(dev_priv);
879 vmw_fence_manager_takedown(dev_priv->fman);
880 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
881 drm_irq_uninstall(dev_priv->dev);
882 if (dev_priv->stealth)
883 pci_release_region(dev->pdev, 2);
885 pci_release_regions(dev->pdev);
887 ttm_object_device_release(&dev_priv->tdev);
888 iounmap(dev_priv->mmio_virt);
889 arch_phys_wc_del(dev_priv->mmio_mtrr);
890 if (dev_priv->has_mob)
891 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
892 if (dev_priv->has_gmr)
893 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
894 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
895 (void)ttm_bo_device_release(&dev_priv->bdev);
896 vmw_ttm_global_release(dev_priv);
898 for (i = vmw_res_context; i < vmw_res_max; ++i)
899 idr_destroy(&dev_priv->res_idr[i]);
906 static void vmw_preclose(struct drm_device *dev,
907 struct drm_file *file_priv)
909 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
910 struct vmw_private *dev_priv = vmw_priv(dev);
912 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
915 static void vmw_postclose(struct drm_device *dev,
916 struct drm_file *file_priv)
918 struct vmw_fpriv *vmw_fp;
920 vmw_fp = vmw_fpriv(file_priv);
922 if (vmw_fp->locked_master) {
923 struct vmw_master *vmaster =
924 vmw_master(vmw_fp->locked_master);
926 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
927 ttm_vt_unlock(&vmaster->lock);
928 drm_master_put(&vmw_fp->locked_master);
931 ttm_object_file_release(&vmw_fp->tfile);
935 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
937 struct vmw_private *dev_priv = vmw_priv(dev);
938 struct vmw_fpriv *vmw_fp;
941 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
942 if (unlikely(vmw_fp == NULL))
945 INIT_LIST_HEAD(&vmw_fp->fence_events);
946 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
947 if (unlikely(vmw_fp->tfile == NULL))
950 file_priv->driver_priv = vmw_fp;
951 dev_priv->bdev.dev_mapping = dev->dev_mapping;
960 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
963 struct drm_file *file_priv = filp->private_data;
964 struct drm_device *dev = file_priv->minor->dev;
965 unsigned int nr = DRM_IOCTL_NR(cmd);
968 * Do extra checking on driver private ioctls.
971 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
972 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
973 const struct drm_ioctl_desc *ioctl =
974 &vmw_ioctls[nr - DRM_COMMAND_BASE];
976 if (unlikely(ioctl->cmd_drv != cmd)) {
977 DRM_ERROR("Invalid command format, ioctl %d\n",
978 nr - DRM_COMMAND_BASE);
983 return drm_ioctl(filp, cmd, arg);
986 static void vmw_lastclose(struct drm_device *dev)
988 struct drm_crtc *crtc;
989 struct drm_mode_set set;
996 set.connectors = NULL;
997 set.num_connectors = 0;
999 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1001 ret = drm_mode_set_config_internal(&set);
1007 static void vmw_master_init(struct vmw_master *vmaster)
1009 ttm_lock_init(&vmaster->lock);
1010 INIT_LIST_HEAD(&vmaster->fb_surf);
1011 mutex_init(&vmaster->fb_surf_mutex);
1014 static int vmw_master_create(struct drm_device *dev,
1015 struct drm_master *master)
1017 struct vmw_master *vmaster;
1019 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1020 if (unlikely(vmaster == NULL))
1023 vmw_master_init(vmaster);
1024 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1025 master->driver_priv = vmaster;
1030 static void vmw_master_destroy(struct drm_device *dev,
1031 struct drm_master *master)
1033 struct vmw_master *vmaster = vmw_master(master);
1035 master->driver_priv = NULL;
1040 static int vmw_master_set(struct drm_device *dev,
1041 struct drm_file *file_priv,
1044 struct vmw_private *dev_priv = vmw_priv(dev);
1045 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1046 struct vmw_master *active = dev_priv->active_master;
1047 struct vmw_master *vmaster = vmw_master(file_priv->master);
1050 if (!dev_priv->enable_fb) {
1051 ret = vmw_3d_resource_inc(dev_priv, true);
1052 if (unlikely(ret != 0))
1054 vmw_kms_save_vga(dev_priv);
1055 mutex_lock(&dev_priv->hw_mutex);
1056 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
1057 mutex_unlock(&dev_priv->hw_mutex);
1061 BUG_ON(active != &dev_priv->fbdev_master);
1062 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1063 if (unlikely(ret != 0))
1064 goto out_no_active_lock;
1066 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1067 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1068 if (unlikely(ret != 0)) {
1069 DRM_ERROR("Unable to clean VRAM on "
1073 dev_priv->active_master = NULL;
1076 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1078 ttm_vt_unlock(&vmaster->lock);
1079 BUG_ON(vmw_fp->locked_master != file_priv->master);
1080 drm_master_put(&vmw_fp->locked_master);
1083 dev_priv->active_master = vmaster;
1088 if (!dev_priv->enable_fb) {
1089 vmw_kms_restore_vga(dev_priv);
1090 vmw_3d_resource_dec(dev_priv, true);
1091 mutex_lock(&dev_priv->hw_mutex);
1092 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1093 mutex_unlock(&dev_priv->hw_mutex);
1098 static void vmw_master_drop(struct drm_device *dev,
1099 struct drm_file *file_priv,
1102 struct vmw_private *dev_priv = vmw_priv(dev);
1103 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1104 struct vmw_master *vmaster = vmw_master(file_priv->master);
1108 * Make sure the master doesn't disappear while we have
1112 vmw_fp->locked_master = drm_master_get(file_priv->master);
1113 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1114 if (unlikely((ret != 0))) {
1115 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1116 drm_master_put(&vmw_fp->locked_master);
1119 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1120 vmw_execbuf_release_pinned_bo(dev_priv);
1122 if (!dev_priv->enable_fb) {
1123 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1124 if (unlikely(ret != 0))
1125 DRM_ERROR("Unable to clean VRAM on master drop.\n");
1126 vmw_kms_restore_vga(dev_priv);
1127 vmw_3d_resource_dec(dev_priv, true);
1128 mutex_lock(&dev_priv->hw_mutex);
1129 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1130 mutex_unlock(&dev_priv->hw_mutex);
1133 dev_priv->active_master = &dev_priv->fbdev_master;
1134 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1135 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1137 if (dev_priv->enable_fb)
1138 vmw_fb_on(dev_priv);
1142 static void vmw_remove(struct pci_dev *pdev)
1144 struct drm_device *dev = pci_get_drvdata(pdev);
1149 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1152 struct vmw_private *dev_priv =
1153 container_of(nb, struct vmw_private, pm_nb);
1154 struct vmw_master *vmaster = dev_priv->active_master;
1157 case PM_HIBERNATION_PREPARE:
1158 case PM_SUSPEND_PREPARE:
1159 ttm_suspend_lock(&vmaster->lock);
1162 * This empties VRAM and unbinds all GMR bindings.
1163 * Buffer contents is moved to swappable memory.
1165 vmw_execbuf_release_pinned_bo(dev_priv);
1166 vmw_resource_evict_all(dev_priv);
1167 ttm_bo_swapout_all(&dev_priv->bdev);
1170 case PM_POST_HIBERNATION:
1171 case PM_POST_SUSPEND:
1172 case PM_POST_RESTORE:
1173 ttm_suspend_unlock(&vmaster->lock);
1176 case PM_RESTORE_PREPARE:
1185 * These might not be needed with the virtual SVGA device.
1188 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1190 struct drm_device *dev = pci_get_drvdata(pdev);
1191 struct vmw_private *dev_priv = vmw_priv(dev);
1193 if (dev_priv->num_3d_resources != 0) {
1194 DRM_INFO("Can't suspend or hibernate "
1195 "while 3D resources are active.\n");
1199 pci_save_state(pdev);
1200 pci_disable_device(pdev);
1201 pci_set_power_state(pdev, PCI_D3hot);
1205 static int vmw_pci_resume(struct pci_dev *pdev)
1207 pci_set_power_state(pdev, PCI_D0);
1208 pci_restore_state(pdev);
1209 return pci_enable_device(pdev);
1212 static int vmw_pm_suspend(struct device *kdev)
1214 struct pci_dev *pdev = to_pci_dev(kdev);
1215 struct pm_message dummy;
1219 return vmw_pci_suspend(pdev, dummy);
1222 static int vmw_pm_resume(struct device *kdev)
1224 struct pci_dev *pdev = to_pci_dev(kdev);
1226 return vmw_pci_resume(pdev);
1229 static int vmw_pm_prepare(struct device *kdev)
1231 struct pci_dev *pdev = to_pci_dev(kdev);
1232 struct drm_device *dev = pci_get_drvdata(pdev);
1233 struct vmw_private *dev_priv = vmw_priv(dev);
1236 * Release 3d reference held by fbdev and potentially
1239 dev_priv->suspended = true;
1240 if (dev_priv->enable_fb)
1241 vmw_3d_resource_dec(dev_priv, true);
1243 if (dev_priv->num_3d_resources != 0) {
1245 DRM_INFO("Can't suspend or hibernate "
1246 "while 3D resources are active.\n");
1248 if (dev_priv->enable_fb)
1249 vmw_3d_resource_inc(dev_priv, true);
1250 dev_priv->suspended = false;
1257 static void vmw_pm_complete(struct device *kdev)
1259 struct pci_dev *pdev = to_pci_dev(kdev);
1260 struct drm_device *dev = pci_get_drvdata(pdev);
1261 struct vmw_private *dev_priv = vmw_priv(dev);
1263 mutex_lock(&dev_priv->hw_mutex);
1264 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1265 (void) vmw_read(dev_priv, SVGA_REG_ID);
1266 mutex_unlock(&dev_priv->hw_mutex);
1269 * Reclaim 3d reference held by fbdev and potentially
1272 if (dev_priv->enable_fb)
1273 vmw_3d_resource_inc(dev_priv, false);
1275 dev_priv->suspended = false;
1278 static const struct dev_pm_ops vmw_pm_ops = {
1279 .prepare = vmw_pm_prepare,
1280 .complete = vmw_pm_complete,
1281 .suspend = vmw_pm_suspend,
1282 .resume = vmw_pm_resume,
1285 static const struct file_operations vmwgfx_driver_fops = {
1286 .owner = THIS_MODULE,
1288 .release = drm_release,
1289 .unlocked_ioctl = vmw_unlocked_ioctl,
1291 .poll = vmw_fops_poll,
1292 .read = vmw_fops_read,
1293 #if defined(CONFIG_COMPAT)
1294 .compat_ioctl = drm_compat_ioctl,
1296 .llseek = noop_llseek,
1299 static struct drm_driver driver = {
1300 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1301 DRIVER_MODESET | DRIVER_PRIME,
1302 .load = vmw_driver_load,
1303 .unload = vmw_driver_unload,
1304 .lastclose = vmw_lastclose,
1305 .irq_preinstall = vmw_irq_preinstall,
1306 .irq_postinstall = vmw_irq_postinstall,
1307 .irq_uninstall = vmw_irq_uninstall,
1308 .irq_handler = vmw_irq_handler,
1309 .get_vblank_counter = vmw_get_vblank_counter,
1310 .enable_vblank = vmw_enable_vblank,
1311 .disable_vblank = vmw_disable_vblank,
1312 .ioctls = vmw_ioctls,
1313 .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
1314 .master_create = vmw_master_create,
1315 .master_destroy = vmw_master_destroy,
1316 .master_set = vmw_master_set,
1317 .master_drop = vmw_master_drop,
1318 .open = vmw_driver_open,
1319 .preclose = vmw_preclose,
1320 .postclose = vmw_postclose,
1322 .dumb_create = vmw_dumb_create,
1323 .dumb_map_offset = vmw_dumb_map_offset,
1324 .dumb_destroy = vmw_dumb_destroy,
1326 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1327 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1329 .fops = &vmwgfx_driver_fops,
1330 .name = VMWGFX_DRIVER_NAME,
1331 .desc = VMWGFX_DRIVER_DESC,
1332 .date = VMWGFX_DRIVER_DATE,
1333 .major = VMWGFX_DRIVER_MAJOR,
1334 .minor = VMWGFX_DRIVER_MINOR,
1335 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1338 static struct pci_driver vmw_pci_driver = {
1339 .name = VMWGFX_DRIVER_NAME,
1340 .id_table = vmw_pci_id_list,
1342 .remove = vmw_remove,
1348 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1350 return drm_get_pci_dev(pdev, ent, &driver);
1353 static int __init vmwgfx_init(void)
1356 ret = drm_pci_init(&driver, &vmw_pci_driver);
1358 DRM_ERROR("Failed initializing DRM.\n");
1362 static void __exit vmwgfx_exit(void)
1364 drm_pci_exit(&driver, &vmw_pci_driver);
1367 module_init(vmwgfx_init);
1368 module_exit(vmwgfx_exit);
1370 MODULE_AUTHOR("VMware Inc. and others");
1371 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1372 MODULE_LICENSE("GPL and additional rights");
1373 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1374 __stringify(VMWGFX_DRIVER_MINOR) "."
1375 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."