2 * Copyright (C) 2015 Red Hat, Inc.
6 * Dave Airlie <airlied@redhat.com>
7 * Gerd Hoffmann <kraxel@redhat.com>
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
26 * OTHER DEALINGS IN THE SOFTWARE.
29 #include <linux/dma-mapping.h>
30 #include <linux/virtio.h>
31 #include <linux/virtio_config.h>
32 #include <linux/virtio_ring.h>
34 #include "virtgpu_drv.h"
35 #include "virtgpu_trace.h"
37 #define MAX_INLINE_CMD_SIZE 96
38 #define MAX_INLINE_RESP_SIZE 24
39 #define VBUFFER_SIZE (sizeof(struct virtio_gpu_vbuffer) \
40 + MAX_INLINE_CMD_SIZE \
41 + MAX_INLINE_RESP_SIZE)
43 static void convert_to_hw_box(struct virtio_gpu_box *dst,
44 const struct drm_virtgpu_3d_box *src)
46 dst->x = cpu_to_le32(src->x);
47 dst->y = cpu_to_le32(src->y);
48 dst->z = cpu_to_le32(src->z);
49 dst->w = cpu_to_le32(src->w);
50 dst->h = cpu_to_le32(src->h);
51 dst->d = cpu_to_le32(src->d);
54 void virtio_gpu_ctrl_ack(struct virtqueue *vq)
56 struct drm_device *dev = vq->vdev->priv;
57 struct virtio_gpu_device *vgdev = dev->dev_private;
59 schedule_work(&vgdev->ctrlq.dequeue_work);
62 void virtio_gpu_cursor_ack(struct virtqueue *vq)
64 struct drm_device *dev = vq->vdev->priv;
65 struct virtio_gpu_device *vgdev = dev->dev_private;
67 schedule_work(&vgdev->cursorq.dequeue_work);
70 int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev)
72 vgdev->vbufs = kmem_cache_create("virtio-gpu-vbufs",
74 __alignof__(struct virtio_gpu_vbuffer),
81 void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev)
83 kmem_cache_destroy(vgdev->vbufs);
87 static struct virtio_gpu_vbuffer*
88 virtio_gpu_get_vbuf(struct virtio_gpu_device *vgdev,
89 int size, int resp_size, void *resp_buf,
90 virtio_gpu_resp_cb resp_cb)
92 struct virtio_gpu_vbuffer *vbuf;
94 vbuf = kmem_cache_zalloc(vgdev->vbufs, GFP_KERNEL);
96 return ERR_PTR(-ENOMEM);
98 BUG_ON(size > MAX_INLINE_CMD_SIZE ||
99 size < sizeof(struct virtio_gpu_ctrl_hdr));
100 vbuf->buf = (void *)vbuf + sizeof(*vbuf);
103 vbuf->resp_cb = resp_cb;
104 vbuf->resp_size = resp_size;
105 if (resp_size <= MAX_INLINE_RESP_SIZE)
106 vbuf->resp_buf = (void *)vbuf->buf + size;
108 vbuf->resp_buf = resp_buf;
109 BUG_ON(!vbuf->resp_buf);
113 static struct virtio_gpu_ctrl_hdr *
114 virtio_gpu_vbuf_ctrl_hdr(struct virtio_gpu_vbuffer *vbuf)
116 /* this assumes a vbuf contains a command that starts with a
117 * virtio_gpu_ctrl_hdr, which is true for both ctrl and cursor
120 return (struct virtio_gpu_ctrl_hdr *)vbuf->buf;
123 static struct virtio_gpu_update_cursor*
124 virtio_gpu_alloc_cursor(struct virtio_gpu_device *vgdev,
125 struct virtio_gpu_vbuffer **vbuffer_p)
127 struct virtio_gpu_vbuffer *vbuf;
129 vbuf = virtio_gpu_get_vbuf
130 (vgdev, sizeof(struct virtio_gpu_update_cursor),
134 return ERR_CAST(vbuf);
137 return (struct virtio_gpu_update_cursor *)vbuf->buf;
140 static void *virtio_gpu_alloc_cmd_resp(struct virtio_gpu_device *vgdev,
141 virtio_gpu_resp_cb cb,
142 struct virtio_gpu_vbuffer **vbuffer_p,
143 int cmd_size, int resp_size,
146 struct virtio_gpu_vbuffer *vbuf;
148 vbuf = virtio_gpu_get_vbuf(vgdev, cmd_size,
149 resp_size, resp_buf, cb);
152 return ERR_CAST(vbuf);
155 return (struct virtio_gpu_command *)vbuf->buf;
158 static void *virtio_gpu_alloc_cmd(struct virtio_gpu_device *vgdev,
159 struct virtio_gpu_vbuffer **vbuffer_p,
162 return virtio_gpu_alloc_cmd_resp(vgdev, NULL, vbuffer_p, size,
163 sizeof(struct virtio_gpu_ctrl_hdr),
167 static void *virtio_gpu_alloc_cmd_cb(struct virtio_gpu_device *vgdev,
168 struct virtio_gpu_vbuffer **vbuffer_p,
170 virtio_gpu_resp_cb cb)
172 return virtio_gpu_alloc_cmd_resp(vgdev, cb, vbuffer_p, size,
173 sizeof(struct virtio_gpu_ctrl_hdr),
177 static void free_vbuf(struct virtio_gpu_device *vgdev,
178 struct virtio_gpu_vbuffer *vbuf)
180 if (vbuf->resp_size > MAX_INLINE_RESP_SIZE)
181 kfree(vbuf->resp_buf);
182 kvfree(vbuf->data_buf);
183 kmem_cache_free(vgdev->vbufs, vbuf);
186 static void reclaim_vbufs(struct virtqueue *vq, struct list_head *reclaim_list)
188 struct virtio_gpu_vbuffer *vbuf;
192 while ((vbuf = virtqueue_get_buf(vq, &len))) {
193 list_add_tail(&vbuf->list, reclaim_list);
197 DRM_DEBUG("Huh? zero vbufs reclaimed");
200 void virtio_gpu_dequeue_ctrl_func(struct work_struct *work)
202 struct virtio_gpu_device *vgdev =
203 container_of(work, struct virtio_gpu_device,
205 struct list_head reclaim_list;
206 struct virtio_gpu_vbuffer *entry, *tmp;
207 struct virtio_gpu_ctrl_hdr *resp;
210 INIT_LIST_HEAD(&reclaim_list);
211 spin_lock(&vgdev->ctrlq.qlock);
213 virtqueue_disable_cb(vgdev->ctrlq.vq);
214 reclaim_vbufs(vgdev->ctrlq.vq, &reclaim_list);
216 } while (!virtqueue_enable_cb(vgdev->ctrlq.vq));
217 spin_unlock(&vgdev->ctrlq.qlock);
219 list_for_each_entry(entry, &reclaim_list, list) {
220 resp = (struct virtio_gpu_ctrl_hdr *)entry->resp_buf;
222 trace_virtio_gpu_cmd_response(vgdev->ctrlq.vq, resp);
224 if (resp->type != cpu_to_le32(VIRTIO_GPU_RESP_OK_NODATA)) {
225 if (le32_to_cpu(resp->type) >= VIRTIO_GPU_RESP_ERR_UNSPEC) {
226 struct virtio_gpu_ctrl_hdr *cmd;
227 cmd = virtio_gpu_vbuf_ctrl_hdr(entry);
228 DRM_ERROR_RATELIMITED("response 0x%x (command 0x%x)\n",
229 le32_to_cpu(resp->type),
230 le32_to_cpu(cmd->type));
232 DRM_DEBUG("response 0x%x\n", le32_to_cpu(resp->type));
234 if (resp->flags & cpu_to_le32(VIRTIO_GPU_FLAG_FENCE)) {
235 u64 f = le64_to_cpu(resp->fence_id);
238 DRM_ERROR("%s: Oops: fence %llx -> %llx\n",
239 __func__, fence_id, f);
245 entry->resp_cb(vgdev, entry);
247 wake_up(&vgdev->ctrlq.ack_queue);
250 virtio_gpu_fence_event_process(vgdev, fence_id);
252 list_for_each_entry_safe(entry, tmp, &reclaim_list, list) {
254 virtio_gpu_array_put_free_delayed(vgdev, entry->objs);
255 list_del(&entry->list);
256 free_vbuf(vgdev, entry);
260 void virtio_gpu_dequeue_cursor_func(struct work_struct *work)
262 struct virtio_gpu_device *vgdev =
263 container_of(work, struct virtio_gpu_device,
264 cursorq.dequeue_work);
265 struct list_head reclaim_list;
266 struct virtio_gpu_vbuffer *entry, *tmp;
268 INIT_LIST_HEAD(&reclaim_list);
269 spin_lock(&vgdev->cursorq.qlock);
271 virtqueue_disable_cb(vgdev->cursorq.vq);
272 reclaim_vbufs(vgdev->cursorq.vq, &reclaim_list);
273 } while (!virtqueue_enable_cb(vgdev->cursorq.vq));
274 spin_unlock(&vgdev->cursorq.qlock);
276 list_for_each_entry_safe(entry, tmp, &reclaim_list, list) {
277 list_del(&entry->list);
278 free_vbuf(vgdev, entry);
280 wake_up(&vgdev->cursorq.ack_queue);
283 /* Create sg_table from a vmalloc'd buffer. */
284 static struct sg_table *vmalloc_to_sgt(char *data, uint32_t size, int *sg_ents)
287 struct sg_table *sgt;
288 struct scatterlist *sg;
291 if (WARN_ON(!PAGE_ALIGNED(data)))
294 sgt = kmalloc(sizeof(*sgt), GFP_KERNEL);
298 *sg_ents = DIV_ROUND_UP(size, PAGE_SIZE);
299 ret = sg_alloc_table(sgt, *sg_ents, GFP_KERNEL);
305 for_each_sgtable_sg(sgt, sg, i) {
306 pg = vmalloc_to_page(data);
313 s = min_t(int, PAGE_SIZE, size);
314 sg_set_page(sg, pg, s, 0);
323 static int virtio_gpu_queue_ctrl_sgs(struct virtio_gpu_device *vgdev,
324 struct virtio_gpu_vbuffer *vbuf,
325 struct virtio_gpu_fence *fence,
327 struct scatterlist **sgs,
331 struct virtqueue *vq = vgdev->ctrlq.vq;
334 if (!drm_dev_enter(vgdev->ddev, &idx)) {
335 if (fence && vbuf->objs)
336 virtio_gpu_array_unlock_resv(vbuf->objs);
337 free_vbuf(vgdev, vbuf);
341 if (vgdev->has_indirect)
345 spin_lock(&vgdev->ctrlq.qlock);
347 if (vq->num_free < elemcnt) {
348 spin_unlock(&vgdev->ctrlq.qlock);
349 virtio_gpu_notify(vgdev);
350 wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= elemcnt);
354 /* now that the position of the vbuf in the virtqueue is known, we can
355 * finally set the fence id
358 virtio_gpu_fence_emit(vgdev, virtio_gpu_vbuf_ctrl_hdr(vbuf),
361 virtio_gpu_array_add_fence(vbuf->objs, &fence->f);
362 virtio_gpu_array_unlock_resv(vbuf->objs);
366 ret = virtqueue_add_sgs(vq, sgs, outcnt, incnt, vbuf, GFP_ATOMIC);
369 trace_virtio_gpu_cmd_queue(vq, virtio_gpu_vbuf_ctrl_hdr(vbuf));
371 atomic_inc(&vgdev->pending_commands);
373 spin_unlock(&vgdev->ctrlq.qlock);
379 static int virtio_gpu_queue_fenced_ctrl_buffer(struct virtio_gpu_device *vgdev,
380 struct virtio_gpu_vbuffer *vbuf,
381 struct virtio_gpu_fence *fence)
383 struct scatterlist *sgs[3], vcmd, vout, vresp;
384 struct sg_table *sgt = NULL;
385 int elemcnt = 0, outcnt = 0, incnt = 0, ret;
388 sg_init_one(&vcmd, vbuf->buf, vbuf->size);
394 if (vbuf->data_size) {
395 if (is_vmalloc_addr(vbuf->data_buf)) {
397 sgt = vmalloc_to_sgt(vbuf->data_buf, vbuf->data_size,
400 if (fence && vbuf->objs)
401 virtio_gpu_array_unlock_resv(vbuf->objs);
406 sgs[outcnt] = sgt->sgl;
408 sg_init_one(&vout, vbuf->data_buf, vbuf->data_size);
416 if (vbuf->resp_size) {
417 sg_init_one(&vresp, vbuf->resp_buf, vbuf->resp_size);
419 sgs[outcnt + incnt] = &vresp;
423 ret = virtio_gpu_queue_ctrl_sgs(vgdev, vbuf, fence, elemcnt, sgs, outcnt,
433 void virtio_gpu_notify(struct virtio_gpu_device *vgdev)
437 if (!atomic_read(&vgdev->pending_commands))
440 spin_lock(&vgdev->ctrlq.qlock);
441 atomic_set(&vgdev->pending_commands, 0);
442 notify = virtqueue_kick_prepare(vgdev->ctrlq.vq);
443 spin_unlock(&vgdev->ctrlq.qlock);
446 virtqueue_notify(vgdev->ctrlq.vq);
449 static int virtio_gpu_queue_ctrl_buffer(struct virtio_gpu_device *vgdev,
450 struct virtio_gpu_vbuffer *vbuf)
452 return virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, NULL);
455 static void virtio_gpu_queue_cursor(struct virtio_gpu_device *vgdev,
456 struct virtio_gpu_vbuffer *vbuf)
458 struct virtqueue *vq = vgdev->cursorq.vq;
459 struct scatterlist *sgs[1], ccmd;
460 int idx, ret, outcnt;
463 if (!drm_dev_enter(vgdev->ddev, &idx)) {
464 free_vbuf(vgdev, vbuf);
468 sg_init_one(&ccmd, vbuf->buf, vbuf->size);
472 spin_lock(&vgdev->cursorq.qlock);
474 ret = virtqueue_add_sgs(vq, sgs, outcnt, 0, vbuf, GFP_ATOMIC);
475 if (ret == -ENOSPC) {
476 spin_unlock(&vgdev->cursorq.qlock);
477 wait_event(vgdev->cursorq.ack_queue, vq->num_free >= outcnt);
478 spin_lock(&vgdev->cursorq.qlock);
481 trace_virtio_gpu_cmd_queue(vq,
482 virtio_gpu_vbuf_ctrl_hdr(vbuf));
484 notify = virtqueue_kick_prepare(vq);
487 spin_unlock(&vgdev->cursorq.qlock);
490 virtqueue_notify(vq);
495 /* just create gem objects for userspace and long lived objects,
496 * just use dma_alloced pages for the queue objects?
499 /* create a basic resource */
500 void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
501 struct virtio_gpu_object *bo,
502 struct virtio_gpu_object_params *params,
503 struct virtio_gpu_object_array *objs,
504 struct virtio_gpu_fence *fence)
506 struct virtio_gpu_resource_create_2d *cmd_p;
507 struct virtio_gpu_vbuffer *vbuf;
509 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
510 memset(cmd_p, 0, sizeof(*cmd_p));
513 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_2D);
514 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
515 cmd_p->format = cpu_to_le32(params->format);
516 cmd_p->width = cpu_to_le32(params->width);
517 cmd_p->height = cpu_to_le32(params->height);
519 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
523 static void virtio_gpu_cmd_unref_cb(struct virtio_gpu_device *vgdev,
524 struct virtio_gpu_vbuffer *vbuf)
526 struct virtio_gpu_object *bo;
528 bo = vbuf->resp_cb_data;
529 vbuf->resp_cb_data = NULL;
531 virtio_gpu_cleanup_object(bo);
534 void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
535 struct virtio_gpu_object *bo)
537 struct virtio_gpu_resource_unref *cmd_p;
538 struct virtio_gpu_vbuffer *vbuf;
541 cmd_p = virtio_gpu_alloc_cmd_cb(vgdev, &vbuf, sizeof(*cmd_p),
542 virtio_gpu_cmd_unref_cb);
543 memset(cmd_p, 0, sizeof(*cmd_p));
545 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_UNREF);
546 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
548 vbuf->resp_cb_data = bo;
549 ret = virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
551 virtio_gpu_cleanup_object(bo);
554 void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
555 uint32_t scanout_id, uint32_t resource_id,
556 uint32_t width, uint32_t height,
557 uint32_t x, uint32_t y)
559 struct virtio_gpu_set_scanout *cmd_p;
560 struct virtio_gpu_vbuffer *vbuf;
562 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
563 memset(cmd_p, 0, sizeof(*cmd_p));
565 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SET_SCANOUT);
566 cmd_p->resource_id = cpu_to_le32(resource_id);
567 cmd_p->scanout_id = cpu_to_le32(scanout_id);
568 cmd_p->r.width = cpu_to_le32(width);
569 cmd_p->r.height = cpu_to_le32(height);
570 cmd_p->r.x = cpu_to_le32(x);
571 cmd_p->r.y = cpu_to_le32(y);
573 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
576 void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
577 uint32_t resource_id,
578 uint32_t x, uint32_t y,
579 uint32_t width, uint32_t height,
580 struct virtio_gpu_object_array *objs,
581 struct virtio_gpu_fence *fence)
583 struct virtio_gpu_resource_flush *cmd_p;
584 struct virtio_gpu_vbuffer *vbuf;
586 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
587 memset(cmd_p, 0, sizeof(*cmd_p));
590 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_FLUSH);
591 cmd_p->resource_id = cpu_to_le32(resource_id);
592 cmd_p->r.width = cpu_to_le32(width);
593 cmd_p->r.height = cpu_to_le32(height);
594 cmd_p->r.x = cpu_to_le32(x);
595 cmd_p->r.y = cpu_to_le32(y);
597 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
600 void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
602 uint32_t width, uint32_t height,
603 uint32_t x, uint32_t y,
604 struct virtio_gpu_object_array *objs,
605 struct virtio_gpu_fence *fence)
607 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
608 struct virtio_gpu_transfer_to_host_2d *cmd_p;
609 struct virtio_gpu_vbuffer *vbuf;
610 bool use_dma_api = !virtio_has_dma_quirk(vgdev->vdev);
611 struct virtio_gpu_object_shmem *shmem = to_virtio_gpu_shmem(bo);
614 dma_sync_sgtable_for_device(vgdev->vdev->dev.parent,
615 shmem->pages, DMA_TO_DEVICE);
617 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
618 memset(cmd_p, 0, sizeof(*cmd_p));
621 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D);
622 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
623 cmd_p->offset = cpu_to_le64(offset);
624 cmd_p->r.width = cpu_to_le32(width);
625 cmd_p->r.height = cpu_to_le32(height);
626 cmd_p->r.x = cpu_to_le32(x);
627 cmd_p->r.y = cpu_to_le32(y);
629 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
633 virtio_gpu_cmd_resource_attach_backing(struct virtio_gpu_device *vgdev,
634 uint32_t resource_id,
635 struct virtio_gpu_mem_entry *ents,
637 struct virtio_gpu_fence *fence)
639 struct virtio_gpu_resource_attach_backing *cmd_p;
640 struct virtio_gpu_vbuffer *vbuf;
642 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
643 memset(cmd_p, 0, sizeof(*cmd_p));
645 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING);
646 cmd_p->resource_id = cpu_to_le32(resource_id);
647 cmd_p->nr_entries = cpu_to_le32(nents);
649 vbuf->data_buf = ents;
650 vbuf->data_size = sizeof(*ents) * nents;
652 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
655 static void virtio_gpu_cmd_get_display_info_cb(struct virtio_gpu_device *vgdev,
656 struct virtio_gpu_vbuffer *vbuf)
658 struct virtio_gpu_resp_display_info *resp =
659 (struct virtio_gpu_resp_display_info *)vbuf->resp_buf;
662 spin_lock(&vgdev->display_info_lock);
663 for (i = 0; i < vgdev->num_scanouts; i++) {
664 vgdev->outputs[i].info = resp->pmodes[i];
665 if (resp->pmodes[i].enabled) {
666 DRM_DEBUG("output %d: %dx%d+%d+%d", i,
667 le32_to_cpu(resp->pmodes[i].r.width),
668 le32_to_cpu(resp->pmodes[i].r.height),
669 le32_to_cpu(resp->pmodes[i].r.x),
670 le32_to_cpu(resp->pmodes[i].r.y));
672 DRM_DEBUG("output %d: disabled", i);
676 vgdev->display_info_pending = false;
677 spin_unlock(&vgdev->display_info_lock);
678 wake_up(&vgdev->resp_wq);
680 if (!drm_helper_hpd_irq_event(vgdev->ddev))
681 drm_kms_helper_hotplug_event(vgdev->ddev);
684 static void virtio_gpu_cmd_get_capset_info_cb(struct virtio_gpu_device *vgdev,
685 struct virtio_gpu_vbuffer *vbuf)
687 struct virtio_gpu_get_capset_info *cmd =
688 (struct virtio_gpu_get_capset_info *)vbuf->buf;
689 struct virtio_gpu_resp_capset_info *resp =
690 (struct virtio_gpu_resp_capset_info *)vbuf->resp_buf;
691 int i = le32_to_cpu(cmd->capset_index);
693 spin_lock(&vgdev->display_info_lock);
694 if (vgdev->capsets) {
695 vgdev->capsets[i].id = le32_to_cpu(resp->capset_id);
696 vgdev->capsets[i].max_version = le32_to_cpu(resp->capset_max_version);
697 vgdev->capsets[i].max_size = le32_to_cpu(resp->capset_max_size);
699 DRM_ERROR("invalid capset memory.");
701 spin_unlock(&vgdev->display_info_lock);
702 wake_up(&vgdev->resp_wq);
705 static void virtio_gpu_cmd_capset_cb(struct virtio_gpu_device *vgdev,
706 struct virtio_gpu_vbuffer *vbuf)
708 struct virtio_gpu_get_capset *cmd =
709 (struct virtio_gpu_get_capset *)vbuf->buf;
710 struct virtio_gpu_resp_capset *resp =
711 (struct virtio_gpu_resp_capset *)vbuf->resp_buf;
712 struct virtio_gpu_drv_cap_cache *cache_ent;
714 spin_lock(&vgdev->display_info_lock);
715 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
716 if (cache_ent->version == le32_to_cpu(cmd->capset_version) &&
717 cache_ent->id == le32_to_cpu(cmd->capset_id)) {
718 memcpy(cache_ent->caps_cache, resp->capset_data,
720 /* Copy must occur before is_valid is signalled. */
722 atomic_set(&cache_ent->is_valid, 1);
726 spin_unlock(&vgdev->display_info_lock);
727 wake_up_all(&vgdev->resp_wq);
730 static int virtio_get_edid_block(void *data, u8 *buf,
731 unsigned int block, size_t len)
733 struct virtio_gpu_resp_edid *resp = data;
734 size_t start = block * EDID_LENGTH;
736 if (start + len > le32_to_cpu(resp->size))
738 memcpy(buf, resp->edid + start, len);
742 static void virtio_gpu_cmd_get_edid_cb(struct virtio_gpu_device *vgdev,
743 struct virtio_gpu_vbuffer *vbuf)
745 struct virtio_gpu_cmd_get_edid *cmd =
746 (struct virtio_gpu_cmd_get_edid *)vbuf->buf;
747 struct virtio_gpu_resp_edid *resp =
748 (struct virtio_gpu_resp_edid *)vbuf->resp_buf;
749 uint32_t scanout = le32_to_cpu(cmd->scanout);
750 struct virtio_gpu_output *output;
751 struct edid *new_edid, *old_edid;
753 if (scanout >= vgdev->num_scanouts)
755 output = vgdev->outputs + scanout;
757 new_edid = drm_do_get_edid(&output->conn, virtio_get_edid_block, resp);
758 drm_connector_update_edid_property(&output->conn, new_edid);
760 spin_lock(&vgdev->display_info_lock);
761 old_edid = output->edid;
762 output->edid = new_edid;
763 spin_unlock(&vgdev->display_info_lock);
766 wake_up(&vgdev->resp_wq);
769 int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev)
771 struct virtio_gpu_ctrl_hdr *cmd_p;
772 struct virtio_gpu_vbuffer *vbuf;
775 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_display_info),
780 cmd_p = virtio_gpu_alloc_cmd_resp
781 (vgdev, &virtio_gpu_cmd_get_display_info_cb, &vbuf,
782 sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_display_info),
784 memset(cmd_p, 0, sizeof(*cmd_p));
786 vgdev->display_info_pending = true;
787 cmd_p->type = cpu_to_le32(VIRTIO_GPU_CMD_GET_DISPLAY_INFO);
788 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
792 int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx)
794 struct virtio_gpu_get_capset_info *cmd_p;
795 struct virtio_gpu_vbuffer *vbuf;
798 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset_info),
803 cmd_p = virtio_gpu_alloc_cmd_resp
804 (vgdev, &virtio_gpu_cmd_get_capset_info_cb, &vbuf,
805 sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_capset_info),
807 memset(cmd_p, 0, sizeof(*cmd_p));
809 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET_INFO);
810 cmd_p->capset_index = cpu_to_le32(idx);
811 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
815 int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
816 int idx, int version,
817 struct virtio_gpu_drv_cap_cache **cache_p)
819 struct virtio_gpu_get_capset *cmd_p;
820 struct virtio_gpu_vbuffer *vbuf;
822 struct virtio_gpu_drv_cap_cache *cache_ent;
823 struct virtio_gpu_drv_cap_cache *search_ent;
828 if (idx >= vgdev->num_capsets)
831 if (version > vgdev->capsets[idx].max_version)
834 cache_ent = kzalloc(sizeof(*cache_ent), GFP_KERNEL);
838 max_size = vgdev->capsets[idx].max_size;
839 cache_ent->caps_cache = kmalloc(max_size, GFP_KERNEL);
840 if (!cache_ent->caps_cache) {
845 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset) + max_size,
848 kfree(cache_ent->caps_cache);
853 cache_ent->version = version;
854 cache_ent->id = vgdev->capsets[idx].id;
855 atomic_set(&cache_ent->is_valid, 0);
856 cache_ent->size = max_size;
857 spin_lock(&vgdev->display_info_lock);
858 /* Search while under lock in case it was added by another task. */
859 list_for_each_entry(search_ent, &vgdev->cap_cache, head) {
860 if (search_ent->id == vgdev->capsets[idx].id &&
861 search_ent->version == version) {
862 *cache_p = search_ent;
867 list_add_tail(&cache_ent->head, &vgdev->cap_cache);
868 spin_unlock(&vgdev->display_info_lock);
871 /* Entry was found, so free everything that was just created. */
873 kfree(cache_ent->caps_cache);
878 cmd_p = virtio_gpu_alloc_cmd_resp
879 (vgdev, &virtio_gpu_cmd_capset_cb, &vbuf, sizeof(*cmd_p),
880 sizeof(struct virtio_gpu_resp_capset) + max_size,
882 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET);
883 cmd_p->capset_id = cpu_to_le32(vgdev->capsets[idx].id);
884 cmd_p->capset_version = cpu_to_le32(version);
885 *cache_p = cache_ent;
886 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
891 int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev)
893 struct virtio_gpu_cmd_get_edid *cmd_p;
894 struct virtio_gpu_vbuffer *vbuf;
898 if (WARN_ON(!vgdev->has_edid))
901 for (scanout = 0; scanout < vgdev->num_scanouts; scanout++) {
902 resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_edid),
907 cmd_p = virtio_gpu_alloc_cmd_resp
908 (vgdev, &virtio_gpu_cmd_get_edid_cb, &vbuf,
909 sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_edid),
911 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_EDID);
912 cmd_p->scanout = cpu_to_le32(scanout);
913 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
919 void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
920 uint32_t nlen, const char *name)
922 struct virtio_gpu_ctx_create *cmd_p;
923 struct virtio_gpu_vbuffer *vbuf;
925 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
926 memset(cmd_p, 0, sizeof(*cmd_p));
928 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_CREATE);
929 cmd_p->hdr.ctx_id = cpu_to_le32(id);
930 cmd_p->nlen = cpu_to_le32(nlen);
931 strncpy(cmd_p->debug_name, name, sizeof(cmd_p->debug_name) - 1);
932 cmd_p->debug_name[sizeof(cmd_p->debug_name) - 1] = 0;
933 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
936 void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
939 struct virtio_gpu_ctx_destroy *cmd_p;
940 struct virtio_gpu_vbuffer *vbuf;
942 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
943 memset(cmd_p, 0, sizeof(*cmd_p));
945 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DESTROY);
946 cmd_p->hdr.ctx_id = cpu_to_le32(id);
947 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
950 void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
952 struct virtio_gpu_object_array *objs)
954 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
955 struct virtio_gpu_ctx_resource *cmd_p;
956 struct virtio_gpu_vbuffer *vbuf;
958 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
959 memset(cmd_p, 0, sizeof(*cmd_p));
962 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE);
963 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
964 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
965 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
968 void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
970 struct virtio_gpu_object_array *objs)
972 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
973 struct virtio_gpu_ctx_resource *cmd_p;
974 struct virtio_gpu_vbuffer *vbuf;
976 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
977 memset(cmd_p, 0, sizeof(*cmd_p));
980 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE);
981 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
982 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
983 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
987 virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
988 struct virtio_gpu_object *bo,
989 struct virtio_gpu_object_params *params,
990 struct virtio_gpu_object_array *objs,
991 struct virtio_gpu_fence *fence)
993 struct virtio_gpu_resource_create_3d *cmd_p;
994 struct virtio_gpu_vbuffer *vbuf;
996 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
997 memset(cmd_p, 0, sizeof(*cmd_p));
1000 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_3D);
1001 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1002 cmd_p->format = cpu_to_le32(params->format);
1003 cmd_p->width = cpu_to_le32(params->width);
1004 cmd_p->height = cpu_to_le32(params->height);
1006 cmd_p->target = cpu_to_le32(params->target);
1007 cmd_p->bind = cpu_to_le32(params->bind);
1008 cmd_p->depth = cpu_to_le32(params->depth);
1009 cmd_p->array_size = cpu_to_le32(params->array_size);
1010 cmd_p->last_level = cpu_to_le32(params->last_level);
1011 cmd_p->nr_samples = cpu_to_le32(params->nr_samples);
1012 cmd_p->flags = cpu_to_le32(params->flags);
1014 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
1019 void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
1021 uint64_t offset, uint32_t level,
1023 uint32_t layer_stride,
1024 struct drm_virtgpu_3d_box *box,
1025 struct virtio_gpu_object_array *objs,
1026 struct virtio_gpu_fence *fence)
1028 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1029 struct virtio_gpu_transfer_host_3d *cmd_p;
1030 struct virtio_gpu_vbuffer *vbuf;
1031 bool use_dma_api = !virtio_has_dma_quirk(vgdev->vdev);
1033 if (virtio_gpu_is_shmem(bo) && use_dma_api) {
1034 struct virtio_gpu_object_shmem *shmem = to_virtio_gpu_shmem(bo);
1035 dma_sync_sgtable_for_device(vgdev->vdev->dev.parent,
1036 shmem->pages, DMA_TO_DEVICE);
1039 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1040 memset(cmd_p, 0, sizeof(*cmd_p));
1044 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D);
1045 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
1046 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1047 convert_to_hw_box(&cmd_p->box, box);
1048 cmd_p->offset = cpu_to_le64(offset);
1049 cmd_p->level = cpu_to_le32(level);
1050 cmd_p->stride = cpu_to_le32(stride);
1051 cmd_p->layer_stride = cpu_to_le32(layer_stride);
1053 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
1056 void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
1058 uint64_t offset, uint32_t level,
1060 uint32_t layer_stride,
1061 struct drm_virtgpu_3d_box *box,
1062 struct virtio_gpu_object_array *objs,
1063 struct virtio_gpu_fence *fence)
1065 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1066 struct virtio_gpu_transfer_host_3d *cmd_p;
1067 struct virtio_gpu_vbuffer *vbuf;
1069 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1070 memset(cmd_p, 0, sizeof(*cmd_p));
1074 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D);
1075 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
1076 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1077 convert_to_hw_box(&cmd_p->box, box);
1078 cmd_p->offset = cpu_to_le64(offset);
1079 cmd_p->level = cpu_to_le32(level);
1080 cmd_p->stride = cpu_to_le32(stride);
1081 cmd_p->layer_stride = cpu_to_le32(layer_stride);
1083 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
1086 void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
1087 void *data, uint32_t data_size,
1089 struct virtio_gpu_object_array *objs,
1090 struct virtio_gpu_fence *fence)
1092 struct virtio_gpu_cmd_submit *cmd_p;
1093 struct virtio_gpu_vbuffer *vbuf;
1095 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1096 memset(cmd_p, 0, sizeof(*cmd_p));
1098 vbuf->data_buf = data;
1099 vbuf->data_size = data_size;
1102 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SUBMIT_3D);
1103 cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id);
1104 cmd_p->size = cpu_to_le32(data_size);
1106 virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, fence);
1109 void virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
1110 struct virtio_gpu_object *obj,
1111 struct virtio_gpu_mem_entry *ents,
1114 virtio_gpu_cmd_resource_attach_backing(vgdev, obj->hw_res_handle,
1118 void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
1119 struct virtio_gpu_output *output)
1121 struct virtio_gpu_vbuffer *vbuf;
1122 struct virtio_gpu_update_cursor *cur_p;
1124 output->cursor.pos.scanout_id = cpu_to_le32(output->index);
1125 cur_p = virtio_gpu_alloc_cursor(vgdev, &vbuf);
1126 memcpy(cur_p, &output->cursor, sizeof(output->cursor));
1127 virtio_gpu_queue_cursor(vgdev, vbuf);
1130 static void virtio_gpu_cmd_resource_uuid_cb(struct virtio_gpu_device *vgdev,
1131 struct virtio_gpu_vbuffer *vbuf)
1133 struct virtio_gpu_object *obj =
1134 gem_to_virtio_gpu_obj(vbuf->objs->objs[0]);
1135 struct virtio_gpu_resp_resource_uuid *resp =
1136 (struct virtio_gpu_resp_resource_uuid *)vbuf->resp_buf;
1137 uint32_t resp_type = le32_to_cpu(resp->hdr.type);
1139 spin_lock(&vgdev->resource_export_lock);
1140 WARN_ON(obj->uuid_state != STATE_INITIALIZING);
1142 if (resp_type == VIRTIO_GPU_RESP_OK_RESOURCE_UUID &&
1143 obj->uuid_state == STATE_INITIALIZING) {
1144 import_uuid(&obj->uuid, resp->uuid);
1145 obj->uuid_state = STATE_OK;
1147 obj->uuid_state = STATE_ERR;
1149 spin_unlock(&vgdev->resource_export_lock);
1151 wake_up_all(&vgdev->resp_wq);
1155 virtio_gpu_cmd_resource_assign_uuid(struct virtio_gpu_device *vgdev,
1156 struct virtio_gpu_object_array *objs)
1158 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1159 struct virtio_gpu_resource_assign_uuid *cmd_p;
1160 struct virtio_gpu_vbuffer *vbuf;
1161 struct virtio_gpu_resp_resource_uuid *resp_buf;
1163 resp_buf = kzalloc(sizeof(*resp_buf), GFP_KERNEL);
1165 spin_lock(&vgdev->resource_export_lock);
1166 bo->uuid_state = STATE_ERR;
1167 spin_unlock(&vgdev->resource_export_lock);
1168 virtio_gpu_array_put_free(objs);
1172 cmd_p = virtio_gpu_alloc_cmd_resp
1173 (vgdev, virtio_gpu_cmd_resource_uuid_cb, &vbuf, sizeof(*cmd_p),
1174 sizeof(struct virtio_gpu_resp_resource_uuid), resp_buf);
1175 memset(cmd_p, 0, sizeof(*cmd_p));
1177 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID);
1178 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1181 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1185 static void virtio_gpu_cmd_resource_map_cb(struct virtio_gpu_device *vgdev,
1186 struct virtio_gpu_vbuffer *vbuf)
1188 struct virtio_gpu_object *bo =
1189 gem_to_virtio_gpu_obj(vbuf->objs->objs[0]);
1190 struct virtio_gpu_resp_map_info *resp =
1191 (struct virtio_gpu_resp_map_info *)vbuf->resp_buf;
1192 struct virtio_gpu_object_vram *vram = to_virtio_gpu_vram(bo);
1193 uint32_t resp_type = le32_to_cpu(resp->hdr.type);
1195 spin_lock(&vgdev->host_visible_lock);
1197 if (resp_type == VIRTIO_GPU_RESP_OK_MAP_INFO) {
1198 vram->map_info = resp->map_info;
1199 vram->map_state = STATE_OK;
1201 vram->map_state = STATE_ERR;
1204 spin_unlock(&vgdev->host_visible_lock);
1205 wake_up_all(&vgdev->resp_wq);
1208 int virtio_gpu_cmd_map(struct virtio_gpu_device *vgdev,
1209 struct virtio_gpu_object_array *objs, uint64_t offset)
1211 struct virtio_gpu_resource_map_blob *cmd_p;
1212 struct virtio_gpu_object *bo = gem_to_virtio_gpu_obj(objs->objs[0]);
1213 struct virtio_gpu_vbuffer *vbuf;
1214 struct virtio_gpu_resp_map_info *resp_buf;
1216 resp_buf = kzalloc(sizeof(*resp_buf), GFP_KERNEL);
1220 cmd_p = virtio_gpu_alloc_cmd_resp
1221 (vgdev, virtio_gpu_cmd_resource_map_cb, &vbuf, sizeof(*cmd_p),
1222 sizeof(struct virtio_gpu_resp_map_info), resp_buf);
1223 memset(cmd_p, 0, sizeof(*cmd_p));
1225 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB);
1226 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1227 cmd_p->offset = cpu_to_le64(offset);
1230 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1234 void virtio_gpu_cmd_unmap(struct virtio_gpu_device *vgdev,
1235 struct virtio_gpu_object *bo)
1237 struct virtio_gpu_resource_unmap_blob *cmd_p;
1238 struct virtio_gpu_vbuffer *vbuf;
1240 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1241 memset(cmd_p, 0, sizeof(*cmd_p));
1243 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB);
1244 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1246 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1250 virtio_gpu_cmd_resource_create_blob(struct virtio_gpu_device *vgdev,
1251 struct virtio_gpu_object *bo,
1252 struct virtio_gpu_object_params *params,
1253 struct virtio_gpu_mem_entry *ents,
1256 struct virtio_gpu_resource_create_blob *cmd_p;
1257 struct virtio_gpu_vbuffer *vbuf;
1259 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1260 memset(cmd_p, 0, sizeof(*cmd_p));
1262 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB);
1263 cmd_p->hdr.ctx_id = cpu_to_le32(params->ctx_id);
1264 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1265 cmd_p->blob_mem = cpu_to_le32(params->blob_mem);
1266 cmd_p->blob_flags = cpu_to_le32(params->blob_flags);
1267 cmd_p->blob_id = cpu_to_le64(params->blob_id);
1268 cmd_p->size = cpu_to_le64(params->size);
1269 cmd_p->nr_entries = cpu_to_le32(nents);
1271 vbuf->data_buf = ents;
1272 vbuf->data_size = sizeof(*ents) * nents;
1274 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);
1278 void virtio_gpu_cmd_set_scanout_blob(struct virtio_gpu_device *vgdev,
1279 uint32_t scanout_id,
1280 struct virtio_gpu_object *bo,
1281 struct drm_framebuffer *fb,
1282 uint32_t width, uint32_t height,
1283 uint32_t x, uint32_t y)
1286 struct virtio_gpu_set_scanout_blob *cmd_p;
1287 struct virtio_gpu_vbuffer *vbuf;
1288 uint32_t format = virtio_gpu_translate_format(fb->format->format);
1290 cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p));
1291 memset(cmd_p, 0, sizeof(*cmd_p));
1293 cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SET_SCANOUT_BLOB);
1294 cmd_p->resource_id = cpu_to_le32(bo->hw_res_handle);
1295 cmd_p->scanout_id = cpu_to_le32(scanout_id);
1297 cmd_p->format = cpu_to_le32(format);
1298 cmd_p->width = cpu_to_le32(fb->width);
1299 cmd_p->height = cpu_to_le32(fb->height);
1301 for (i = 0; i < 4; i++) {
1302 cmd_p->strides[i] = cpu_to_le32(fb->pitches[i]);
1303 cmd_p->offsets[i] = cpu_to_le32(fb->offsets[i]);
1306 cmd_p->r.width = cpu_to_le32(width);
1307 cmd_p->r.height = cpu_to_le32(height);
1308 cmd_p->r.x = cpu_to_le32(x);
1309 cmd_p->r.y = cpu_to_le32(y);
1311 virtio_gpu_queue_ctrl_buffer(vgdev, vbuf);