drivers/gpu/drm/verisilicon/inno_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   4  *    Zheng Yang <zhengyang@rock-chips.com>
   5  *    Yakir Yang <ykk@rock-chips.com>
   6  */
   7
   8 #include <linux/irq.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/err.h>
  12 #include <linux/hdmi.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/module.h>
  15 #include <linux/mutex.h>
  16 #include <linux/of_device.h>
  17 #include <linux/component.h>
  18 #include<linux/reset.h>
  19
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_edid.h>
  22 #include <drm/drm_of.h>
  23 #include <drm/drm_probe_helper.h>
  24 #include <drm/drm_simple_kms_helper.h>
  25 #include "vs_clock.h"
  26
  27 #include "vs_drv.h"
  28
  29 #include "inno_hdmi.h"
  30
  31 #include "fmux_macro.h"
  32 #include "sys_iomux_cfg_macro.h"
  33
  34 #define to_inno_hdmi(x) container_of(x, struct inno_hdmi, x)
  35
  36 struct hdmi_data_info {
  37         int vic;
  38         bool sink_is_hdmi;
  39         bool sink_has_audio;
  40         unsigned int enc_in_format;
  41         unsigned int enc_out_format;
  42         unsigned int colorimetry;
  43 };
  44
  45 struct inno_hdmi_i2c {
  46         struct i2c_adapter adap;
  47
  48         u8 ddc_addr;
  49         u8 segment_addr;
  50
  51         struct mutex lock;
  52         struct completion cmp;
  53 };
  54
  55 struct inno_hdmi {
  56         struct device *dev;
  57         struct drm_device *drm_dev;
  58
  59         int irq;
  60         struct clk *pclk;
  61         struct clk *sys_clk;
  62         struct clk *mclk;
  63         struct clk *bclk;
  64         struct reset_control *tx_rst;
  65         void __iomem *regs;
  66
  67         struct drm_connector    connector;
  68         struct drm_encoder      encoder;
  69
  70         struct inno_hdmi_i2c *i2c;
  71         struct i2c_adapter *ddc;
  72
  73         unsigned int tmds_rate;
  74
  75         struct hdmi_data_info   hdmi_data;
  76         struct drm_display_mode previous_mode;
  77 };
  78
  79 enum {
  80         CSC_ITU601_16_235_TO_RGB_0_255_8BIT,
  81         CSC_ITU601_0_255_TO_RGB_0_255_8BIT,
  82         CSC_ITU709_16_235_TO_RGB_0_255_8BIT,
  83         CSC_RGB_0_255_TO_ITU601_16_235_8BIT,
  84         CSC_RGB_0_255_TO_ITU709_16_235_8BIT,
  85         CSC_RGB_0_255_TO_RGB_16_235_8BIT,
  86 };
  87
  88 static const char coeff_csc[][24] = {
  89         /*
  90          * YUV2RGB:601 SD mode(Y[16:235], UV[16:240], RGB[0:255]):
  91          *   R = 1.164*Y + 1.596*V - 204
  92          *   G = 1.164*Y - 0.391*U - 0.813*V + 154
  93          *   B = 1.164*Y + 2.018*U - 258
  94          */
  95         {
  96                 0x04, 0xa7, 0x00, 0x00, 0x06, 0x62, 0x02, 0xcc,
  97                 0x04, 0xa7, 0x11, 0x90, 0x13, 0x40, 0x00, 0x9a,
  98                 0x04, 0xa7, 0x08, 0x12, 0x00, 0x00, 0x03, 0x02
  99         },
 100         /*
 101          * YUV2RGB:601 SD mode(YUV[0:255],RGB[0:255]):
 102          *   R = Y + 1.402*V - 248
 103          *   G = Y - 0.344*U - 0.714*V + 135
 104          *   B = Y + 1.772*U - 227
 105          */
 106         {
 107                 0x04, 0x00, 0x00, 0x00, 0x05, 0x9b, 0x02, 0xf8,
 108                 0x04, 0x00, 0x11, 0x60, 0x12, 0xdb, 0x00, 0x87,
 109                 0x04, 0x00, 0x07, 0x16, 0x00, 0x00, 0x02, 0xe3
 110         },
 111         /*
 112          * YUV2RGB:709 HD mode(Y[16:235],UV[16:240],RGB[0:255]):
 113          *   R = 1.164*Y + 1.793*V - 248
 114          *   G = 1.164*Y - 0.213*U - 0.534*V + 77
 115          *   B = 1.164*Y + 2.115*U - 289
 116          */
 117         {
 118                 0x04, 0xa7, 0x00, 0x00, 0x07, 0x2c, 0x02, 0xf8,
 119                 0x04, 0xa7, 0x10, 0xda, 0x12, 0x22, 0x00, 0x4d,
 120                 0x04, 0xa7, 0x08, 0x74, 0x00, 0x00, 0x03, 0x21
 121         },
 122
 123         /*
 124          * RGB2YUV:601 SD mode:
 125          *   Cb = -0.291G - 0.148R + 0.439B + 128
 126          *   Y  = 0.504G  + 0.257R + 0.098B + 16
 127          *   Cr = -0.368G + 0.439R - 0.071B + 128
 128          */
 129         {
 130                 0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80,
 131                 0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e,
 132                 0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80
 133         },
 134         /*
 135          * RGB2YUV:709 HD mode:
 136          *   Cb = - 0.338G - 0.101R + 0.439B + 128
 137          *   Y  = 0.614G   + 0.183R + 0.062B + 16
 138          *   Cr = - 0.399G + 0.439R - 0.040B + 128
 139          */
 140         {
 141                 0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80,
 142                 0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10,
 143                 0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80
 144         },
 145         /*
 146          * RGB[0:255]2RGB[16:235]:
 147          *   R' = R x (235-16)/255 + 16;
 148          *   G' = G x (235-16)/255 + 16;
 149          *   B' = B x (235-16)/255 + 16;
 150          */
 151         {
 152                 0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10,
 153                 0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
 154                 0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10
 155         },
 156 };
 157
 158 static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset)
 159 {
 160         return readl_relaxed(hdmi->regs + (offset) * 0x04);
 161 }
 162
 163 static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val)
 164 {
 165         writel_relaxed(val, hdmi->regs + (offset) * 0x04);
 166 }
 167
 168 static inline void hdmi_modb(struct inno_hdmi *hdmi, u16 offset,
 169                              u32 msk, u32 val)
 170 {
 171         u8 temp = hdmi_readb(hdmi, offset) & ~msk;
 172
 173         temp |= val & msk;
 174         hdmi_writeb(hdmi, offset, temp);
 175 }
 176
 177 void inno_hdmi_srcdata_fmt_config(int panel_sel, int dpi_dp_sel, int dpi_dp_depth)
 178 {
 179         SET_U2_DISPLAY_PANEL_MUX_PANEL_SEL(panel_sel);
 180         SET_U0_HDMI_DATA_MAPPING_DPI_DP_SEL(dpi_dp_sel);
 181         SET_U0_HDMI_DATA_MAPPING_DPI_BIT_DEPTH(dpi_dp_depth);
 182 }
 183
 184 static void inno_hdmi_power_up(struct inno_hdmi *hdmi)
 185 {
 186         int val;
 187
 188         val = readl_relaxed(hdmi->regs + (0x1b0) * 0x04);
 189         val |= 0x4;
 190         writel_relaxed(val, hdmi->regs + (0x1b0) * 0x04);
 191         writel_relaxed(0xf, hdmi->regs + (0x1cc) * 0x04);
 192
 193         /*turn on pre-PLL*/
 194         val = readl_relaxed(hdmi->regs + (0x1a0) * 0x04);
 195         val &= ~(0x1);
 196         writel_relaxed(val, hdmi->regs + (0x1a0) * 0x04);
 197         /*turn on post-PLL*/
 198         val = readl_relaxed(hdmi->regs + (0x1aa) * 0x04);
 199         val &= ~(0x1);
 200         writel_relaxed(val, hdmi->regs + (0x1aa) * 0x04);
 201
 202         /*wait for pre-PLL and post-PLL lock*/
 203         //while(!(hdmi_read(word_align(0x1a9)) & 0x1));
 204         //while(!(hdmi_read(word_align(0x1af)) & 0x1));
 205         while (!(readl_relaxed(hdmi->regs + (0x1a9) * 0x04) & 0x1))
 206         ;
 207         while (!(readl_relaxed(hdmi->regs + (0x1af) * 0x04) & 0x1))
 208         ;
 209
 210         /*turn on LDO*/
 211         writel_relaxed(0x7, hdmi->regs + (0x1b4) * 0x04);
 212         /*turn on serializer*/
 213         writel_relaxed(0x70, hdmi->regs + (0x1be) * 0x04);
 214 }
 215
 216 static void inno_hdmi_tx_phy_power_down(struct inno_hdmi *hdmi)
 217 {
 218         //hdmi_write(0x63, word_align(0x00));
 219         writel_relaxed(0x63, hdmi->regs + (0x00) * 0x04);
 220 }
 221
 222 typedef struct register_value {
 223         u16 reg;
 224         u8 value;
 225 } reg_value_t;
 226
 227 #if 0
 228 static void inno_hdmi_config_640x480p60(struct inno_hdmi *hdmi)
 229 {
 230         const reg_value_t cfg_pll_data[] = {
 231                 /* config pll: 640x480p, 60hz*/
 232                 {0x1a0, 0x01},
 233                 //{0x1aa, 0x0f},
 234                 {0x1a1, 0x01},
 235                 {0x1a2, 0xf0},
 236                 {0x1a3, 0x64},
 237                 {0x1a4, 0x2f},
 238                 //{0x1a4, 0x2a},
 239                 {0x1a5, 0x6c},
 240                 {0x1a6, 0x64},
 241                 {0x1ab, 0x01},
 242                 {0x1ac, 0x50},
 243                 //{0x1ad, 0x07},
 244                 {0x1ad, 0x0d},
 245                 {0x1aa, 0x0e},
 246                 {0x1a0, 0x00},
 247         };
 248
 249         int i;
 250
 251         for (i = 0; i < sizeof(cfg_pll_data) / sizeof(reg_value_t); i++) {
 252                 //hdmi_write(cfg_pll_data[i].value, word_align(cfg_pll_data[i].reg));
 253                 writel_relaxed(cfg_pll_data[i].value, hdmi->regs + (cfg_pll_data[i].reg) * 0x04);
 254         }
 255         return;
 256 }
 257 #endif
 258
 259 static void inno_hdmi_config_1920x1080p60(struct inno_hdmi *hdmi)
 260 {
 261
 262         const reg_value_t cfg_pll_data[] = {
 263                 /* config pll: 1080p, 60hz*/
 264                 {0x1a0, 0x01},
 265                 {0x1aa, 0x0f},
 266                 {0x1a1, 0x01},
 267                 {0x1a2, 0xf0},
 268                 {0x1a3, 0x63},
 269                 {0x1a4, 0x15},
 270                 {0x1a5, 0x41},
 271                 {0x1a6, 0x42},
 272                 {0x1ab, 0x01},
 273                 {0x1ac, 0x0a},
 274                 {0x1ad, 0x00},
 275                 {0x1aa, 0x0e},
 276                 {0x1a0, 0x00},
 277         };
 278
 279         int i;
 280         for (i = 0; i < sizeof(cfg_pll_data) / sizeof(reg_value_t); i++)
 281                 writel_relaxed(cfg_pll_data[i].value, hdmi->regs + (cfg_pll_data[i].reg) * 0x04);
 282
 283         return;
 284 }
 285
 286 static void inno_hdmi_tx_ctrl(struct inno_hdmi *hdmi)
 287 {
 288         writel_relaxed(0x06, hdmi->regs + (0x9f) * 0x04);
 289         writel_relaxed(0x82, hdmi->regs + (0xa0) * 0x04);
 290         writel_relaxed(0xd, hdmi->regs + (0xa2) * 0x04);
 291         writel_relaxed(0x0, hdmi->regs + (0xa3) * 0x04);
 292         writel_relaxed(0x0, hdmi->regs + (0xa4) * 0x04);
 293         writel_relaxed(0x8, hdmi->regs + (0xa5) * 0x04);
 294         writel_relaxed(0x70, hdmi->regs + (0xa6) * 0x04);
 295         writel_relaxed(0x10, hdmi->regs + (0xa7) * 0x04);
 296         writel_relaxed(0x10, hdmi->regs + (0xc9) * 0x04);
 297 }
 298
 299 static void inno_hdmi_tx_phy_param_config(struct inno_hdmi *hdmi)
 300 {
 301
 302         //640x480p60
 303         //vic = VIC_640x480p60;
 304         //inno_hdmi_config_640x480p60(hdmi);
 305         //640x480p60
 306         //1920x1080p60
 307         inno_hdmi_config_1920x1080p60(hdmi);
 308         //1920x1080p60
 309         inno_hdmi_tx_ctrl(hdmi);
 310
 311     return;
 312 }
 313
 314 static void inno_hdmi_tx_phy_power_on(struct inno_hdmi *hdmi)
 315 {
 316         const reg_value_t pwon_data[] = {
 317                 {0x00, 0x61},
 318                 //{0xce, 0x00},//data sync
 319                 //{0xce, 0x01}
 320         };
 321         int i;
 322         for (i = 0; i < sizeof(pwon_data)/sizeof(reg_value_t); i++) {
 323                 //hdmi_write(pwon_data[i].value, word_align(pwon_data[i].reg));
 324                 writel_relaxed(pwon_data[i].value, hdmi->regs + (pwon_data[i].reg) * 0x04);
 325         }
 326         return;
 327 }
 328
 329 void inno_hdmi_tmds_driver_on(struct inno_hdmi *hdmi)
 330 {
 331         writel_relaxed(0x8f, hdmi->regs + (0x1b2) * 0x04);
 332         printk("HDMI tmds encode driver on\r\n");
 333 }
 334
 335
 336 static void inno_hdmi_i2c_init(struct inno_hdmi *hdmi)
 337 {
 338         int ddc_bus_freq;
 339
 340         ddc_bus_freq = (hdmi->tmds_rate >> 2) / HDMI_SCL_RATE;
 341
 342         hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
 343         hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
 344
 345         /* Clear the EDID interrupt flag and mute the interrupt */
 346         hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
 347         hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
 348 }
 349
 350 static void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable)
 351 {
 352         if (enable)
 353                 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON);
 354         else
 355                 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF);
 356 }
 357
 358 static void inno_hdmi_set_pwr_mode(struct inno_hdmi *hdmi, int mode)
 359 {
 360         switch (mode) {
 361         case NORMAL:
 362                 inno_hdmi_sys_power(hdmi, true);
 363                 break;
 364
 365         case LOWER_PWR:
 366                 inno_hdmi_sys_power(hdmi, false);
 367                 break;
 368
 369         default:
 370                 DRM_DEV_ERROR(hdmi->dev, "Unknown power mode %d\n", mode);
 371         }
 372 }
 373
 374 static void inno_hdmi_init(struct inno_hdmi *hdmi)
 375 {
 376         writel_relaxed(0x3, hdmi->regs + (0x100) * 0x04);
 377         writel_relaxed(0xc, hdmi->regs + (0x8) * 0x04);
 378
 379         inno_hdmi_power_up(hdmi);
 380         inno_hdmi_tx_phy_power_down(hdmi);
 381         inno_hdmi_tx_phy_param_config(hdmi);
 382         //inno_hdmi_wait_pll_clk_locked();
 383
 384         inno_hdmi_tx_phy_power_on(hdmi);
 385         inno_hdmi_tmds_driver_on(hdmi);
 386
 387         writel_relaxed(0x0, hdmi->regs + (0xce) * 0x04);
 388         writel_relaxed(0x1, hdmi->regs + (0xce) * 0x04);
 389
 390 }
 391
 392 static void inno_hdmi_reset(struct inno_hdmi *hdmi)
 393 {
 394         u32 val;
 395         u32 msk;
 396
 397         hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL);
 398         udelay(100);
 399
 400         hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG);
 401         udelay(100);
 402
 403         msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL;
 404         val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH;
 405         hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val);
 406
 407         inno_hdmi_set_pwr_mode(hdmi, NORMAL);
 408 }
 409
 410 static int inno_hdmi_upload_frame(struct inno_hdmi *hdmi, int setup_rc,
 411                                   union hdmi_infoframe *frame, u32 frame_index,
 412                                   u32 mask, u32 disable, u32 enable)
 413 {
 414
 415         if (mask)
 416                 hdmi_modb(hdmi, HDMI_PACKET_SEND_AUTO, mask, disable);
 417
 418         hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, frame_index);
 419
 420         if (setup_rc >= 0) {
 421                 u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
 422                 ssize_t rc, i;
 423
 424                 rc = hdmi_infoframe_pack(frame, packed_frame,
 425                                          sizeof(packed_frame));
 426                 if (rc < 0)
 427                         return rc;
 428
 429                 for (i = 0; i < rc; i++)
 430                         hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i,
 431                                     packed_frame[i]);
 432
 433                 if (mask)
 434                         hdmi_modb(hdmi, HDMI_PACKET_SEND_AUTO, mask, enable);
 435         }
 436
 437         return setup_rc;
 438 }
 439
 440 static int inno_hdmi_config_video_vsi(struct inno_hdmi *hdmi,
 441                                       struct drm_display_mode *mode)
 442 {
 443         union hdmi_infoframe frame;
 444         int rc;
 445
 446         rc = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 447                                                          &hdmi->connector,
 448                                                          mode);
 449
 450         return inno_hdmi_upload_frame(hdmi, rc, &frame, INFOFRAME_VSI,
 451                 m_PACKET_VSI_EN, v_PACKET_VSI_EN(0), v_PACKET_VSI_EN(1));
 452 }
 453
 454 static int inno_hdmi_config_video_avi(struct inno_hdmi *hdmi,
 455                                       struct drm_display_mode *mode)
 456 {
 457         union hdmi_infoframe frame;
 458         int rc;
 459
 460         rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 461                                                       &hdmi->connector,
 462                                                       mode);
 463
 464         if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444)
 465                 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
 466         else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422)
 467                 frame.avi.colorspace = HDMI_COLORSPACE_YUV422;
 468         else
 469                 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
 470
 471         return inno_hdmi_upload_frame(hdmi, rc, &frame, INFOFRAME_AVI, 0, 0, 0);
 472 }
 473
 474 static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi)
 475 {
 476         struct hdmi_data_info *data = &hdmi->hdmi_data;
 477         int c0_c2_change = 0;
 478         int csc_enable = 0;
 479         int csc_mode = 0;
 480         int auto_csc = 0;
 481         int value;
 482         int i;
 483
 484         /* Input video mode is SDR RGB24bit, data enable signal from external */
 485         hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL |
 486                     v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444));
 487
 488         /* Input color hardcode to RGB, and output color hardcode to RGB888 */
 489         value = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) |
 490                 v_VIDEO_OUTPUT_COLOR(0) |
 491                 v_VIDEO_INPUT_CSP(0);
 492         hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value);
 493
 494         if (data->enc_in_format == data->enc_out_format) {
 495                 if ((data->enc_in_format == HDMI_COLORSPACE_RGB) ||
 496                     (data->enc_in_format >= HDMI_COLORSPACE_YUV444)) {
 497                         value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1);
 498                         hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
 499
 500                         hdmi_modb(hdmi, HDMI_VIDEO_CONTRL,
 501                                   m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP,
 502                                   v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) |
 503                                   v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE));
 504                         return 0;
 505                 }
 506         }
 507
 508         if (data->colorimetry == HDMI_COLORIMETRY_ITU_601) {
 509                 if ((data->enc_in_format == HDMI_COLORSPACE_RGB) &&
 510                     (data->enc_out_format == HDMI_COLORSPACE_YUV444)) {
 511                         csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
 512                         auto_csc = AUTO_CSC_DISABLE;
 513                         c0_c2_change = C0_C2_CHANGE_DISABLE;
 514                         csc_enable = v_CSC_ENABLE;
 515                 } else if ((data->enc_in_format == HDMI_COLORSPACE_YUV444) &&
 516                            (data->enc_out_format == HDMI_COLORSPACE_RGB)) {
 517                         csc_mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT;
 518                         auto_csc = AUTO_CSC_ENABLE;
 519                         c0_c2_change = C0_C2_CHANGE_DISABLE;
 520                         csc_enable = v_CSC_DISABLE;
 521                 }
 522         } else {
 523                 if ((data->enc_in_format == HDMI_COLORSPACE_RGB) &&
 524                     (data->enc_out_format == HDMI_COLORSPACE_YUV444)) {
 525                         csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
 526                         auto_csc = AUTO_CSC_DISABLE;
 527                         c0_c2_change = C0_C2_CHANGE_DISABLE;
 528                         csc_enable = v_CSC_ENABLE;
 529                 } else if ((data->enc_in_format == HDMI_COLORSPACE_YUV444) &&
 530                            (data->enc_out_format == HDMI_COLORSPACE_RGB)) {
 531                         csc_mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT;
 532                         auto_csc = AUTO_CSC_ENABLE;
 533                         c0_c2_change = C0_C2_CHANGE_DISABLE;
 534                         csc_enable = v_CSC_DISABLE;
 535                 }
 536         }
 537
 538         for (i = 0; i < 24; i++)
 539                 hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i,
 540                             coeff_csc[csc_mode][i]);
 541
 542         value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1);
 543         hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
 544         hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC |
 545                   m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) |
 546                   v_VIDEO_C0_C2_SWAP(c0_c2_change));
 547
 548         return 0;
 549 }
 550
 551 static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi,
 552                                          struct drm_display_mode *mode)
 553 {
 554         int value;
 555
 556         /* Set detail external video timing polarity and interlace mode */
 557         value = v_EXTERANL_VIDEO(1);
 558         value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
 559                  v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0);
 560         value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
 561                  v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0);
 562         value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
 563                  v_INETLACE(1) : v_INETLACE(0);
 564         hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value);
 565
 566         /* Set detail external video timing */
 567         value = mode->htotal;
 568         hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF);
 569         hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF);
 570
 571         value = mode->htotal - mode->hdisplay;
 572         hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF);
 573         hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF);
 574
 575         value = mode->hsync_start - mode->hdisplay;
 576         hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF);
 577         hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF);
 578
 579         value = mode->hsync_end - mode->hsync_start;
 580         hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF);
 581         hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF);
 582
 583         value = mode->vtotal;
 584         hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF);
 585         hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF);
 586
 587         value = mode->vtotal - mode->vdisplay;
 588         hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF);
 589
 590         value = mode->vsync_start - mode->vdisplay;
 591         hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF);
 592
 593         value = mode->vsync_end - mode->vsync_start;
 594         hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF);
 595
 596         return 0;
 597 }
 598
 599 static int inno_hdmi_setup(struct inno_hdmi *hdmi,
 600                            struct drm_display_mode *mode)
 601 {
 602         hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
 603
 604         hdmi->hdmi_data.enc_in_format = HDMI_COLORSPACE_RGB;
 605         hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB;
 606
 607         if ((hdmi->hdmi_data.vic == 6) || (hdmi->hdmi_data.vic == 7) ||
 608             (hdmi->hdmi_data.vic == 21) || (hdmi->hdmi_data.vic == 22) ||
 609             (hdmi->hdmi_data.vic == 2) || (hdmi->hdmi_data.vic == 3) ||
 610             (hdmi->hdmi_data.vic == 17) || (hdmi->hdmi_data.vic == 18))
 611                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
 612         else
 613                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
 614
 615         /* Mute video and audio output */
 616         hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
 617                   v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1));
 618
 619         /* Set HDMI Mode */
 620         hdmi_writeb(hdmi, HDMI_HDCP_CTRL,
 621                     v_HDMI_DVI(hdmi->hdmi_data.sink_is_hdmi));
 622
 623         inno_hdmi_config_video_timing(hdmi, mode);
 624
 625         inno_hdmi_config_video_csc(hdmi);
 626
 627         if (hdmi->hdmi_data.sink_is_hdmi) {
 628                 inno_hdmi_config_video_avi(hdmi, mode);
 629                 inno_hdmi_config_video_vsi(hdmi, mode);
 630         }
 631
 632         /*
 633          * When IP controller have configured to an accurate video
 634          * timing, then the TMDS clock source would be switched to
 635          * DCLK_LCDC, so we need to init the TMDS rate to mode pixel
 636          * clock rate, and reconfigure the DDC clock.
 637          */
 638         hdmi->tmds_rate = mode->clock * 1000;
 639         inno_hdmi_i2c_init(hdmi);
 640
 641         /* Unmute video and audio output */
 642         hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
 643                   v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0));
 644
 645         return 0;
 646 }
 647
 648 static void inno_hdmi_encoder_mode_set(struct drm_encoder *encoder,
 649                                        struct drm_display_mode *mode,
 650                                        struct drm_display_mode *adj_mode)
 651 {
 652         struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
 653
 654         inno_hdmi_setup(hdmi, adj_mode);
 655
 656         /* Store the display mode for plugin/DPMS poweron events */
 657         memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode));
 658 }
 659
 660 static void inno_hdmi_encoder_enable(struct drm_encoder *encoder)
 661 {
 662         struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
 663         inno_hdmi_init(hdmi);
 664
 665         inno_hdmi_set_pwr_mode(hdmi, NORMAL);
 666 }
 667
 668 static void inno_hdmi_encoder_disable(struct drm_encoder *encoder)
 669 {
 670         struct inno_hdmi *hdmi = to_inno_hdmi(encoder);
 671
 672         inno_hdmi_set_pwr_mode(hdmi, LOWER_PWR);
 673 }
 674
 675 static bool inno_hdmi_encoder_mode_fixup(struct drm_encoder *encoder,
 676                                          const struct drm_display_mode *mode,
 677                                          struct drm_display_mode *adj_mode)
 678 {
 679         return true;
 680 }
 681
 682 static int
 683 inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
 684                                struct drm_crtc_state *crtc_state,
 685                                struct drm_connector_state *conn_state)
 686 {
 687         //struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
 688
 689         //s->output_mode = ROCKCHIP_OUT_MODE_P888;
 690         //s->output_type = DRM_MODE_CONNECTOR_HDMIA;
 691
 692         return 0;
 693 }
 694
 695 static const struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = {
 696         .enable     = inno_hdmi_encoder_enable,
 697         .disable    = inno_hdmi_encoder_disable,
 698         .mode_fixup = inno_hdmi_encoder_mode_fixup,
 699         .mode_set   = inno_hdmi_encoder_mode_set,
 700         .atomic_check = inno_hdmi_encoder_atomic_check,
 701 };
 702
 703 static enum drm_connector_status
 704 inno_hdmi_connector_detect(struct drm_connector *connector, bool force)
 705 {
 706         struct inno_hdmi *hdmi = to_inno_hdmi(connector);
 707
 708         return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ?
 709                 connector_status_connected : connector_status_disconnected;
 710 }
 711
 712 static int inno_hdmi_connector_get_modes(struct drm_connector *connector)
 713 {
 714         struct inno_hdmi *hdmi = to_inno_hdmi(connector);
 715         struct edid *edid;
 716         int ret = 0;
 717
 718         if (!hdmi->ddc)
 719                 return 0;
 720
 721         edid = drm_get_edid(connector, hdmi->ddc);
 722         if (edid) {
 723                 hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid);
 724                 hdmi->hdmi_data.sink_has_audio = drm_detect_monitor_audio(edid);
 725                 drm_connector_update_edid_property(connector, edid);
 726                 ret = drm_add_edid_modes(connector, edid);
 727                 kfree(edid);
 728         }
 729
 730         return ret;
 731 }
 732
 733 static enum drm_mode_status
 734 inno_hdmi_connector_mode_valid(struct drm_connector *connector,
 735                                struct drm_display_mode *mode)
 736 {
 737         return MODE_OK;
 738 }
 739
 740 static int
 741 inno_hdmi_probe_single_connector_modes(struct drm_connector *connector,
 742                                        uint32_t maxX, uint32_t maxY)
 743 {
 744         return drm_helper_probe_single_connector_modes(connector, 1920, 1080);
 745 }
 746
 747 static void inno_hdmi_connector_destroy(struct drm_connector *connector)
 748 {
 749         drm_connector_unregister(connector);
 750         drm_connector_cleanup(connector);
 751 }
 752
 753 static const struct drm_connector_funcs inno_hdmi_connector_funcs = {
 754         .fill_modes = inno_hdmi_probe_single_connector_modes,
 755         .detect = inno_hdmi_connector_detect,
 756         .destroy = inno_hdmi_connector_destroy,
 757         .reset = drm_atomic_helper_connector_reset,
 758         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 759         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 760 };
 761
 762 static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = {
 763         .get_modes = inno_hdmi_connector_get_modes,
 764         .mode_valid = inno_hdmi_connector_mode_valid,
 765 };
 766
 767 static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi)
 768 {
 769         struct drm_encoder *encoder = &hdmi->encoder;
 770         struct device *dev = hdmi->dev;
 771
 772         encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
 773
 774         /*
 775          * If we failed to find the CRTC(s) which this encoder is
 776          * supposed to be connected to, it's because the CRTC has
 777          * not been registered yet.  Defer probing, and hope that
 778          * the required CRTC is added later.
 779          */
 780         if (encoder->possible_crtcs == 0)
 781                 return -EPROBE_DEFER;
 782
 783         drm_encoder_helper_add(encoder, &inno_hdmi_encoder_helper_funcs);
 784         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
 785
 786         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
 787
 788         drm_connector_helper_add(&hdmi->connector,
 789                                  &inno_hdmi_connector_helper_funcs);
 790         drm_connector_init_with_ddc(drm, &hdmi->connector,
 791                                     &inno_hdmi_connector_funcs,
 792                                     DRM_MODE_CONNECTOR_HDMIA,
 793                                     hdmi->ddc);
 794
 795         drm_connector_attach_encoder(&hdmi->connector, encoder);
 796
 797         return 0;
 798 }
 799
 800 static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi)
 801 {
 802         struct inno_hdmi_i2c *i2c = hdmi->i2c;
 803         u8 stat;
 804
 805         stat = hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1);
 806         if (!(stat & m_INT_EDID_READY))
 807                 return IRQ_NONE;
 808
 809         /* Clear HDMI EDID interrupt flag */
 810         hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
 811
 812         complete(&i2c->cmp);
 813
 814         return IRQ_HANDLED;
 815 }
 816
 817 static irqreturn_t inno_hdmi_hardirq(int irq, void *dev_id)
 818 {
 819         struct inno_hdmi *hdmi = dev_id;
 820         irqreturn_t ret = IRQ_NONE;
 821         u8 interrupt;
 822
 823         if (hdmi->i2c)
 824                 ret = inno_hdmi_i2c_irq(hdmi);
 825
 826         interrupt = hdmi_readb(hdmi, HDMI_STATUS);
 827         if (interrupt & m_INT_HOTPLUG) {
 828                 hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG);
 829                 ret = IRQ_WAKE_THREAD;
 830         }
 831
 832         return ret;
 833 }
 834
 835 static irqreturn_t inno_hdmi_irq(int irq, void *dev_id)
 836 {
 837         struct inno_hdmi *hdmi = dev_id;
 838
 839         drm_helper_hpd_irq_event(hdmi->connector.dev);
 840
 841         return IRQ_HANDLED;
 842 }
 843
 844 static int inno_hdmi_i2c_read(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
 845 {
 846         int length = msgs->len;
 847         u8 *buf = msgs->buf;
 848         int ret;
 849
 850         ret = wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10);
 851         if (!ret)
 852                 return -EAGAIN;
 853
 854         while (length--)
 855                 *buf++ = hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR);
 856
 857         return 0;
 858 }
 859
 860 static int inno_hdmi_i2c_write(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
 861 {
 862         /*
 863          * The DDC module only support read EDID message, so
 864          * we assume that each word write to this i2c adapter
 865          * should be the offset of EDID word address.
 866          */
 867         if ((msgs->len != 1) ||
 868             ((msgs->addr != DDC_ADDR) && (msgs->addr != DDC_SEGMENT_ADDR)))
 869                 return -EINVAL;
 870
 871         reinit_completion(&hdmi->i2c->cmp);
 872
 873         if (msgs->addr == DDC_SEGMENT_ADDR)
 874                 hdmi->i2c->segment_addr = msgs->buf[0];
 875         if (msgs->addr == DDC_ADDR)
 876                 hdmi->i2c->ddc_addr = msgs->buf[0];
 877
 878         /* Set edid fifo first addr */
 879         hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00);
 880
 881         /* Set edid word address 0x00/0x80 */
 882         hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
 883
 884         /* Set edid segment pointer */
 885         hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
 886
 887         return 0;
 888 }
 889
 890 static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap,
 891                               struct i2c_msg *msgs, int num)
 892 {
 893         struct inno_hdmi *hdmi = i2c_get_adapdata(adap);
 894         struct inno_hdmi_i2c *i2c = hdmi->i2c;
 895         int i, ret = 0;
 896
 897         mutex_lock(&i2c->lock);
 898
 899         /* Clear the EDID interrupt flag and unmute the interrupt */
 900         hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY);
 901         hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
 902
 903         for (i = 0; i < num; i++) {
 904                 DRM_DEV_DEBUG(hdmi->dev,
 905                               "xfer: num: %d/%d, len: %d, flags: %#x\n",
 906                               i + 1, num, msgs[i].len, msgs[i].flags);
 907
 908                 if (msgs[i].flags & I2C_M_RD)
 909                         ret = inno_hdmi_i2c_read(hdmi, &msgs[i]);
 910                 else
 911                         ret = inno_hdmi_i2c_write(hdmi, &msgs[i]);
 912
 913                 if (ret < 0)
 914                         break;
 915         }
 916
 917         if (!ret)
 918                 ret = num;
 919
 920         /* Mute HDMI EDID interrupt */
 921         hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
 922
 923         mutex_unlock(&i2c->lock);
 924
 925         return ret;
 926 }
 927
 928 static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter)
 929 {
 930         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 931 }
 932
 933 static const struct i2c_algorithm inno_hdmi_algorithm = {
 934         .master_xfer    = inno_hdmi_i2c_xfer,
 935         .functionality  = inno_hdmi_i2c_func,
 936 };
 937
 938 static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi)
 939 {
 940         struct i2c_adapter *adap;
 941         struct inno_hdmi_i2c *i2c;
 942         int ret;
 943
 944         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 945         if (!i2c)
 946                 return ERR_PTR(-ENOMEM);
 947
 948         mutex_init(&i2c->lock);
 949         init_completion(&i2c->cmp);
 950
 951         adap = &i2c->adap;
 952         adap->class = I2C_CLASS_DDC;
 953         adap->owner = THIS_MODULE;
 954         adap->dev.parent = hdmi->dev;
 955         adap->dev.of_node = hdmi->dev->of_node;
 956         adap->algo = &inno_hdmi_algorithm;
 957         strlcpy(adap->name, "Inno HDMI", sizeof(adap->name));
 958         i2c_set_adapdata(adap, hdmi);
 959
 960         ret = i2c_add_adapter(adap);
 961         if (ret) {
 962                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 963                 devm_kfree(hdmi->dev, i2c);
 964                 return ERR_PTR(ret);
 965         }
 966
 967         hdmi->i2c = i2c;
 968
 969         DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 970
 971         return adap;
 972 }
 973
 974
 975
 976
 977 #if 0
 978 static void inno_hdmi_get_edid(struct inno_hdmi *hdmi, unsigned int tmds_clk, unsigned char *data)
 979 {
 980         unsigned int i, ddc_div_msb, ddc_div_lsb;
 981         unsigned int ddc_scl = 100000; //scl:100k
 982
 983         //hdmi_write(0xff, 0x0c2);
 984         //hdmi_write(0xff, 0x0c4);
 985
 986         ddc_div_lsb = (tmds_clk/(4*ddc_scl))>>2;
 987         ddc_div_msb = (tmds_clk/(4*ddc_scl)) & 0x00ff;
 988         hdmi_writeb(hdmi, 0x04b,ddc_div_lsb);
 989         hdmi_writeb(hdmi, 0x04c,ddc_div_msb);
 990         /*enable EDID ready interrupt*/
 991         hdmi_writeb(hdmi,0x0c0,0x04 );
 992
 993         /*read e-edid segment 0x00 256 bytes steps*/
 994         /*set EDID FIFO initial address*/
 995         hdmi_writeb(hdmi,0x04f, 0x00);
 996         /*set EDID first word address, read first 128 byte*/
 997         hdmi_writeb(hdmi,0x04e, 0x00);
 998         /*set EDID segment 0x00 address*/
 999         hdmi_writeb(hdmi, 0x04d,0x00);
1000
1001         while(!(hdmi_readb(hdmi,0x0c1) & 0x4));
1002         hdmi_writeb(hdmi,0x0c1, 0x04); // clear ready interrupt: write 1 to bit2
1003
1004         /*read first 128 bytes*/
1005         for(i = 0; i < 128; i++)
1006         {
1007                 data[i] = hdmi_readb(hdmi,0x050);
1008         }
1009
1010         /*set EDID FIFO initial address again*/
1011         hdmi_writeb(hdmi,0x04f, 0x00);
1012         /*set EDID first word address, read last 128 byte*/
1013         hdmi_writeb(hdmi,0x04e, 0x80);
1014         /*set EDID segment 0x00 address*/
1015         hdmi_writeb(hdmi,0x04d, 0x00);
1016
1017         while(!(hdmi_readb(hdmi,0x0c1) & 0x4));
1018         hdmi_writeb(hdmi,0x0c1, 0x04); // clear ready interrupt: write 1 to bit2
1019
1020         /*read last 128 bytes*/
1021         for(i = 128; i < 256; i++)
1022         {
1023                 data[i] = hdmi_readb(hdmi,0x050);
1024         }
1025
1026 }
1027 #endif
1028
1029 static int inno_hdmi_get_clk_rst(struct device *dev, struct inno_hdmi *hdmi)
1030 {
1031         int ret;
1032         hdmi->sys_clk = devm_clk_get(dev, "sysclk");
1033         if (IS_ERR(hdmi->sys_clk)) {
1034                 DRM_DEV_ERROR(dev, "Unable to get HDMI sysclk clk\n");
1035                 return PTR_ERR(hdmi->sys_clk);
1036         }
1037         hdmi->mclk = devm_clk_get(dev, "mclk");
1038         if (IS_ERR(hdmi->mclk)) {
1039                 DRM_DEV_ERROR(dev, "Unable to get HDMI mclk clk\n");
1040                 return PTR_ERR(hdmi->mclk);
1041         }
1042         hdmi->bclk = devm_clk_get(dev, "bclk");
1043         if (IS_ERR(hdmi->bclk)) {
1044                 DRM_DEV_ERROR(dev, "Unable to get HDMI bclk clk\n");
1045                 return PTR_ERR(hdmi->bclk);
1046         }
1047         hdmi->tx_rst = reset_control_get_exclusive(dev, "hdmi_tx");
1048         if (IS_ERR(hdmi->tx_rst)) {
1049                 DRM_DEV_ERROR(dev, "Unable to get HDMI tx rst\n");
1050                 return PTR_ERR(hdmi->tx_rst);
1051         }
1052         return ret;
1053 }
1054
1055 static int inno_hdmi_en_clk_deas_rst(struct device *dev, struct inno_hdmi *hdmi)
1056 {
1057         int ret;
1058
1059         ret = clk_prepare_enable(hdmi->sys_clk);
1060         if (ret) {
1061                 DRM_DEV_ERROR(dev,
1062                               "Cannot enable HDMI sys clock: %d\n", ret);
1063                 return ret;
1064         }
1065         ret = clk_prepare_enable(hdmi->mclk);
1066         if (ret) {
1067                 DRM_DEV_ERROR(dev,
1068                               "Cannot enable HDMI mclk clock: %d\n", ret);
1069                 return ret;
1070         }
1071         ret = clk_prepare_enable(hdmi->bclk);
1072         if (ret) {
1073                 DRM_DEV_ERROR(dev,
1074                               "Cannot enable HDMI bclk clock: %d\n", ret);
1075                 return ret;
1076         }
1077
1078         ret = reset_control_deassert(hdmi->tx_rst);
1079         if (ret < 0) {
1080                 dev_err(dev, "failed to deassert tx_rst\n");
1081                 return ret;
1082     }
1083         return ret;
1084 }
1085
1086
1087 static int inno_hdmi_bind(struct device *dev, struct device *master,
1088                                  void *data)
1089 {
1090         struct platform_device *pdev = to_platform_device(dev);
1091         struct drm_device *drm = data;
1092         struct inno_hdmi *hdmi;
1093         struct resource *iores;
1094         int irq;
1095         int ret;
1096
1097         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1098         if (!hdmi)
1099                 return -ENOMEM;
1100
1101         hdmi->dev = dev;
1102         hdmi->drm_dev = drm;
1103
1104         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1105         hdmi->regs = devm_ioremap_resource(dev, iores);
1106         if (IS_ERR(hdmi->regs))
1107                 return PTR_ERR(hdmi->regs);
1108
1109         //pmic turn on
1110         udelay(100);
1111         udelay(100);
1112
1113 //20220531 clk rst interface support
1114 #if 1
1115         ret = inno_hdmi_get_clk_rst(dev, hdmi);
1116         //if (ret) {
1117         //      dev_err(dev, "failed to get clock or reset\n");
1118         //      return ret;
1119         //}
1120         ret = inno_hdmi_en_clk_deas_rst(dev, hdmi);
1121         //if (ret) {
1122         //      dev_err(dev, "failed to enable clock or deassert reset\n");
1123         //      return ret;
1124         //}
1125 #endif
1126 //20220531 clk rst interface support
1127
1128
1129         irq = platform_get_irq(pdev, 0);
1130         if (irq < 0) {
1131                 ret = irq;
1132                 goto err_disable_clk;
1133         }
1134         //inno_hdmi_set_pinmux();//20220601 disable for testing dts pinctrl setting
1135         //inno_hdmi_init(hdmi);
1136         //inno_hdmi_get_edid(hdmi,51200000, data);//20220525
1137         inno_hdmi_reset(hdmi);
1138
1139         hdmi->ddc = inno_hdmi_i2c_adapter(hdmi);
1140         if (IS_ERR(hdmi->ddc)) {
1141                 ret = PTR_ERR(hdmi->ddc);
1142                 hdmi->ddc = NULL;
1143                 goto err_disable_clk;
1144         }
1145
1146         hdmi->tmds_rate = 51200000;
1147
1148         inno_hdmi_i2c_init(hdmi);
1149
1150         ret = inno_hdmi_register(drm, hdmi);
1151         if (ret)
1152                 goto err_put_adapter;
1153
1154         dev_set_drvdata(dev, hdmi);
1155
1156         /* Unmute hotplug interrupt */
1157         hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1));
1158
1159         ret = devm_request_threaded_irq(dev, irq, inno_hdmi_hardirq,
1160                                         inno_hdmi_irq, IRQF_SHARED,
1161                                         dev_name(dev), hdmi);
1162         if (ret < 0)
1163                 goto err_cleanup_hdmi;
1164
1165         return 0;
1166 err_cleanup_hdmi:
1167         hdmi->connector.funcs->destroy(&hdmi->connector);
1168         hdmi->encoder.funcs->destroy(&hdmi->encoder);
1169 err_put_adapter:
1170         i2c_put_adapter(hdmi->ddc);
1171 err_disable_clk:
1172         //clk_disable_unprepare(hdmi->pclk);
1173         return ret;
1174 }
1175
1176 static void inno_hdmi_unbind(struct device *dev, struct device *master,
1177                              void *data)
1178 {
1179         struct inno_hdmi *hdmi = dev_get_drvdata(dev);
1180         int ret;
1181
1182         hdmi->connector.funcs->destroy(&hdmi->connector);
1183         hdmi->encoder.funcs->destroy(&hdmi->encoder);
1184
1185         i2c_put_adapter(hdmi->ddc);
1186
1187         ret = reset_control_assert(hdmi->tx_rst);
1188         if (ret < 0)
1189                 dev_err(dev, "failed to assert tx_rst\n");
1190
1191         clk_disable_unprepare(hdmi->sys_clk);
1192         clk_disable_unprepare(hdmi->mclk);
1193         clk_disable_unprepare(hdmi->bclk);
1194
1195         //pmic turn off
1196         #if 1
1197         udelay(100);
1198         #endif
1199         //pmic turn off
1200
1201 //      clk_disable_unprepare(hdmi->pclk);
1202 }
1203
1204 static const struct component_ops inno_hdmi_ops = {
1205         .bind   = inno_hdmi_bind,
1206         .unbind = inno_hdmi_unbind,
1207 };
1208
1209 static int inno_hdmi_probe(struct platform_device *pdev)
1210 {
1211         return component_add(&pdev->dev, &inno_hdmi_ops);
1212 }
1213
1214 static int inno_hdmi_remove(struct platform_device *pdev)
1215 {
1216         component_del(&pdev->dev, &inno_hdmi_ops);
1217
1218         return 0;
1219 }
1220
1221 static const struct of_device_id inno_hdmi_dt_ids[] = {
1222         { .compatible = "rockchip,rk3036-inno-hdmi",
1223         },
1224         {},
1225 };
1226 MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids);
1227
1228 struct platform_driver inno_hdmi_driver = {
1229         .probe  = inno_hdmi_probe,
1230         .remove = inno_hdmi_remove,
1231         .driver = {
1232                 .name = "innohdmi-rockchip",
1233                 .of_match_table = inno_hdmi_dt_ids,
1234         },
1235 };