drivers/gpu/drm/vc4/vc4_vec.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2016 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 SDTV module
   8  *
   9  * The VEC encoder generates PAL or NTSC composite video output.
  10  *
  11  * TV mode selection is done by an atomic property on the encoder,
  12  * because a drm_mode_modeinfo is insufficient to distinguish between
  13  * PAL and PAL-M or NTSC and NTSC-J.
  14  */
  15
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_edid.h>
  18 #include <drm/drm_panel.h>
  19 #include <drm/drm_probe_helper.h>
  20 #include <drm/drm_simple_kms_helper.h>
  21 #include <linux/clk.h>
  22 #include <linux/component.h>
  23 #include <linux/of_graph.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/pm_runtime.h>
  26
  27 #include "vc4_drv.h"
  28 #include "vc4_regs.h"
  29
  30 /* WSE Registers */
  31 #define VEC_WSE_RESET                   0xc0
  32
  33 #define VEC_WSE_CONTROL                 0xc4
  34 #define VEC_WSE_WSS_ENABLE              BIT(7)
  35
  36 #define VEC_WSE_WSS_DATA                0xc8
  37 #define VEC_WSE_VPS_DATA1               0xcc
  38 #define VEC_WSE_VPS_CONTROL             0xd0
  39
  40 /* VEC Registers */
  41 #define VEC_REVID                       0x100
  42
  43 #define VEC_CONFIG0                     0x104
  44 #define VEC_CONFIG0_YDEL_MASK           GENMASK(28, 26)
  45 #define VEC_CONFIG0_YDEL(x)             ((x) << 26)
  46 #define VEC_CONFIG0_CDEL_MASK           GENMASK(25, 24)
  47 #define VEC_CONFIG0_CDEL(x)             ((x) << 24)
  48 #define VEC_CONFIG0_SECAM_STD           BIT(21)
  49 #define VEC_CONFIG0_PBPR_FIL            BIT(18)
  50 #define VEC_CONFIG0_CHROMA_GAIN_MASK    GENMASK(17, 16)
  51 #define VEC_CONFIG0_CHROMA_GAIN_UNITY   (0 << 16)
  52 #define VEC_CONFIG0_CHROMA_GAIN_1_32    (1 << 16)
  53 #define VEC_CONFIG0_CHROMA_GAIN_1_16    (2 << 16)
  54 #define VEC_CONFIG0_CHROMA_GAIN_1_8     (3 << 16)
  55 #define VEC_CONFIG0_CBURST_GAIN_MASK    GENMASK(14, 13)
  56 #define VEC_CONFIG0_CBURST_GAIN_UNITY   (0 << 13)
  57 #define VEC_CONFIG0_CBURST_GAIN_1_128   (1 << 13)
  58 #define VEC_CONFIG0_CBURST_GAIN_1_64    (2 << 13)
  59 #define VEC_CONFIG0_CBURST_GAIN_1_32    (3 << 13)
  60 #define VEC_CONFIG0_CHRBW1              BIT(11)
  61 #define VEC_CONFIG0_CHRBW0              BIT(10)
  62 #define VEC_CONFIG0_SYNCDIS             BIT(9)
  63 #define VEC_CONFIG0_BURDIS              BIT(8)
  64 #define VEC_CONFIG0_CHRDIS              BIT(7)
  65 #define VEC_CONFIG0_PDEN                BIT(6)
  66 #define VEC_CONFIG0_YCDELAY             BIT(4)
  67 #define VEC_CONFIG0_RAMPEN              BIT(2)
  68 #define VEC_CONFIG0_YCDIS               BIT(2)
  69 #define VEC_CONFIG0_STD_MASK            (VEC_CONFIG0_SECAM_STD | GENMASK(1, 0))
  70 #define VEC_CONFIG0_NTSC_STD            0
  71 #define VEC_CONFIG0_PAL_BDGHI_STD       1
  72 #define VEC_CONFIG0_PAL_M_STD           2
  73 #define VEC_CONFIG0_PAL_N_STD           3
  74
  75 #define VEC_SCHPH                       0x108
  76 #define VEC_SOFT_RESET                  0x10c
  77 #define VEC_CLMP0_START                 0x144
  78 #define VEC_CLMP0_END                   0x148
  79
  80 /*
  81  * These set the color subcarrier frequency
  82  * if VEC_CONFIG1_CUSTOM_FREQ is enabled.
  83  *
  84  * VEC_FREQ1_0 contains the most significant 16-bit half-word,
  85  * VEC_FREQ3_2 contains the least significant 16-bit half-word.
  86  * 0x80000000 seems to be equivalent to the pixel clock
  87  * (which itself is the VEC clock divided by 8).
  88  *
  89  * Reference values (with the default pixel clock of 13.5 MHz):
  90  *
  91  * NTSC  (3579545.[45] Hz)     - 0x21F07C1F
  92  * PAL   (4433618.75 Hz)       - 0x2A098ACB
  93  * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3
  94  * PAL-N (3582056.25 Hz)       - 0x21F69446
  95  *
  96  * NOTE: For SECAM, it is used as the Dr center frequency,
  97  * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not;
  98  * that is specified as 4406250 Hz, which corresponds to 0x29C71C72.
  99  */
 100 #define VEC_FREQ3_2                     0x180
 101 #define VEC_FREQ1_0                     0x184
 102
 103 #define VEC_CONFIG1                     0x188
 104 #define VEC_CONFIG_VEC_RESYNC_OFF       BIT(18)
 105 #define VEC_CONFIG_RGB219               BIT(17)
 106 #define VEC_CONFIG_CBAR_EN              BIT(16)
 107 #define VEC_CONFIG_TC_OBB               BIT(15)
 108 #define VEC_CONFIG1_OUTPUT_MODE_MASK    GENMASK(12, 10)
 109 #define VEC_CONFIG1_C_Y_CVBS            (0 << 10)
 110 #define VEC_CONFIG1_CVBS_Y_C            (1 << 10)
 111 #define VEC_CONFIG1_PR_Y_PB             (2 << 10)
 112 #define VEC_CONFIG1_RGB                 (4 << 10)
 113 #define VEC_CONFIG1_Y_C_CVBS            (5 << 10)
 114 #define VEC_CONFIG1_C_CVBS_Y            (6 << 10)
 115 #define VEC_CONFIG1_C_CVBS_CVBS         (7 << 10)
 116 #define VEC_CONFIG1_DIS_CHR             BIT(9)
 117 #define VEC_CONFIG1_DIS_LUMA            BIT(8)
 118 #define VEC_CONFIG1_YCBCR_IN            BIT(6)
 119 #define VEC_CONFIG1_DITHER_TYPE_LFSR    0
 120 #define VEC_CONFIG1_DITHER_TYPE_COUNTER BIT(5)
 121 #define VEC_CONFIG1_DITHER_EN           BIT(4)
 122 #define VEC_CONFIG1_CYDELAY             BIT(3)
 123 #define VEC_CONFIG1_LUMADIS             BIT(2)
 124 #define VEC_CONFIG1_COMPDIS             BIT(1)
 125 #define VEC_CONFIG1_CUSTOM_FREQ         BIT(0)
 126
 127 #define VEC_CONFIG2                     0x18c
 128 #define VEC_CONFIG2_PROG_SCAN           BIT(15)
 129 #define VEC_CONFIG2_SYNC_ADJ_MASK       GENMASK(14, 12)
 130 #define VEC_CONFIG2_SYNC_ADJ(x)         (((x) / 2) << 12)
 131 #define VEC_CONFIG2_PBPR_EN             BIT(10)
 132 #define VEC_CONFIG2_UV_DIG_DIS          BIT(6)
 133 #define VEC_CONFIG2_RGB_DIG_DIS         BIT(5)
 134 #define VEC_CONFIG2_TMUX_MASK           GENMASK(3, 2)
 135 #define VEC_CONFIG2_TMUX_DRIVE0         (0 << 2)
 136 #define VEC_CONFIG2_TMUX_RG_COMP        (1 << 2)
 137 #define VEC_CONFIG2_TMUX_UV_YC          (2 << 2)
 138 #define VEC_CONFIG2_TMUX_SYNC_YC        (3 << 2)
 139
 140 #define VEC_INTERRUPT_CONTROL           0x190
 141 #define VEC_INTERRUPT_STATUS            0x194
 142
 143 /*
 144  * Db center frequency for SECAM; the clock for this is the same as for
 145  * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency.
 146  *
 147  * This is specified as 4250000 Hz, which corresponds to 0x284BDA13.
 148  * That is also the default value, so no need to set it explicitly.
 149  */
 150 #define VEC_FCW_SECAM_B                 0x198
 151 #define VEC_SECAM_GAIN_VAL              0x19c
 152
 153 #define VEC_CONFIG3                     0x1a0
 154 #define VEC_CONFIG3_HORIZ_LEN_STD       (0 << 0)
 155 #define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF (1 << 0)
 156 #define VEC_CONFIG3_SHAPE_NON_LINEAR    BIT(1)
 157
 158 #define VEC_STATUS0                     0x200
 159 #define VEC_MASK0                       0x204
 160
 161 #define VEC_CFG                         0x208
 162 #define VEC_CFG_SG_MODE_MASK            GENMASK(6, 5)
 163 #define VEC_CFG_SG_MODE(x)              ((x) << 5)
 164 #define VEC_CFG_SG_EN                   BIT(4)
 165 #define VEC_CFG_VEC_EN                  BIT(3)
 166 #define VEC_CFG_MB_EN                   BIT(2)
 167 #define VEC_CFG_ENABLE                  BIT(1)
 168 #define VEC_CFG_TB_EN                   BIT(0)
 169
 170 #define VEC_DAC_TEST                    0x20c
 171
 172 #define VEC_DAC_CONFIG                  0x210
 173 #define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x) ((x) << 24)
 174 #define VEC_DAC_CONFIG_DRIVER_CTRL(x)   ((x) << 16)
 175 #define VEC_DAC_CONFIG_DAC_CTRL(x)      (x)
 176
 177 #define VEC_DAC_MISC                    0x214
 178 #define VEC_DAC_MISC_VCD_CTRL_MASK      GENMASK(31, 16)
 179 #define VEC_DAC_MISC_VCD_CTRL(x)        ((x) << 16)
 180 #define VEC_DAC_MISC_VID_ACT            BIT(8)
 181 #define VEC_DAC_MISC_VCD_PWRDN          BIT(6)
 182 #define VEC_DAC_MISC_BIAS_PWRDN         BIT(5)
 183 #define VEC_DAC_MISC_DAC_PWRDN          BIT(2)
 184 #define VEC_DAC_MISC_LDO_PWRDN          BIT(1)
 185 #define VEC_DAC_MISC_DAC_RST_N          BIT(0)
 186
 187
 188 static char *vc4_vec_tv_norm;
 189
 190 struct vc4_vec_variant {
 191         u32 dac_config;
 192 };
 193
 194 /* General VEC hardware state. */
 195 struct vc4_vec {
 196         struct platform_device *pdev;
 197         const struct vc4_vec_variant *variant;
 198
 199         struct drm_encoder *encoder;
 200         struct drm_connector *connector;
 201
 202         void __iomem *regs;
 203
 204         struct clk *clock;
 205
 206         struct debugfs_regset32 regset;
 207 };
 208
 209 #define VEC_READ(offset) readl(vec->regs + (offset))
 210 #define VEC_WRITE(offset, val) writel(val, vec->regs + (offset))
 211
 212 /* VC4 VEC encoder KMS struct */
 213 struct vc4_vec_encoder {
 214         struct vc4_encoder base;
 215         struct vc4_vec *vec;
 216 };
 217
 218 static inline struct vc4_vec_encoder *
 219 to_vc4_vec_encoder(struct drm_encoder *encoder)
 220 {
 221         return container_of(encoder, struct vc4_vec_encoder, base.base);
 222 }
 223
 224 /* VC4 VEC connector KMS struct */
 225 struct vc4_vec_connector {
 226         struct drm_connector base;
 227         struct vc4_vec *vec;
 228
 229         /* Since the connector is attached to just the one encoder,
 230          * this is the reference to it so we can do the best_encoder()
 231          * hook.
 232          */
 233         struct drm_encoder *encoder;
 234 };
 235
 236 enum vc4_vec_tv_mode_id {
 237         VC4_VEC_TV_MODE_NTSC,
 238         VC4_VEC_TV_MODE_NTSC_J,
 239         VC4_VEC_TV_MODE_NTSC_443,
 240         VC4_VEC_TV_MODE_PAL,
 241         VC4_VEC_TV_MODE_PAL_M,
 242         VC4_VEC_TV_MODE_PAL_N,
 243         VC4_VEC_TV_MODE_PAL60,
 244         VC4_VEC_TV_MODE_SECAM,
 245 };
 246
 247 struct vc4_vec_tv_mode {
 248         const struct drm_display_mode *interlaced_mode;
 249         const struct drm_display_mode *progressive_mode;
 250         u32 config0;
 251         u32 config1;
 252         u32 custom_freq;
 253 };
 254
 255 static const struct debugfs_reg32 vec_regs[] = {
 256         VC4_REG32(VEC_WSE_CONTROL),
 257         VC4_REG32(VEC_WSE_WSS_DATA),
 258         VC4_REG32(VEC_WSE_VPS_DATA1),
 259         VC4_REG32(VEC_WSE_VPS_CONTROL),
 260         VC4_REG32(VEC_REVID),
 261         VC4_REG32(VEC_CONFIG0),
 262         VC4_REG32(VEC_SCHPH),
 263         VC4_REG32(VEC_CLMP0_START),
 264         VC4_REG32(VEC_CLMP0_END),
 265         VC4_REG32(VEC_FREQ3_2),
 266         VC4_REG32(VEC_FREQ1_0),
 267         VC4_REG32(VEC_CONFIG1),
 268         VC4_REG32(VEC_CONFIG2),
 269         VC4_REG32(VEC_INTERRUPT_CONTROL),
 270         VC4_REG32(VEC_INTERRUPT_STATUS),
 271         VC4_REG32(VEC_FCW_SECAM_B),
 272         VC4_REG32(VEC_SECAM_GAIN_VAL),
 273         VC4_REG32(VEC_CONFIG3),
 274         VC4_REG32(VEC_STATUS0),
 275         VC4_REG32(VEC_MASK0),
 276         VC4_REG32(VEC_CFG),
 277         VC4_REG32(VEC_DAC_TEST),
 278         VC4_REG32(VEC_DAC_CONFIG),
 279         VC4_REG32(VEC_DAC_MISC),
 280 };
 281
 282 static const struct drm_display_mode drm_mode_480i = {
 283         DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500,
 284                  720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
 285                  480, 480 + 7, 480 + 7 + 6, 525, 0,
 286                  DRM_MODE_FLAG_INTERLACE)
 287 };
 288
 289 static const struct drm_display_mode drm_mode_240p = {
 290         DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500,
 291                  720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
 292                  240, 240 + 3, 240 + 3 + 3, 262, 0, 0)
 293 };
 294
 295 static const struct drm_display_mode drm_mode_576i = {
 296         DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500,
 297                  720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
 298                  576, 576 + 4, 576 + 4 + 6, 625, 0,
 299                  DRM_MODE_FLAG_INTERLACE)
 300 };
 301
 302 static const struct drm_display_mode drm_mode_288p = {
 303         DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500,
 304                  720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
 305                  288, 288 + 2, 288 + 2 + 3, 312, 0, 0)
 306 };
 307
 308 static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
 309         [VC4_VEC_TV_MODE_NTSC] = {
 310                 .interlaced_mode = &drm_mode_480i,
 311                 .progressive_mode = &drm_mode_240p,
 312                 .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN,
 313                 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
 314         },
 315         [VC4_VEC_TV_MODE_NTSC_J] = {
 316                 .interlaced_mode = &drm_mode_480i,
 317                 .progressive_mode = &drm_mode_240p,
 318                 .config0 = VEC_CONFIG0_NTSC_STD,
 319                 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
 320         },
 321         [VC4_VEC_TV_MODE_NTSC_443] = {
 322                 /* NTSC with PAL chroma frequency */
 323                 .interlaced_mode = &drm_mode_480i,
 324                 .progressive_mode = &drm_mode_240p,
 325                 .config0 = VEC_CONFIG0_NTSC_STD,
 326                 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
 327                 .custom_freq = 0x2a098acb,
 328         },
 329         [VC4_VEC_TV_MODE_PAL] = {
 330                 .interlaced_mode = &drm_mode_576i,
 331                 .progressive_mode = &drm_mode_288p,
 332                 .config0 = VEC_CONFIG0_PAL_BDGHI_STD,
 333                 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
 334         },
 335         [VC4_VEC_TV_MODE_PAL_M] = {
 336                 .interlaced_mode = &drm_mode_480i,
 337                 .progressive_mode = &drm_mode_240p,
 338                 .config0 = VEC_CONFIG0_PAL_M_STD,
 339                 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
 340         },
 341         [VC4_VEC_TV_MODE_PAL_N] = {
 342                 .interlaced_mode = &drm_mode_576i,
 343                 .progressive_mode = &drm_mode_288p,
 344                 .config0 = VEC_CONFIG0_PAL_N_STD,
 345                 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
 346         },
 347         [VC4_VEC_TV_MODE_PAL60] = {
 348                 /* PAL-M with chroma frequency of regular PAL */
 349                 .interlaced_mode = &drm_mode_480i,
 350                 .progressive_mode = &drm_mode_240p,
 351                 .config0 = VEC_CONFIG0_PAL_M_STD,
 352                 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
 353                 .custom_freq = 0x2a098acb,
 354         },
 355         [VC4_VEC_TV_MODE_SECAM] = {
 356                 .interlaced_mode = &drm_mode_576i,
 357                 .progressive_mode = &drm_mode_288p,
 358                 .config0 = VEC_CONFIG0_SECAM_STD,
 359                 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
 360                 .custom_freq = 0x29c71c72,
 361         },
 362 };
 363
 364 static const char * const tv_mode_names[] = {
 365         [VC4_VEC_TV_MODE_NTSC] = "NTSC",
 366         [VC4_VEC_TV_MODE_NTSC_J] = "NTSC-J",
 367         [VC4_VEC_TV_MODE_NTSC_443] = "NTSC-443",
 368         [VC4_VEC_TV_MODE_PAL] = "PAL",
 369         [VC4_VEC_TV_MODE_PAL_M] = "PAL-M",
 370         [VC4_VEC_TV_MODE_PAL_N] = "PAL-N",
 371         [VC4_VEC_TV_MODE_PAL60] = "PAL60",
 372         [VC4_VEC_TV_MODE_SECAM] = "SECAM",
 373 };
 374
 375 enum vc4_vec_tv_mode_id
 376 vc4_vec_get_default_mode(struct drm_connector *connector)
 377 {
 378         int i;
 379
 380         if (vc4_vec_tv_norm) {
 381                 for (i = 0; i < ARRAY_SIZE(tv_mode_names); i++)
 382                         if (strcmp(vc4_vec_tv_norm, tv_mode_names[i]) == 0)
 383                                 return (enum vc4_vec_tv_mode_id) i;
 384         } else if (connector->cmdline_mode.specified &&
 385                    ((connector->cmdline_mode.refresh_specified &&
 386                      (connector->cmdline_mode.refresh == 25 ||
 387                       connector->cmdline_mode.refresh == 50)) ||
 388                     (!connector->cmdline_mode.refresh_specified &&
 389                      (connector->cmdline_mode.yres == 288 ||
 390                       connector->cmdline_mode.yres == 576)))) {
 391                 /*
 392                  * no explicitly specified TV norm; use PAL if a mode that
 393                  * looks like PAL has been specified on the command line
 394                  */
 395                 return VC4_VEC_TV_MODE_PAL;
 396         }
 397
 398         /* in all other cases, default to NTSC */
 399         return VC4_VEC_TV_MODE_NTSC;
 400 }
 401
 402 static enum drm_connector_status
 403 vc4_vec_connector_detect(struct drm_connector *connector, bool force)
 404 {
 405         return connector_status_unknown;
 406 }
 407
 408 static void vc4_vec_connector_destroy(struct drm_connector *connector)
 409 {
 410         drm_connector_unregister(connector);
 411         drm_connector_cleanup(connector);
 412 }
 413
 414 static int vc4_vec_connector_get_modes(struct drm_connector *connector)
 415 {
 416         struct drm_connector_state *state = connector->state;
 417         struct drm_display_mode *interlaced_mode, *progressive_mode;
 418
 419         interlaced_mode =
 420                 drm_mode_duplicate(connector->dev,
 421                                    vc4_vec_tv_modes[state->tv.mode].interlaced_mode);
 422         progressive_mode =
 423                 drm_mode_duplicate(connector->dev,
 424                                    vc4_vec_tv_modes[state->tv.mode].progressive_mode);
 425         if (!interlaced_mode || !progressive_mode) {
 426                 DRM_ERROR("Failed to create a new display mode\n");
 427                 drm_mode_destroy(connector->dev, interlaced_mode);
 428                 drm_mode_destroy(connector->dev, progressive_mode);
 429                 return -ENOMEM;
 430         }
 431
 432         if (connector->cmdline_mode.specified &&
 433             connector->cmdline_mode.refresh_specified &&
 434             !connector->cmdline_mode.interlace)
 435                 /* progressive mode set at boot, let's make it preferred */
 436                 progressive_mode->type |= DRM_MODE_TYPE_PREFERRED;
 437         else
 438                 /* otherwise, interlaced mode is preferred */
 439                 interlaced_mode->type |= DRM_MODE_TYPE_PREFERRED;
 440
 441         drm_mode_probed_add(connector, interlaced_mode);
 442         drm_mode_probed_add(connector, progressive_mode);
 443
 444         return 1;
 445 }
 446
 447 static void vc4_vec_connector_reset(struct drm_connector *connector)
 448 {
 449         drm_atomic_helper_connector_reset(connector);
 450         /* preserve TV standard */
 451         if (connector->state)
 452                 connector->state->tv.mode = vc4_vec_get_default_mode(connector);
 453 }
 454
 455 static int vc4_vec_connector_atomic_check(struct drm_connector *conn,
 456                                           struct drm_atomic_state *state)
 457 {
 458         struct drm_connector_state *old_state =
 459                 drm_atomic_get_old_connector_state(state, conn);
 460         struct drm_connector_state *new_state =
 461                 drm_atomic_get_new_connector_state(state, conn);
 462
 463         if (new_state->crtc && old_state->tv.mode != new_state->tv.mode) {
 464                 struct drm_crtc_state *crtc_state =
 465                         drm_atomic_get_new_crtc_state(state, new_state->crtc);
 466
 467                 crtc_state->mode_changed = true;
 468         }
 469
 470         return 0;
 471 }
 472
 473 static const struct drm_connector_funcs vc4_vec_connector_funcs = {
 474         .detect = vc4_vec_connector_detect,
 475         .fill_modes = drm_helper_probe_single_connector_modes,
 476         .destroy = vc4_vec_connector_destroy,
 477         .reset = vc4_vec_connector_reset,
 478         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 479         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 480 };
 481
 482 static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = {
 483         .get_modes = vc4_vec_connector_get_modes,
 484         .atomic_check = vc4_vec_connector_atomic_check,
 485 };
 486
 487 static struct drm_connector *vc4_vec_connector_init(struct drm_device *dev,
 488                                                     struct vc4_vec *vec)
 489 {
 490         struct drm_connector *connector = NULL;
 491         struct vc4_vec_connector *vec_connector;
 492
 493         vec_connector = devm_kzalloc(dev->dev, sizeof(*vec_connector),
 494                                      GFP_KERNEL);
 495         if (!vec_connector)
 496                 return ERR_PTR(-ENOMEM);
 497
 498         connector = &vec_connector->base;
 499         connector->interlace_allowed = true;
 500
 501         vec_connector->encoder = vec->encoder;
 502         vec_connector->vec = vec;
 503
 504         drm_connector_init(dev, connector, &vc4_vec_connector_funcs,
 505                            DRM_MODE_CONNECTOR_Composite);
 506         drm_connector_helper_add(connector, &vc4_vec_connector_helper_funcs);
 507
 508         drm_object_attach_property(&connector->base,
 509                                    dev->mode_config.tv_mode_property,
 510                                    vc4_vec_get_default_mode(connector));
 511
 512         drm_connector_attach_encoder(connector, vec->encoder);
 513
 514         return connector;
 515 }
 516
 517 static void vc4_vec_encoder_disable(struct drm_encoder *encoder)
 518 {
 519         struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);
 520         struct vc4_vec *vec = vc4_vec_encoder->vec;
 521         int ret;
 522
 523         VEC_WRITE(VEC_CFG, 0);
 524         VEC_WRITE(VEC_DAC_MISC,
 525                   VEC_DAC_MISC_VCD_PWRDN |
 526                   VEC_DAC_MISC_BIAS_PWRDN |
 527                   VEC_DAC_MISC_DAC_PWRDN |
 528                   VEC_DAC_MISC_LDO_PWRDN);
 529
 530         clk_disable_unprepare(vec->clock);
 531
 532         ret = pm_runtime_put(&vec->pdev->dev);
 533         if (ret < 0) {
 534                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 535                 return;
 536         }
 537 }
 538
 539 static void vc4_vec_encoder_enable(struct drm_encoder *encoder)
 540 {
 541         struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder);
 542         struct vc4_vec *vec = vc4_vec_encoder->vec;
 543         unsigned int tv_mode = vec->connector->state->tv.mode;
 544         int ret;
 545
 546         ret = pm_runtime_get_sync(&vec->pdev->dev);
 547         if (ret < 0) {
 548                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 549                 return;
 550         }
 551
 552         /*
 553          * We need to set the clock rate each time we enable the encoder
 554          * because there's a chance we share the same parent with the HDMI
 555          * clock, and both drivers are requesting different rates.
 556          * The good news is, these 2 encoders cannot be enabled at the same
 557          * time, thus preventing incompatible rate requests.
 558          */
 559         ret = clk_set_rate(vec->clock, 108000000);
 560         if (ret) {
 561                 DRM_ERROR("Failed to set clock rate: %d\n", ret);
 562                 return;
 563         }
 564
 565         ret = clk_prepare_enable(vec->clock);
 566         if (ret) {
 567                 DRM_ERROR("Failed to turn on core clock: %d\n", ret);
 568                 return;
 569         }
 570
 571         /* Reset the different blocks */
 572         VEC_WRITE(VEC_WSE_RESET, 1);
 573         VEC_WRITE(VEC_SOFT_RESET, 1);
 574
 575         /* Disable the CGSM-A and WSE blocks */
 576         VEC_WRITE(VEC_WSE_CONTROL, 0);
 577
 578         /* Write config common to all modes. */
 579
 580         /*
 581          * Color subcarrier phase: phase = 360 * SCHPH / 256.
 582          * 0x28 <=> 39.375 deg.
 583          */
 584         VEC_WRITE(VEC_SCHPH, 0x28);
 585
 586         /*
 587          * Reset to default values.
 588          */
 589         VEC_WRITE(VEC_CLMP0_START, 0xac);
 590         VEC_WRITE(VEC_CLMP0_END, 0xec);
 591         VEC_WRITE(VEC_CONFIG2,
 592                   VEC_CONFIG2_UV_DIG_DIS |
 593                   VEC_CONFIG2_RGB_DIG_DIS |
 594                   ((encoder->crtc->state->adjusted_mode.flags &
 595                     DRM_MODE_FLAG_INTERLACE) ? 0 : VEC_CONFIG2_PROG_SCAN));
 596         VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD);
 597         VEC_WRITE(VEC_DAC_CONFIG, vec->variant->dac_config);
 598
 599         /* Mask all interrupts. */
 600         VEC_WRITE(VEC_MASK0, 0);
 601
 602         VEC_WRITE(VEC_CONFIG0, vc4_vec_tv_modes[tv_mode].config0);
 603         VEC_WRITE(VEC_CONFIG1, vc4_vec_tv_modes[tv_mode].config1);
 604         if (vc4_vec_tv_modes[tv_mode].custom_freq != 0) {
 605                 VEC_WRITE(VEC_FREQ3_2,
 606                           (vc4_vec_tv_modes[tv_mode].custom_freq >> 16) &
 607                           0xffff);
 608                 VEC_WRITE(VEC_FREQ1_0,
 609                           vc4_vec_tv_modes[tv_mode].custom_freq & 0xffff);
 610         }
 611
 612         VEC_WRITE(VEC_DAC_MISC,
 613                   VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N);
 614         VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN);
 615 }
 616
 617
 618 static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,
 619                                         struct drm_crtc_state *crtc_state,
 620                                         struct drm_connector_state *conn_state)
 621 {
 622         const struct drm_display_mode *reference_mode =
 623                 vc4_vec_tv_modes[conn_state->tv.mode].interlaced_mode;
 624
 625         if (crtc_state->adjusted_mode.crtc_clock != reference_mode->clock ||
 626             crtc_state->adjusted_mode.crtc_htotal != reference_mode->htotal ||
 627             crtc_state->adjusted_mode.crtc_hdisplay % 4 != 0 ||
 628             crtc_state->adjusted_mode.crtc_hsync_end -
 629                     crtc_state->adjusted_mode.crtc_hsync_start < 1)
 630                 return -EINVAL;
 631
 632         switch (reference_mode->vtotal) {
 633         case 525:
 634                 if (crtc_state->adjusted_mode.crtc_vdisplay < 1 ||
 635                     crtc_state->adjusted_mode.crtc_vdisplay > 253 ||
 636                     crtc_state->adjusted_mode.crtc_vsync_start -
 637                             crtc_state->adjusted_mode.crtc_vdisplay < 1 ||
 638                     crtc_state->adjusted_mode.crtc_vsync_end -
 639                             crtc_state->adjusted_mode.crtc_vsync_start != 3 ||
 640                     crtc_state->adjusted_mode.crtc_vtotal -
 641                             crtc_state->adjusted_mode.crtc_vsync_end < 4 ||
 642                     crtc_state->adjusted_mode.crtc_vtotal > 262)
 643                         return -EINVAL;
 644
 645                 if ((crtc_state->adjusted_mode.flags &
 646                      DRM_MODE_FLAG_INTERLACE) &&
 647                     (crtc_state->adjusted_mode.vdisplay % 2 != 0 ||
 648                      crtc_state->adjusted_mode.vsync_start % 2 != 1 ||
 649                      crtc_state->adjusted_mode.vsync_end % 2 != 1 ||
 650                      crtc_state->adjusted_mode.vtotal % 2 != 1))
 651                         return -EINVAL;
 652
 653                 /* progressive mode is hard-wired to 262 total lines */
 654                 if (!(crtc_state->adjusted_mode.flags &
 655                       DRM_MODE_FLAG_INTERLACE) &&
 656                     crtc_state->adjusted_mode.crtc_vtotal != 262)
 657                         return -EINVAL;
 658
 659                 break;
 660
 661         case 625:
 662                 if (crtc_state->adjusted_mode.crtc_vdisplay < 1 ||
 663                     crtc_state->adjusted_mode.crtc_vdisplay > 305 ||
 664                     crtc_state->adjusted_mode.crtc_vsync_start -
 665                             crtc_state->adjusted_mode.crtc_vdisplay < 1 ||
 666                     crtc_state->adjusted_mode.crtc_vsync_end -
 667                             crtc_state->adjusted_mode.crtc_vsync_start != 3 ||
 668                     crtc_state->adjusted_mode.crtc_vtotal -
 669                             crtc_state->adjusted_mode.crtc_vsync_end < 2 ||
 670                     crtc_state->adjusted_mode.crtc_vtotal > 312)
 671                         return -EINVAL;
 672
 673                 if ((crtc_state->adjusted_mode.flags &
 674                      DRM_MODE_FLAG_INTERLACE) &&
 675                     (crtc_state->adjusted_mode.vdisplay % 2 != 0 ||
 676                      crtc_state->adjusted_mode.vsync_start % 2 != 0 ||
 677                      crtc_state->adjusted_mode.vsync_end % 2 != 0 ||
 678                      crtc_state->adjusted_mode.vtotal % 2 != 1))
 679                         return -EINVAL;
 680
 681                 /* progressive mode is hard-wired to 312 total lines */
 682                 if (!(crtc_state->adjusted_mode.flags &
 683                       DRM_MODE_FLAG_INTERLACE) &&
 684                     crtc_state->adjusted_mode.crtc_vtotal != 312)
 685                         return -EINVAL;
 686
 687                 break;
 688
 689         default:
 690                 return -EINVAL;
 691         }
 692
 693         return 0;
 694 }
 695
 696 static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = {
 697         .disable = vc4_vec_encoder_disable,
 698         .enable = vc4_vec_encoder_enable,
 699         .atomic_check = vc4_vec_encoder_atomic_check,
 700 };
 701
 702 static const struct vc4_vec_variant bcm2835_vec_variant = {
 703         .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0xc) |
 704                       VEC_DAC_CONFIG_DRIVER_CTRL(0xc) |
 705                       VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46)
 706 };
 707
 708 static const struct vc4_vec_variant bcm2711_vec_variant = {
 709         .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0x0) |
 710                       VEC_DAC_CONFIG_DRIVER_CTRL(0x80) |
 711                       VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x61)
 712 };
 713
 714 static const struct of_device_id vc4_vec_dt_match[] = {
 715         { .compatible = "brcm,bcm2835-vec", .data = &bcm2835_vec_variant },
 716         { .compatible = "brcm,bcm2711-vec", .data = &bcm2711_vec_variant },
 717         { /* sentinel */ },
 718 };
 719
 720 static int vc4_vec_bind(struct device *dev, struct device *master, void *data)
 721 {
 722         struct platform_device *pdev = to_platform_device(dev);
 723         struct drm_device *drm = dev_get_drvdata(master);
 724         struct vc4_dev *vc4 = to_vc4_dev(drm);
 725         struct vc4_vec *vec;
 726         struct vc4_vec_encoder *vc4_vec_encoder;
 727         int ret;
 728
 729         ret = drm_mode_create_tv_properties(drm, ARRAY_SIZE(tv_mode_names),
 730                                             tv_mode_names);
 731         if (ret)
 732                 return ret;
 733
 734         vec = devm_kzalloc(dev, sizeof(*vec), GFP_KERNEL);
 735         if (!vec)
 736                 return -ENOMEM;
 737
 738         vc4_vec_encoder = devm_kzalloc(dev, sizeof(*vc4_vec_encoder),
 739                                        GFP_KERNEL);
 740         if (!vc4_vec_encoder)
 741                 return -ENOMEM;
 742         vc4_vec_encoder->base.type = VC4_ENCODER_TYPE_VEC;
 743         vc4_vec_encoder->vec = vec;
 744         vec->encoder = &vc4_vec_encoder->base.base;
 745
 746         vec->pdev = pdev;
 747         vec->variant = (const struct vc4_vec_variant *)
 748                 of_device_get_match_data(dev);
 749         vec->regs = vc4_ioremap_regs(pdev, 0);
 750         if (IS_ERR(vec->regs))
 751                 return PTR_ERR(vec->regs);
 752         vec->regset.base = vec->regs;
 753         vec->regset.regs = vec_regs;
 754         vec->regset.nregs = ARRAY_SIZE(vec_regs);
 755
 756         vec->clock = devm_clk_get(dev, NULL);
 757         if (IS_ERR(vec->clock)) {
 758                 ret = PTR_ERR(vec->clock);
 759                 if (ret != -EPROBE_DEFER)
 760                         DRM_ERROR("Failed to get clock: %d\n", ret);
 761                 return ret;
 762         }
 763
 764         pm_runtime_enable(dev);
 765
 766         drm_simple_encoder_init(drm, vec->encoder, DRM_MODE_ENCODER_TVDAC);
 767         drm_encoder_helper_add(vec->encoder, &vc4_vec_encoder_helper_funcs);
 768
 769         vec->connector = vc4_vec_connector_init(drm, vec);
 770         if (IS_ERR(vec->connector)) {
 771                 ret = PTR_ERR(vec->connector);
 772                 goto err_destroy_encoder;
 773         }
 774
 775         dev_set_drvdata(dev, vec);
 776
 777         vc4->vec = vec;
 778
 779         vc4_debugfs_add_regset32(drm, "vec_regs", &vec->regset);
 780
 781         return 0;
 782
 783 err_destroy_encoder:
 784         drm_encoder_cleanup(vec->encoder);
 785         pm_runtime_disable(dev);
 786
 787         return ret;
 788 }
 789
 790 static void vc4_vec_unbind(struct device *dev, struct device *master,
 791                            void *data)
 792 {
 793         struct drm_device *drm = dev_get_drvdata(master);
 794         struct vc4_dev *vc4 = to_vc4_dev(drm);
 795         struct vc4_vec *vec = dev_get_drvdata(dev);
 796
 797         vc4_vec_connector_destroy(vec->connector);
 798         drm_encoder_cleanup(vec->encoder);
 799         pm_runtime_disable(dev);
 800
 801         vc4->vec = NULL;
 802 }
 803
 804 static const struct component_ops vc4_vec_ops = {
 805         .bind   = vc4_vec_bind,
 806         .unbind = vc4_vec_unbind,
 807 };
 808
 809 static int vc4_vec_dev_probe(struct platform_device *pdev)
 810 {
 811         return component_add(&pdev->dev, &vc4_vec_ops);
 812 }
 813
 814 static int vc4_vec_dev_remove(struct platform_device *pdev)
 815 {
 816         component_del(&pdev->dev, &vc4_vec_ops);
 817         return 0;
 818 }
 819
 820 struct platform_driver vc4_vec_driver = {
 821         .probe = vc4_vec_dev_probe,
 822         .remove = vc4_vec_dev_remove,
 823         .driver = {
 824                 .name = "vc4_vec",
 825                 .of_match_table = vc4_vec_dt_match,
 826         },
 827 };
 828
 829 module_param_named(tv_norm, vc4_vec_tv_norm, charp, 0600);
 830 MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
 831                  "\t\tSupported: NTSC, NTSC-J, NTSC-443, PAL, PAL-M, PAL-N,\n"
 832                  "\t\t\tPAL60, SECAM.\n"
 833                  "\t\tDefault: PAL if a 50 Hz mode has been set via video=,\n"
 834                  "\t\t\tNTSC otherwise");